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feat(tc): add memory node in the device tree

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With new TC revisions, memory banks move around which requires an update
in platform_def. It also requires an update in the device tree which
doesn't come naturally. To avoid this, add the memory node such that it
uses the macros defined in platform_def.

By doing this we can put u-boot out of its misery in trying to come up
with the correct memory node and tf-a's device tree becomes complete.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ia92cc6931abb12be2856ac3fb1455e4f3005b326
This commit is contained in:
Boyan Karatotev 2023-12-04 16:09:14 +00:00
parent 638e4a92d8
commit 5ee4deb8e6
3 changed files with 20 additions and 6 deletions
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11
fdts/tc.dts
View file

@ -348,6 +348,13 @@
};
};
memory {
device_type = "memory";
reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>,
<HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE)
HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@ -367,11 +374,11 @@
sram: sram@6000000 {
compatible = "mmio-sram";
reg = <0x0 0x06000000 0x0 0x8000>;
reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x06000000 0x8000>;
ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>;
cpu_scp_scmi_mem: scp-shmem@0 {
compatible = "arm,scmi-shmem";

5
include/lib/utils_def.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -53,6 +53,9 @@
#define GENMASK GENMASK_32
#endif
#define HI(addr) (addr >> 32)
#define LO(addr) (addr & 0xffffffff)
/*
* This variant of div_round_up can be used in macro definition but should not
* be used in C code as the `div` parameter is evaluated twice.

10
plat/arm/board/tc/include/platform_def.h
View file

@ -44,7 +44,7 @@
*/
#define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
TC_TZC_DRAM1_SIZE)
#define TC_TZC_DRAM1_SIZE 96 * SZ_1M /* 96 MB */
#define TC_TZC_DRAM1_SIZE (96 * SZ_1M) /* 96 MB */
#define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \
TC_TZC_DRAM1_SIZE - 1)
@ -52,8 +52,8 @@
#define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
ARM_TZC_DRAM1_SIZE - \
TC_TZC_DRAM1_SIZE)
#define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + \
TC_NS_DRAM1_SIZE - 1)
#define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - 1)
/*
* Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure)
@ -225,6 +225,10 @@
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
#define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL)
#define TC_NS_MTE_SIZE (256 * SZ_1M)
/* the SCP puts the carveout at the end of DRAM2 */
#define TC_NS_DRAM2_SIZE (PLAT_ARM_DRAM2_SIZE - TC_NS_MTE_SIZE)
#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \
INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \