The code in the AMD-Xilinx platform for Versal and Versal NET is being
refactored to move the plat_get_syscnt_freq2() function to a common
file. This common function is utilized for obtaining the CPU clock
frequency from the platform.
Change-Id: I7a4c3fa43a2941d51cacd259c57b24e545aea848
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Refactor, the macro named VERSAL_NET_IOU_SCNTRS is being renamed to a more
generic macro name, which will be used in common code to enable reuse
across various platforms.
Change-Id: I548437e0fe2d73b196468bc92029f8099ea1f8d1
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Refactor the system counter configuration into the
syscnt_freq_config_setup() function as it involves timestamp and
system counter configuration, which requires early configuration for
clock setup and read the value of the IOU_SCNTRS_BASE_FREQ register
using mmio_read_32() to determine the counter frequency.
If the counter frequency is zero, the system will set the default CPU
clocks constants in TF-A and displays message. However, if the counter
frequency is non-zero, the program will return the value stored in the
IOU_SCNTRS_BASE_FREQ register.
The issue lies in dcc_status_timeout(),function verifying timeout
status, particularly within timeout_cnt_us2cnt(), converting
microseconds to counter ticks using read_cntfrq_el0(), which returns
zero. timeout_elapsed() then checks if the current counter from
read_cntpct_el0() exceeds the expiration count, reached to timeout.
After the function set_cnt_freq() writes into the counter frequency
register, the function timeout_cnt_us2cnt() is used to obtain the
appropriate counter ticks. Subsequently, the function timeout_elapsed()
checks whether the current counter value read_cntpct_el0() has
exceeded the specified expiration count. If it has, this indicates
that the timeout has lapsed.
Change-Id: Ib9ed3493d22f23c832f8bb7d11c4f727fe1ebe3c
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
The set_cnt_freq() function is introduced to configure the counter
frequency register.If the counter frequency register is zero, it writes
the output of plat_get_syscnt_freq2() the cpu_clocks to the counter
frequency register.
According to the design specifications provided for Versal, the
lpd_data.cdo file contains a mask_write operation for register
0xFF140020 (base_frequency_ID_register) to set it to 0x5f5e100,
configuring it for a 100MHz clock frequency.
Reading the value of the IOU_SCNTRS_BASE_FREQ register using
mmio_read_32() to determine the counter frequency. If the counter
frequency is zero, the system will set the default CPU clocks constants
in TF-A and displays message. However, if the counter frequency is
non-zero, the program will return the value stored in the
IOU_SCNTRS_BASE_FREQ register.
The issue lies in dcc_status_timeout(),function verifying timeout
status, particularly within timeout_cnt_us2cnt(), converting
microseconds to counter ticks using read_cntfrq_el0(), which returns
zero. timeout_elapsed() then checks if the current counter from
read_cntpct_el0()exceeds the expiration count, denoting timeout.
After the function set_cnt_freq() writes into the counter frequency
register, the function timeout_cnt_us2cnt() is used to obtain the
appropriate counter ticks. Subsequently, the function timeout_elapsed()
checks whether the current counter value read_cntpct_el0() has
exceeded the specified expiration count. If it has, this indicates
that the timeout has lapsed.
Change-Id: I8f2f4d804b5aefa6f92083d831a5ebfade384294
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Use unsigned long values for __aarch64__ version of SZ_* macros.
This allows using masks with ~SZ_* without losing the 32 upper bits.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ie485fad65088df17e6c489ebb3159220d6add647
This patch provides a reporting functionality to display the memory
consumed by the context in each security state and for each exception
level. Flag PLATFORM_REPORT_CTX_MEM_USE enables or disables this
feature.
Change-Id: I1515366bf87561dcedf2b3206be167804df681d4
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
New build option CTX_INCLUDE_MPAM_REGS is added to select
if the firmware needs to save the MPAM EL2 registers during world
switches. This option is currently disabled as MPAM is only
enabled for NS world.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie2e5e184cdb65f7e1a98d8fe81590253fd859679
* changes:
feat(intel): support QSPI ECC Linux for Agilex
feat(intel): support QSPI ECC Linux for N5X
feat(intel): support QSPI ECC Linux for Stratix10
feat(intel): add in QSPI ECC for Linux
The same was done for other platforms: stm32mp1, tc before in
commit 034a2e3ef8 ('refactor(fiptool):
move plat_fiptool.mk to tools')
Additionally this will make ignore generated files:
Untracked files:
plat/arm/board/juno/fip/plat_def_uuid_config.d
plat/arm/board/juno/fip/plat_def_uuid_config.o
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Change-Id: Ia5f1082fcd6d9dfc0be012759493e61ddb869956
Update from INFO to VERBOSE when print out debug message.
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Iefdbd44e711c0fd589bef454b42754cf9e3cd391
After a calibration we cannot trust the DDR content. Let's explicitly
clear the DDR content using the built-in scrubber in this case.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I6f429623f76a21f61f85efbb660cf65d99c04f56
Due to design issue, updated system counter back to hardcoded 400MHz
Change-Id: Id85b2541880fac88b2a9a0a46b27b0a0da0eed6d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Using mpu_peri as the clock source will caused the system
timer vary. System timer shall get from a static clock
source.
L4 and L3 clock are both the same at the moment.
There shall be a hardware update to differentiate the clock pll.
To keep this as dormant function for now.
Change-Id: I4d253e2f24a74cbec59bfcbf0e8547abbe3643a8
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Add QSPI ECC new opcodes for Linux to access to SDM register
Change-Id: I548e30340320ae2c2c9d60d20b218ee844516d64
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Add QSPI ECC new opcodes for Linux to access to SDM register
Change-Id: I65c7fd1bfc21baa6c45d9f8a0ee9618e6061e8d7
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Add QSPI ECC new opcodes for Linux to access to SDM register
Change-Id: I1cdacc0f10dfa2a969f0bc5086277fd9081d02e2
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Add QSPI ECC new opcodes for Linux to access to SDM register
Change-Id: If9ac35afdddb91db6bad6b474060cd001f6d89e6
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Remap base address for SDM to access DRAM.
Change-Id: If064bd1ff4571d3217b136d9b5ebbfdecb68231e
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
tf.org-wide documents have been migrated away from
developer.trustedfirmware.org, because the latter will be
decomissioned at some point in the future. These documents are now
hosted in a new 'tf_docs' repository hosted on Github [1] and can be
easily browsed through a new ReadTheDocs website at [2].
Update all relevant links in TF-A documentation to refer to [2].
[1] https://github.com/TrustedFirmware/tf_docs
[2] https://trusted-firmware-docs.readthedocs.io/
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Ib9d39c36250a05754fe5e46cb6f3044ecb776534
Cortex X3 erratum 2743088 is a Cat B erratum that applies to all
revisions <= r1p1 and is fixed in r1p2. The workaround is to add a DSB
instruction before the ISB of the powerdown code sequence specified in
the TRM.
SDEN documentation: https://developer.arm.com/documentation/2055130
Change-Id: I2c8577e3ca0781af8b1c3912e577d3bd77f92709
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Add information about Versal platform for ERRATA_ABI_SUPPORT and
provide the build commands.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I8466ea446814f888ae56f5cbb7bbdc06099d54f8
The errata ABI feature-specific build flag, the flag enabling CPUs
in the CPU list, and the flags testing non-ARM interconnect-based
errata when enabled from a platform level are added to the AMD-Xilinx
Versal platform makefile to assess the errata ABI feature
implementation.
ERRATA_ABI_SUPPORT : Boolean option to enable support for Errata
management firmware interface for the BL31 image. By default,
its disabled set to zero.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I54cda23d699abc0782f44172c28933f5cbb010b8
Currently, the registers which are maintained per-world, does not
take into account the reset value while configuring the context for
the respective world.
This leads to an issue, wherein the register retains the same value
across world switch, which is an error.
This patch addresses this problem, by configuring the register
(cptr_el3) precisely according to the world, the cpu is in
execution via resetting it before initializing the world specific context.
Change-Id: I592d82af373155fca67eed109c199341c305f0b9
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Cortex-A520 erratum 2858100 is a Cat B erratum that applies to
all revisions <=r0p1 and is still open. The workaround is to
set bit[29] of CPUACTLR_EL1.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5a07163f919352583b03328abd5659bf7b268677
Define new transfer entry TL_TAG_OPTEE_PAGABLE_PART for OP-TEE.
Add API for achieving handoff args from transfer entries.
Add API for dumping the transfer list.
Add tl->flags, tl->reserved and TL_FLAGS_HAS_CHECKSUM to align to
the spec update.
Update TL signature to 4a0f_b10b to align to the spec update.
Minor fixes for the coding and comment style.
Change-Id: I0e159672e4ef4c50576f70b82e1b7bae08407acc
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
SDMMC is 1 of the boot source for Agilex5 and legacy products.
By enabling this, ATF is able to read out the DTB binary and
loaded it to DDR for Linux boot.
Change-Id: Ida303fb43ea63013a08083ce65952c5ad4e28f93
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Linux RAS shall handle the SEU error received from SDM and report
an error message to user
Change-Id: I89181a388063ce9bd6f56b45b1851ccb08582437
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Update DDR range checking for Agilex when total max size of
DRAM_BASE and DRAM_SIZE overflow unsigned 64bit.
Change-Id: Iaecfa5daae48da0af46cc1831d10c0e6a79613c2
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
The src addr and dest addr of fcs functions are not checked against
their valid ddr range. Thus adding the ddr range checking to avoid
overlap/overwritten ddr address.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9b4d4155dd16d9d5d36e0c91e4a2600c17867daf
