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build(mpam): add new build option CTX_INCLUDE_MPAM_REGS

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New build option CTX_INCLUDE_MPAM_REGS is added to select
if the firmware needs to save the MPAM EL2 registers during world
switches. This option is currently disabled as MPAM is only
enabled for NS world.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie2e5e184cdb65f7e1a98d8fe81590253fd859679
This commit is contained in:
Arvind Ram Prakash 2023-10-06 14:35:21 -05:00
parent 5551264910
commit 9acff28ae4
5 changed files with 68 additions and 16 deletions
Makefile
docs/getting_started
build-options.rst
include/lib/el3_runtime/aarch64
context.h
lib/el3_runtime/aarch64
context_mgmt.c
make_helpers
defaults.mk

2
Makefile
View file

@ -1170,6 +1170,7 @@ $(eval $(call assert_booleans,\
CTX_INCLUDE_AARCH32_REGS \
CTX_INCLUDE_FPREGS \
CTX_INCLUDE_EL2_REGS \
CTX_INCLUDE_MPAM_REGS \
DEBUG \
DYN_DISABLE_AUTH \
EL3_EXCEPTION_HANDLING \
@ -1320,6 +1321,7 @@ $(eval $(call add_defines,\
CTX_INCLUDE_AARCH32_REGS \
CTX_INCLUDE_FPREGS \
CTX_INCLUDE_PAUTH_REGS \
CTX_INCLUDE_MPAM_REGS \
EL3_EXCEPTION_HANDLING \
CTX_INCLUDE_MTE_REGS \
CTX_INCLUDE_EL2_REGS \

5
docs/getting_started/build-options.rst
View file

@ -180,6 +180,11 @@ Common build options
registers to be included when saving and restoring the CPU context. Default
is 0.
- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the
Memory System Resource Partitioning and Monitoring (MPAM)
registers to be included when saving and restoring the CPU context.
Default is '0'.
- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension
registers in cpu context. This must be enabled, if the platform wants to use
this feature in the Secure world and MTE is enabled at ELX. This flag can

51
include/lib/el3_runtime/aarch64/context.h
View file

@ -207,18 +207,6 @@
// Only if MTE registers in use
#define CTX_TFSR_EL2 U(0x100)
#define CTX_MPAM2_EL2 U(0x108)
#define CTX_MPAMHCR_EL2 U(0x110)
#define CTX_MPAMVPM0_EL2 U(0x118)
#define CTX_MPAMVPM1_EL2 U(0x120)
#define CTX_MPAMVPM2_EL2 U(0x128)
#define CTX_MPAMVPM3_EL2 U(0x130)
#define CTX_MPAMVPM4_EL2 U(0x138)
#define CTX_MPAMVPM5_EL2 U(0x140)
#define CTX_MPAMVPM6_EL2 U(0x148)
#define CTX_MPAMVPM7_EL2 U(0x150)
#define CTX_MPAMVPMV_EL2 U(0x158)
// Starting with Armv8.6
#define CTX_HDFGRTR_EL2 U(0x160)
#define CTX_HAFGRTR_EL2 U(0x168)
@ -337,6 +325,27 @@
#define CTX_PAUTH_REGS_END U(0)
#endif /* CTX_INCLUDE_PAUTH_REGS */
/*******************************************************************************
* Registers related to ARMv8.2-MPAM.
******************************************************************************/
#define CTX_MPAM_REGS_OFFSET (CTX_PAUTH_REGS_OFFSET + CTX_PAUTH_REGS_END)
#if CTX_INCLUDE_MPAM_REGS
#define CTX_MPAM2_EL2 U(0x0)
#define CTX_MPAMHCR_EL2 U(0x8)
#define CTX_MPAMVPM0_EL2 U(0x10)
#define CTX_MPAMVPM1_EL2 U(0x18)
#define CTX_MPAMVPM2_EL2 U(0x20)
#define CTX_MPAMVPM3_EL2 U(0x28)
#define CTX_MPAMVPM4_EL2 U(0x30)
#define CTX_MPAMVPM5_EL2 U(0x38)
#define CTX_MPAMVPM6_EL2 U(0x40)
#define CTX_MPAMVPM7_EL2 U(0x48)
#define CTX_MPAMVPMV_EL2 U(0x50)
#define CTX_MPAM_REGS_END U(0x60)
#else
#define CTX_MPAM_REGS_END U(0x0)
#endif /* CTX_INCLUDE_MPAM_REGS */
/*******************************************************************************
* Registers initialised in a per-world context.
******************************************************************************/
@ -375,6 +384,9 @@
#if CTX_INCLUDE_PAUTH_REGS
# define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT)
#endif
#if CTX_INCLUDE_MPAM_REGS
# define CTX_MPAM_REGS_ALL (CTX_MPAM_REGS_END >> DWORD_SHIFT)
#endif
/*
* AArch64 general purpose register context structure. Usually x0-x18,
@ -423,6 +435,11 @@ DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL);
DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL);
#endif
/* Registers associated to ARMv8.2 MPAM */
#if CTX_INCLUDE_MPAM_REGS
DEFINE_REG_STRUCT(mpam, CTX_MPAM_REGS_ALL);
#endif
/*
* Macros to access members of any of the above structures using their
* offsets
@ -453,6 +470,9 @@ typedef struct cpu_context {
#if CTX_INCLUDE_PAUTH_REGS
pauth_t pauth_ctx;
#endif
#if CTX_INCLUDE_MPAM_REGS
mpam_t mpam_ctx;
#endif
} cpu_context_t;
/*
@ -481,6 +501,9 @@ extern per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM];
#if CTX_INCLUDE_PAUTH_REGS
# define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx)
#endif
#if CTX_INCLUDE_MPAM_REGS
# define get_mpam_ctx(h) (&((cpu_context_t *) h)->mpam_ctx)
#endif
/*
* Compile time assertions related to the 'cpu_context' structure to
@ -507,6 +530,10 @@ CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3
CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx),
assert_core_context_pauth_offset_mismatch);
#endif
#if CTX_INCLUDE_MPAM_REGS
CASSERT(CTX_MPAM_REGS_OFFSET == __builtin_offsetof(cpu_context_t, mpam_ctx),
assert_core_context_mpam_offset_mismatch);
#endif
/*
* Helper macro to set the general purpose registers that correspond to

22
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -1048,7 +1048,9 @@ static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx)
write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2));
}
static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx)
#if CTX_INCLUDE_MPAM_REGS
static void el2_sysregs_context_save_mpam(mpam_t *ctx)
{
u_register_t mpam_idr = read_mpamidr_el1();
@ -1099,7 +1101,10 @@ static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx)
}
}
static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx)
#endif /* CTX_INCLUDE_MPAM_REGS */
#if CTX_INCLUDE_MPAM_REGS
static void el2_sysregs_context_restore_mpam(mpam_t *ctx)
{
u_register_t mpam_idr = read_mpamidr_el1();
@ -1137,6 +1142,7 @@ static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx)
break;
}
}
#endif /* CTX_INCLUDE_MPAM_REGS */
/* -----------------------------------------------------
* The following registers are not added:
@ -1264,9 +1270,13 @@ void cm_el2_sysregs_context_save(uint32_t security_state)
#if CTX_INCLUDE_MTE_REGS
write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2());
#endif
#if CTX_INCLUDE_MPAM_REGS
if (is_feat_mpam_supported()) {
el2_sysregs_context_save_mpam(el2_sysregs_ctx);
mpam_t *mpam_ctx = get_mpam_ctx(ctx);
el2_sysregs_context_save_mpam(mpam_ctx);
}
#endif
if (is_feat_fgt_supported()) {
el2_sysregs_context_save_fgt(el2_sysregs_ctx);
@ -1337,9 +1347,13 @@ void cm_el2_sysregs_context_restore(uint32_t security_state)
#if CTX_INCLUDE_MTE_REGS
write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2));
#endif
#if CTX_INCLUDE_MPAM_REGS
if (is_feat_mpam_supported()) {
el2_sysregs_context_restore_mpam(el2_sysregs_ctx);
mpam_t *mpam_ctx = get_mpam_ctx(ctx);
el2_sysregs_context_restore_mpam(mpam_ctx);
}
#endif
if (is_feat_fgt_supported()) {
el2_sysregs_context_restore_fgt(el2_sysregs_ctx);

4
make_helpers/defaults.mk
View file

@ -374,3 +374,7 @@ ENABLE_CONSOLE_GETC := 0
# functions must be enabled by platforms if they require it.
# Disabled by default.
INIT_UNUSED_NS_EL2 := 0
# Disable including MPAM EL2 registers in context by default since currently
# it's only enabled for NS world
CTX_INCLUDE_MPAM_REGS := 0