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feat(intel): support QSPI ECC Linux for Stratix10

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Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I1cdacc0f10dfa2a969f0bc5086277fd9081d02e2
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
This commit is contained in:
Jit Loon Lim 2023-10-18 16:19:27 +08:00 • committed by Sieu Mun Tang
parent 4d122e5f19
commit 8be16e44cf
2 changed files with 15 additions and 0 deletions
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14
plat/intel/soc/stratix10/include/s10_system_manager.h
View file

@ -142,6 +142,18 @@
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C
/* QSPI ECC from SDM register */
#define SOCFPGA_ECC_QSPI_CTRL 0x08
#define SOCFPGA_ECC_QSPI_ERRINTEN 0x10
#define SOCFPGA_ECC_QSPI_ERRINTENS 0x14
#define SOCFPGA_ECC_QSPI_ERRINTENR 0x18
#define SOCFPGA_ECC_QSPI_INTMODE 0x1C
#define SOCFPGA_ECC_QSPI_INTSTAT 0x20
#define SOCFPGA_ECC_QSPI_INTTEST 0x24
#define SOCFPGA_ECC_QSPI_ECC_ACCCTRL 0x78
#define SOCFPGA_ECC_QSPI_ECC_STARTACC 0x7C
#define SOCFPGA_ECC_QSPI_ECC_WDCTRL 0x80
#define DMA0_STREAM_CTRL_REG 0x10D1217C
#define DMA1_STREAM_CTRL_REG 0x10D12180
#define SDM_STREAM_CTRL_REG 0x10D12184
@ -182,6 +194,8 @@
#define RMMUSECSID_REG_VAL BIT(5)
/* Macros */
#define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \
+ (SOCFPGA_ECC_QSPI_##_reg))
#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
+ (SOCFPGA_SYSMGR_##_reg))

1
plat/intel/soc/stratix10/include/socfpga_plat_def.h
View file

@ -33,6 +33,7 @@
#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000
#define SOCFPGA_ECC_QSPI_REG_BASE 0xffa22000
#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000
#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100