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https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
feat(intel): support wipe DDR after calibration
After a calibration we cannot trust the DDR content. Let's explicitly clear the DDR content using the built-in scrubber in this case. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: I6f429623f76a21f61f85efbb660cf65d99c04f56
This commit is contained in:
Jit Loon Lim
Sieu Mun Tang
parent
d0574da589
commit
68bb3e836e
4 changed files with 199 additions and 0 deletions
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@ -53,6 +53,7 @@ BL2_SOURCES += \
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plat/intel/soc/common/soc/socfpga_handoff.c \
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plat/intel/soc/common/soc/socfpga_mailbox.c \
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plat/intel/soc/common/soc/socfpga_reset_manager.c \
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plat/intel/soc/common/drivers/ddr/ddr.c \
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plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
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plat/intel/soc/common/drivers/wdt/watchdog.c
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@ -7,6 +7,7 @@
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#include <assert.h>
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#include <errno.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include "ddr.h"
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#include <lib/mmio.h>
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#include "socfpga_handoff.h"
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@ -340,3 +341,143 @@ int ddr_init(void)
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NOTICE("DDR init successfully\n");
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return status;
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}
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int ddr_config_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type)
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{
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uint32_t temp[9] = {0};
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int ret = 0;
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/* Write default value to prevent scrubber stop due to lower power */
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mmio_write_32(0, umctl2_base + DDR4_PWRCTL_OFFSET);
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/* To backup user configurations in temp array */
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temp[0] = mmio_read_32(umctl2_base + DDR4_SBRCTL_OFFSET);
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temp[1] = mmio_read_32(umctl2_base + DDR4_SBRWDATA0_OFFSET);
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temp[2] = mmio_read_32(umctl2_base + DDR4_SBRSTART0_OFFSET);
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if (umctl2_type == DDR_TYPE_DDR4) {
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temp[3] = mmio_read_32(umctl2_base + DDR4_SBRWDATA1_OFFSET);
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temp[4] = mmio_read_32(umctl2_base + DDR4_SBRSTART1_OFFSET);
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}
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temp[5] = mmio_read_32(umctl2_base + DDR4_SBRRANGE0_OFFSET);
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temp[6] = mmio_read_32(umctl2_base + DDR4_SBRRANGE1_OFFSET);
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temp[7] = mmio_read_32(umctl2_base + DDR4_ECCCFG0_OFFSET);
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temp[8] = mmio_read_32(umctl2_base + DDR4_ECCCFG1_OFFSET);
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if (umctl2_type != DDR_TYPE_DDR4) {
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/* Lock ECC region, ensure this regions is not being accessed */
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mmio_setbits_32(umctl2_base + DDR4_ECCCFG1_OFFSET,
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LPDDR4_ECCCFG1_ECC_REGIONS_PARITY_LOCK);
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}
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/* Disable input traffic per port */
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mmio_clrbits_32(umctl2_base + DDR4_PCTRL0_OFFSET, DDR4_PCTRL0_PORT_EN);
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/* Disables scrubber */
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mmio_clrbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);
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/* Polling all scrub writes data have been sent */
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ret = poll_idle_status((umctl2_base + DDR4_SBRSTAT_OFFSET),
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DDR4_SBRSTAT_SCRUB_BUSY, true, 5000);
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if (ret) {
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INFO("%s: Timeout while waiting for", __func__);
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INFO(" sending all scrub data\n");
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return ret;
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}
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/* LPDDR4 supports inline ECC only */
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if (umctl2_type != DDR_TYPE_DDR4) {
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/*
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* Setting all regions for protected, this is required for
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* srubber to init whole LPDDR4 expect ECC region
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*/
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mmio_write_32(((ONE_EIGHT <<
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LPDDR4_ECCCFG0_ECC_REGION_MAP_GRANU_SHIFT) |
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(ALL_PROTECTED << LPDDR4_ECCCFG0_ECC_REGION_MAP_SHIFT)),
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umctl2_base + DDR4_ECCCFG0_OFFSET);
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}
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/* Scrub_burst = 1, scrub_mode = 1(performs writes) */
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mmio_write_32(DDR4_SBRCTL_SCRUB_BURST_1 | DDR4_SBRCTL_SCRUB_WRITE,
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umctl2_base + DDR4_SBRCTL_OFFSET);
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/* Wipe DDR content after calibration */
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ret = ddr_zerofill_scrubber(umctl2_base, umctl2_type);
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if (ret) {
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ERROR("Failed to clear DDR content\n");
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}
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/* Polling all scrub writes data have been sent */
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ret = poll_idle_status((umctl2_base + DDR4_SBRSTAT_OFFSET),
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DDR4_SBRSTAT_SCRUB_BUSY, true, 5000);
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if (ret) {
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INFO("%s: Timeout while waiting for", __func__);
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INFO(" sending all scrub data\n");
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return ret;
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}
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/* Disables scrubber */
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mmio_clrbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);
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/* Restore user configurations */
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mmio_write_32(temp[0], umctl2_base + DDR4_SBRCTL_OFFSET);
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mmio_write_32(temp[1], umctl2_base + DDR4_SBRWDATA0_OFFSET);
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mmio_write_32(temp[2], umctl2_base + DDR4_SBRSTART0_OFFSET);
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if (umctl2_type == DDR_TYPE_DDR4) {
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mmio_write_32(temp[3], umctl2_base + DDR4_SBRWDATA1_OFFSET);
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mmio_write_32(temp[4], umctl2_base + DDR4_SBRSTART1_OFFSET);
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}
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mmio_write_32(temp[5], umctl2_base + DDR4_SBRRANGE0_OFFSET);
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mmio_write_32(temp[6], umctl2_base + DDR4_SBRRANGE1_OFFSET);
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mmio_write_32(temp[7], umctl2_base + DDR4_ECCCFG0_OFFSET);
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mmio_write_32(temp[8], umctl2_base + DDR4_ECCCFG1_OFFSET);
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/* Enables ECC scrub on scrubber */
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if (!(mmio_read_32(umctl2_base + DDR4_SBRCTL_OFFSET) & DDR4_SBRCTL_SCRUB_WRITE)) {
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/* Enables scrubber */
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mmio_setbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);
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}
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return 0;
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}
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int ddr_zerofill_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type)
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{
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int ret = 0;
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/* Zeroing whole DDR */
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mmio_write_32(0, umctl2_base + DDR4_SBRWDATA0_OFFSET);
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mmio_write_32(0, umctl2_base + DDR4_SBRSTART0_OFFSET);
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if (umctl2_type == DDR_TYPE_DDR4) {
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mmio_write_32(0, umctl2_base + DDR4_SBRWDATA1_OFFSET);
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mmio_write_32(0, umctl2_base + DDR4_SBRSTART1_OFFSET);
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}
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mmio_write_32(0, umctl2_base + DDR4_SBRRANGE0_OFFSET);
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mmio_write_32(0, umctl2_base + DDR4_SBRRANGE1_OFFSET);
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NOTICE("Enabling scrubber (zeroing whole DDR) ...\n");
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/* Enables scrubber */
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mmio_setbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);
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/* Polling all scrub writes commands have been sent */
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ret = poll_idle_status((umctl2_base + DDR4_SBRSTAT_OFFSET),
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DDR4_SBRSTAT_SCRUB_DONE, true, 5000);
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if (ret) {
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INFO("%s: Timeout while waiting for", __func__);
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INFO(" sending all scrub commands\n");
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return ret;
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}
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return 0;
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}
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int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms)
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{
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int time_out = delay_ms;
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while (time_out-- > 0) {
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if ((mmio_read_32(addr) & mask) == match) {
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return 0;
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}
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udelay(1000);
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}
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return -ETIMEDOUT;
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}
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@ -10,6 +10,28 @@
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#include <lib/mmio.h>
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#include "socfpga_handoff.h"
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enum ddr_type {
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DDR_TYPE_LPDDR4_0,
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DDR_TYPE_LPDDR4_1,
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DDR_TYPE_DDR4,
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DDR_TYPE_LPDDR5_0,
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DDR_TYPE_LPDDR5_1,
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DDR_TYPE_DDR5,
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DDR_TYPE_UNKNOWN
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};
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/* Region size for ECCCFG0.ecc_region_map */
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enum region_size {
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ONE_EIGHT,
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ONE_SIXTEENTH,
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ONE_THIRTY_SECOND,
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ONE_SIXTY_FOURTH
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};
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/* DATATYPE DEFINATION */
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typedef unsigned long long phys_addr_t;
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typedef unsigned long long phys_size_t;
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/* MACRO DEFINATION */
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#define IO96B_0_REG_BASE 0x18400000
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#define IO96B_1_REG_BASE 0x18800000
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@ -86,6 +108,34 @@
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#define IOSSM_MB_WRITE(addr, data) mmio_write_32(addr, data)
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/* DDR4 Register */
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#define DDR4_PWRCTL_OFFSET 0x30
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#define DDR4_SBRCTL_OFFSET 0x0F24
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#define DDR4_SBRSTAT_OFFSET 0x0F28
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#define DDR4_SBRWDATA0_OFFSET 0x0F2C
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#define DDR4_SBRSTART0_OFFSET 0x0F38
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#define DDR4_SBRWDATA1_OFFSET 0x0F30
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#define DDR4_SBRSTART1_OFFSET 0x0F3C
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#define DDR4_SBRRANGE0_OFFSET 0x0F40
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#define DDR4_SBRRANGE1_OFFSET 0x0F44
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#define DDR4_ECCCFG0_OFFSET 0x70
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#define DDR4_ECCCFG1_OFFSET 0x74
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#define DDR4_PCTRL0_OFFSET 0x0490
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#define LPDDR4_ECCCFG0_ECC_REGION_MAP_GRANU_SHIFT 30
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#define ALL_PROTECTED 0x7F
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#define LPDDR4_ECCCFG0_ECC_REGION_MAP_SHIFT 8
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#define LPDDR4_ECCCFG1_ECC_REGIONS_PARITY_LOCK BIT(4)
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#define DDR4_PCTRL0_PORT_EN BIT(0)
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#define DDR4_SBRCTL_SCRUB_EN BIT(0)
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#define DDR4_SBRSTAT_SCRUB_BUSY BIT(0)
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#define DDR4_SBRCTL_SCRUB_BURST_1 BIT(4)
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#define DDR4_SBRCTL_SCRUB_WRITE BIT(2)
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#define DDR4_SBRSTAT_SCRUB_DONE BIT(1)
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/* FUNCTION DEFINATION */
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int ddr_calibration_check(void);
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@ -109,4 +159,10 @@ void ddr_enable_firewall(void);
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bool is_ddr_init_in_progress(void);
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int ddr_zerofill_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type);
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int ddr_config_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type);
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int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms);
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#endif
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@ -53,6 +53,7 @@ BL2_SOURCES += \
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plat/intel/soc/common/soc/socfpga_mailbox.c \
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plat/intel/soc/common/soc/socfpga_reset_manager.c \
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plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
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plat/intel/soc/common/drivers/ddr/ddr.c \
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plat/intel/soc/common/drivers/wdt/watchdog.c
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include lib/zlib/zlib.mk
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