mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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feat(intel): support SDM mailbox safe inject seu error for Linux
Linux RAS shall handle the SEU error received from SDM and report an error message to user Change-Id: I89181a388063ce9bd6f56b45b1851ccb08582437 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
This commit is contained in:
Jit Loon Lim
parent
93823fb6ec
commit
fffcb25c3c
4 changed files with 107 additions and 83 deletions
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@ -68,6 +68,7 @@
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/* SEU Commands */
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#define MBOX_CMD_SEU_ERR_READ 0x3C
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#define MBOX_CMD_SAFE_INJECT_SEU_ERR 0x41
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/* RSU Commands */
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#define MBOX_GET_SUBPARTITION_TABLE 0x5A
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@ -107,7 +108,7 @@
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#define MBOX_GET_MEASUREMENT 0x183
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/* Miscellaneous commands */
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#define MBOX_GET_ROM_PATCH_SHA384 0x1B0
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#define MBOX_GET_ROM_PATCH_SHA384 0x1B0
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/* Mailbox Definitions */
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@ -196,9 +197,9 @@
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#define RSU_VERSION_ACMF_MASK 0xff00
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/* Config Status Macros */
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#define CONFIG_STATUS_WORD_SIZE 16U
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#define CONFIG_STATUS_FW_VER_OFFSET 1
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#define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF
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#define CONFIG_STATUS_WORD_SIZE 16U
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#define CONFIG_STATUS_FW_VER_OFFSET 1
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#define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF
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/* Data structure */
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@ -249,5 +250,6 @@ int mailbox_hps_stage_notify(uint32_t execution_stage);
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int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf);
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int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf);
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int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len);
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int mailbox_safe_inject_seu_err(uint32_t *arg, unsigned int len);
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#endif /* SOCFPGA_MBOX_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -9,82 +9,82 @@
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/* SiP status response */
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#define INTEL_SIP_SMC_STATUS_OK 0
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#define INTEL_SIP_SMC_STATUS_BUSY 0x1
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#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
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#define INTEL_SIP_SMC_STATUS_NO_RESPONSE 0x3
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#define INTEL_SIP_SMC_STATUS_ERROR 0x4
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#define INTEL_SIP_SMC_RSU_ERROR 0x7
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#define INTEL_SIP_SMC_SEU_ERR_READ_ERROR 0x8
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#define INTEL_SIP_SMC_STATUS_OK 0
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#define INTEL_SIP_SMC_STATUS_BUSY 0x1
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#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
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#define INTEL_SIP_SMC_STATUS_NO_RESPONSE 0x3
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#define INTEL_SIP_SMC_STATUS_ERROR 0x4
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#define INTEL_SIP_SMC_RSU_ERROR 0x7
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#define INTEL_SIP_SMC_SEU_ERR_READ_ERROR 0x8
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/* SiP mailbox error code */
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#define GENERIC_RESPONSE_ERROR 0x3FF
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#define GENERIC_RESPONSE_ERROR 0x3FF
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/* SiP V2 command code range */
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#define INTEL_SIP_SMC_CMD_MASK 0xFFFF
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#define INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN 0x400
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#define INTEL_SIP_SMC_CMD_V2_RANGE_END 0x4FF
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#define INTEL_SIP_SMC_CMD_MASK 0xFFFF
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#define INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN 0x400
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#define INTEL_SIP_SMC_CMD_V2_RANGE_END 0x4FF
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/* SiP V2 protocol header */
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#define INTEL_SIP_SMC_HEADER_JOB_ID_MASK 0xF
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#define INTEL_SIP_SMC_HEADER_JOB_ID_OFFSET 0U
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#define INTEL_SIP_SMC_HEADER_CID_MASK 0xF
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#define INTEL_SIP_SMC_HEADER_CID_OFFSET 4U
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#define INTEL_SIP_SMC_HEADER_VERSION_MASK 0xF
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#define INTEL_SIP_SMC_HEADER_VERSION_OFFSET 60U
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#define INTEL_SIP_SMC_HEADER_JOB_ID_MASK 0xF
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#define INTEL_SIP_SMC_HEADER_JOB_ID_OFFSET 0U
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#define INTEL_SIP_SMC_HEADER_CID_MASK 0xF
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#define INTEL_SIP_SMC_HEADER_CID_OFFSET 4U
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#define INTEL_SIP_SMC_HEADER_VERSION_MASK 0xF
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#define INTEL_SIP_SMC_HEADER_VERSION_OFFSET 60U
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/* SMC SiP service function identifier for version 1 */
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/* FPGA Reconfig */
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#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
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#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
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#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
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#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
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#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
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#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
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#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
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#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
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#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
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#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
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/* FPGA Bitstream Flag */
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#define FLAG_PARTIAL_CONFIG BIT(0)
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#define FLAG_AUTHENTICATION BIT(1)
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#define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \
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== FLAG_##_type)
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#define FLAG_PARTIAL_CONFIG BIT(0)
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#define FLAG_AUTHENTICATION BIT(1)
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#define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \
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== FLAG_##_type)
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/* Secure Register Access */
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#define INTEL_SIP_SMC_REG_READ 0xC2000007
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#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
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#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009
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#define INTEL_SIP_SMC_REG_READ 0xC2000007
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#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
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#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009
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/* Remote System Update */
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#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B
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#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
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#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
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#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
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#define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010
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#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011
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#define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012
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#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013
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#define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014
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#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015
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#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B
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#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
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#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
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#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
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#define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010
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#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011
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#define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012
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#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013
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#define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014
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#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015
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/* Hardware monitor */
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#define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020
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#define INTEL_SIP_SMC_HWMON_READVOLT 0xC2000021
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#define TEMP_CHANNEL_MAX (1 << 15)
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#define VOLT_CHANNEL_MAX (1 << 15)
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#define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020
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#define INTEL_SIP_SMC_HWMON_READVOLT 0xC2000021
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#define TEMP_CHANNEL_MAX (1 << 15)
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#define VOLT_CHANNEL_MAX (1 << 15)
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/* ECC */
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#define INTEL_SIP_SMC_ECC_DBE 0xC200000D
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#define INTEL_SIP_SMC_ECC_DBE 0xC200000D
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/* Generic Command */
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#define INTEL_SIP_SMC_SERVICE_COMPLETED 0xC200001E
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#define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F
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#define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032
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#define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040
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#define INTEL_SIP_SMC_SERVICE_COMPLETED 0xC200001E
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#define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F
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#define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032
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#define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040
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#define SERVICE_COMPLETED_MODE_ASYNC 0x00004F4E
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#define SERVICE_COMPLETED_MODE_ASYNC 0x00004F4E
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/* Mailbox Command */
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#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200003C
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#define INTEL_SIP_SMC_GET_USERCODE 0xC200003D
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#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200003C
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#define INTEL_SIP_SMC_GET_USERCODE 0xC200003D
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/* FPGA Crypto Services */
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#define INTEL_SIP_SMC_FCS_RANDOM_NUMBER 0xC200005A
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@ -140,21 +140,22 @@
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#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE 0xC200008E
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/* SEU ERR */
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#define INTEL_SIP_SMC_SEU_ERR_STATUS 0xC2000099
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#define INTEL_SIP_SMC_SEU_ERR_STATUS 0xC2000099
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#define INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR 0xC200009A
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#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF
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#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF
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#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U
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#define INTEL_SIP_SMC_FCS_ECC_ALGO_MASK 0xF
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#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF
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#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF
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#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U
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#define INTEL_SIP_SMC_FCS_ECC_ALGO_MASK 0xF
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/* ECC DBE */
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#define WARM_RESET_WFI_FLAG BIT(31)
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#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
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SYSMGR_ECC_DDR0_MASK |\
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SYSMGR_ECC_DDR1_MASK)
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#define WARM_RESET_WFI_FLAG BIT(31)
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#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
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SYSMGR_ECC_DDR0_MASK |\
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SYSMGR_ECC_DDR1_MASK)
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/* Non-mailbox SMC Call */
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#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
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#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
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/**
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* SMC SiP service function identifier for version 2
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@ -162,31 +163,31 @@
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*/
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/* V2: Non-mailbox function identifier */
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#define INTEL_SIP_SMC_V2_GET_SVC_VERSION 0xC2000400
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#define INTEL_SIP_SMC_V2_REG_READ 0xC2000401
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#define INTEL_SIP_SMC_V2_REG_WRITE 0xC2000402
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#define INTEL_SIP_SMC_V2_REG_UPDATE 0xC2000403
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#define INTEL_SIP_SMC_V2_HPS_SET_BRIDGES 0xC2000404
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#define INTEL_SIP_SMC_V2_RSU_UPDATE_ADDR 0xC2000405
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#define INTEL_SIP_SMC_V2_GET_SVC_VERSION 0xC2000400
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#define INTEL_SIP_SMC_V2_REG_READ 0xC2000401
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#define INTEL_SIP_SMC_V2_REG_WRITE 0xC2000402
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#define INTEL_SIP_SMC_V2_REG_UPDATE 0xC2000403
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#define INTEL_SIP_SMC_V2_HPS_SET_BRIDGES 0xC2000404
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#define INTEL_SIP_SMC_V2_RSU_UPDATE_ADDR 0xC2000405
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/* V2: Mailbox function identifier */
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#define INTEL_SIP_SMC_V2_MAILBOX_SEND_COMMAND 0xC2000420
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#define INTEL_SIP_SMC_V2_MAILBOX_POLL_RESPONSE 0xC2000421
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#define INTEL_SIP_SMC_V2_MAILBOX_SEND_COMMAND 0xC2000420
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#define INTEL_SIP_SMC_V2_MAILBOX_POLL_RESPONSE 0xC2000421
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/* SMC function IDs for SiP Service queries */
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#define SIP_SVC_CALL_COUNT 0x8200ff00
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#define SIP_SVC_UID 0x8200ff01
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#define SIP_SVC_VERSION 0x8200ff03
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#define SIP_SVC_CALL_COUNT 0x8200ff00
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#define SIP_SVC_UID 0x8200ff01
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#define SIP_SVC_VERSION 0x8200ff03
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/* SiP Service Calls version numbers */
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/*
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* Increase if there is any backward compatibility impact
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*/
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#define SIP_SVC_VERSION_MAJOR 2
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#define SIP_SVC_VERSION_MAJOR 2
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/*
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* Increase if there is new SMC function ID being added
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*/
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#define SIP_SVC_VERSION_MINOR 2
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#define SIP_SVC_VERSION_MINOR 2
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/* Structure Definitions */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
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* Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -696,3 +696,9 @@ int mailbox_seu_err_status(uint32_t *resp_buf, unsigned int resp_buf_len)
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CMD_CASUAL, resp_buf,
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&resp_buf_len);
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}
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int mailbox_safe_inject_seu_err(uint32_t *arg, unsigned int len)
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{
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return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_SAFE_INJECT_SEU_ERR, arg, len,
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CMD_CASUAL, NULL, NULL);
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}
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@ -689,9 +689,19 @@ uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask)
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}
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/* SDM SEU Error services */
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static uint32_t intel_sdm_seu_err_read(uint64_t *respbuf, unsigned int respbuf_sz)
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static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz)
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{
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if (mailbox_seu_err_status((uint32_t *)respbuf, respbuf_sz) < 0) {
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if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) {
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return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
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}
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return INTEL_SIP_SMC_STATUS_OK;
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}
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/* SDM SAFE SEU Error inject services */
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static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len)
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{
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if (mailbox_safe_inject_seu_err(command, len) < 0) {
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return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
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}
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@ -714,7 +724,8 @@ uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
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uint32_t retval = 0, completed_addr[3];
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uint32_t retval2 = 0;
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uint32_t mbox_error = 0;
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uint64_t retval64, rsu_respbuf[9], seu_respbuf[3];
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uint64_t retval64, rsu_respbuf[9];
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uint32_t seu_respbuf[3];
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int status = INTEL_SIP_SMC_STATUS_OK;
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int mbox_status;
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unsigned int len_in_resp;
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@ -1229,6 +1240,10 @@ uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
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SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]);
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}
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case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR:
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status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2);
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SMC_RET1(handle, status);
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default:
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return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
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cookie, handle, flags);
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