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Merge "fix(intel): update DDR range checking for Agilex5" into integration

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Sandrine Bailleux 2023-12-19 15:32:06 +01:00 • committed by TrustedFirmware Code Review
commit 108a1c1d9d
1 changed files with 4 additions and 1 deletions
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5
plat/intel/soc/common/socfpga_sip_svc.c
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@ -280,6 +280,9 @@ static bool is_fpga_config_buffer_full(void)
bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
{
uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE;
uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size;
if (!addr && !size) {
return true;
}
@ -289,7 +292,7 @@ bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
if (addr < BL31_LIMIT) {
return false;
}
if (addr + size > DRAM_BASE + DRAM_SIZE) {
if (dram_region_end > dram_max_sz) {
return false;
}