The problem that this resolves is a bit involved; the following
must be met at the same time for some function <to_be_wrapped>:
* to_be_wrapped must be specified as part of the romlib
* to_be_wrapped must _not_ be referenced by any translation unit
in TF-A
* to_be_wrapped must be referenced by a translation unit in a
dependent library, mbedtls for example.
Under these circumstances, to_be_wrapped will not be wrapped, and
will instead reference its original definition while simultaneously
residing in romlib.
This is a side effect of two issues with romlib prior to this patch:
1 to_be_wrapped is expected to wrap by duplicating its definition.
This causes any condition that links against both the base and
wrapper functions to be a link error (duplicate symbol definition).
2 to_be_wrapped is in its own translation unit
This causes the wrappers to be used by TF-A in an as needed.
The duplicate function definitions can be worked around using the
linker's `--wrap` flag, which redirects all references to a symbol
to resolve to `__wrap_<symbol>` and the original symbol to be
available as `__real_<symbol>`. Most of the changes handle creating
this arguments and passing them to the linker.
Further, once you use the linker's wrap, you will encounter another
issue: if TF-A does not use a function, its wrapper is not present.
This causes link issues when a library and not TF-A uses the wrapper.
Note that this issue would have been resolved previously by ignoring
the wrapper and using the base definition.
This further issue is worked around by concatenating the assembly for
all of the wrappers into a single translation unit. It's possible to
work around this issue in a few other ways, including reordering the
libraries passed to the linker to place libwrapper.a last or grouping
the libraries so that symbols from later libraries may be resolved
with prior libraries.
I chose the translation unit concatenation approach as it revealed
that a jumptable has duplicate symbols within it.
Change-Id: Ie57b5ae69bde2fc8705bdc7a93fae3ddb5341ed9
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* changes:
docs: add binding for vm availability messages
docs: fix discrepancies in value type of manifest fields
docs: update ff-a manifest bindings
chore(docs): remove hafnium specific documentation
Per GIC architecture version 3 and version 4, Where the GICR_CTRL.EnableLPIs
remains programmable:
- Software must observe GICR_CTLR.RWP==0 after clearing GICR_CTLR.EnableLPIs
from 1 to 0 before writing GICR_PENDBASER or GICR_PROPBASER, otherwise
behavior is UNPREDICTABLE.
- Software must observe GICR_CTLR.RWP==0 after clearing GICR_CTLR.EnableLPIs
from 1 to 0 before setting GICR_CTLR.EnableLPIs to 1, otherwise behavior is
UNPREDICTABLE.
After changing EnableLPIs from 1 to 0, wait RWP got cleared, otherwise
setting EnableLPIs from 0 to 1 may fail.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Tested-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I6aaf96dc9984376de9399d0dac8a8504ba095149
SPs can subscribe to get notified when a VM is created or destroyed.
This patch adds a binding to the SP manifest to represent this.
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Change-Id: Ib23655575f471a22bcf261f70f2c4124a3f292c3
* changes:
docs(xilinx): update SMC documentation in TF-A
feat(xilinx): add feature check function for TF-A specific APIs
feat(xilinx): update SiP SVC version number
feat(xilinx): update TF-A to passthrough all PLM commands
fix(xilinx): fix logic to read ipi response
* changes:
feat(nxp-clk): enable the XBAR clock
feat(nxp-clk): add dependencies for the XBAR clock
feat(nxp-clk): add CGM0 instance
feat(nxp-clk): add DFS module enablement
feat(nxp-clk): add clock objects for ARM DFS
refactor(nxp-clk): organize early clocks in groups
Following IOCTL IDs are required for UFS specific functionalities.
IOCTL ID - 40(IOCTL_UFS_TXRX_CFGRDY_GET)
This gives the Tx_Rx_config_rdy_signal_mon(0xF1061054) register value
which contains the Tx and Rx lanes configuration ready signal information.
IOCTL ID - 41(IOCTL_UFS_SRAM_CSR_SEL)
Select - 0(IOCTL_UFS_SRAM_CSR_SET)
This will allow to set sram control and status register (0xF106104C)
with the value provided by driver.
Select - 1(IOCTL_UFS_SRAM_CSR_GET)
This should return the sram control and status register (0xF106104C) value
to the driver.
UFS Host reset assert/de-assert(using SCMI) support is added.
register address : 0xF1260340
UFS PHY reset assert/de-assert(using SCMI) support is added.
register address : 0xF1061050
Change-Id: I5368cc7251350946bd5ddb3a4c817b75e1d4a43e
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Add dummy implementation of power domain. There is dwc3 usb driver which
requires power domain to be setup and make sense to have interface prepared
even it is not doing anything. When this runs on real HW functionality will
be extended.
Change-Id: I68151edc3ab817da3308e7c21af57a3355a17d37
Signed-off-by: Michal Simek <michal.simek@amd.com>
Enable the XBAR clock, which is the primary system clock.
Change-Id: Idaafbb8894472b10e1ed8a35b25967c82106e667
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add all clock modules required to enable the XBAR clock, including the
DFS, its output dividers and MC_CGM muxes.
Change-Id: Ib9cf82c0e40b76863637ed7602c3a09411d17615
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Introduce the MC_CGM0 instance responsible for XBAR and other peripheral
clocks.
Change-Id: Icf1e9ce6e71e4ff446835d1e7b6522bfb6f2b4b6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
In order to avoid the complexity of supporting value types smaller
than u32 and avoid discrepancies for the various manifest fields
among different projects, the value type for relevant fields are
upgraded to u32.
Change-Id: Ib033019b3b8c26bf4b8b50f89b7a6d1a772e5e51
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Various SPMC projects within trustefirmware.org have decided to adhere
to a common FF-A manifest binding document. The one hosted in the
readthedocs portal of TF-A project will be considered as the reference.
Hence, this binding document is updated to reflect new additions made
to binding document hosted in Hafnium project. Eventually, all other
binding document are going to be removed.
Also, few fields were incorrectly identified as mandatory. Necessary
corrections are made in this patch.
Change-Id: I2eadd77487c770e49605285bbd72027c5e72e385
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
All the relevant documentation for Hafnium as the chosen Secure
Partition Manager has been moved to hafnium project[1].
This patch removes the redundant sections without any loss of
information.
This patch adds links to documentation of each of the SPM projects.
[1] https://hafnium.readthedocs.io/en/latest/secure-partition-manager/index.html
Change-Id: I52caf7dc50f4aa253c68309cac0915b7d368939d
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
The DFS modules are connected to the PLL VCO and provide a clock
downstream through a set of output dividers, the frequency of which can
be adjusted programmatically.
Change-Id: Ie945d10fd39e6e40e6c051ccde8486dcfb5bd53f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This reduces the length of the s32cc_init_early_clks function and offers
space for more early clocks to be added.
Change-Id: I0d11b97779433a6b15cd76c36aefbb7b92381067
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
There is no need for the bl2 static c file for
CCA and Duaroot CoT, remove them from the repo
Change-Id: I251d085034dae0f6b3c6cefdbb129a9e1dd0530b
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
Integrate the cot-dt2c tool into build process
for TBBR configuration
Change-Id: I42ccbc96c5c8fd21266200e427306a80236a78aa
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
Change the makefile to call the cot-dt2c tool
during the build for Arm platform
Change-Id: Idb7c02cca6b9ddd87f575a42c88e7b2660b896e0
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
Add the standalone CoT dt2c tool for CoT DTB conversion to
c file
Change-Id: If28e580a4c2825f5dc9008e93cd2aae3fc173e73
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
Separate the bl1 and bl2 CoT into individual C files for the
upcoming tool, i.e. the CoT device tree-to-source file generator.
Change-Id: I0d24791991b3539c7aef9a562920dc62fecdc69a
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
align the nv counter naming for stm32mp1-cot-descriptor.dtsi file
Change-Id: I8c41c5e323e8bf867e08b4590dfb42e86204ab65
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
Align the naming of nv_counter to nv_ctr in the DTBs
so that they match with the static C files. Update the
binding documentation accordingly. This renaming is beneficial
for the upcoming conversion tool that will convert CoT DT files
to C files.
Change-Id: If65d51ad9fc6445b1ae9937f1691becf8742cf01
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
* changes:
feat(nxp-clk): enable the A53 clock
feat(nxp-clk): add ARM PLL ODIV enablement
feat(nxp-clk): add ARM PLL enablement
feat(nxp-clk): set rate for clock muxes
As the NEED_* are internal flags used in the build system and are not
meant to be used by platforms, remove them from the RD-V3 makefile.
Signed-off-by: Jaylyn Ren <Jaylyn.Ren2@arm.com>
Change-Id: If7144b9d72c16e8025f929f2546abd96194615ce
The GICR_WAKER.Sleep and GICR_WAKE.Quiescent functionality is solely
about flushing out the LPI cache and ensuring that the contents are
consistent with external memory.
Hence, as shown in GIC-700 TRM version r3p0, software must poll for
Quiescent bit only if LPIs are supported.
Change-Id: I7d69b208428e24d8a3ff30e81bd1a8ee3d0bda6e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
The function always checks the first parent of the current core
instead parse the tree topology to find the parent at parent level
of the CPU. It is because the current loop has no effect as it uses
a fixed parameter 'my_idx' and returns the FIRST parent of CPU.
Also, it looks for the parent nodes in the array of CPU nodes, but
actually they are in a separate array.
This update allows to parse the PSCI topology tree to find
the parent at parent level of the CPU identified by my_idx.
Fixes: 606b743007 ("feat(psci): add support for OS-initiated mode")
Change-Id: I96fb5ecc154a76b16adca5b5055217b8626c9e66
Signed-off-by: Charlie Bareham <charlie.bareham@arm.com>
CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU nodes per micro architectures.
Change-Id: I4e940976cdda9a6eab3e15936c6c41a2bb668c9d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Add node for Statistical Profiling Extension, which provides
periodic sampling of operations in the CPU pipeline and reports
this via the perf AUX interface.
Change-Id: Ic7a9d9ce927edbce02c7c09470a009dc56247240
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
