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feat(nxp-clk): enable the XBAR clock

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Enable the XBAR clock, which is the primary system clock.

Change-Id: Idaafbb8894472b10e1ed8a35b25967c82106e667
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This commit is contained in:
Ghennadi Procopciuc 2024-08-05 16:51:03 +03:00
parent 5692f881f5
commit b8ad8800b2
1 changed files with 33 additions and 0 deletions
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33
drivers/nxp/clk/s32cc/s32cc_early_clks.c
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@ -12,6 +12,7 @@
#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
#define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ)
#define S32CC_A53_FREQ (1U * GHZ)
#define S32CC_XBAR_2X_FREQ (800U * MHZ)
static int enable_fxosc_clk(void)
{
@ -84,6 +85,33 @@ static int enable_a53_clk(void)
return ret;
}
static int enable_xbar_clk(void)
{
int ret;
ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX0, S32CC_CLK_ARM_PLL_DFS1);
if (ret != 0) {
return ret;
}
ret = clk_set_rate(S32CC_CLK_XBAR_2X, S32CC_XBAR_2X_FREQ, NULL);
if (ret != 0) {
return ret;
}
ret = clk_enable(S32CC_CLK_ARM_PLL_DFS1);
if (ret != 0) {
return ret;
}
ret = clk_enable(S32CC_CLK_XBAR_2X);
if (ret != 0) {
return ret;
}
return ret;
}
int s32cc_init_early_clks(void)
{
int ret;
@ -105,5 +133,10 @@ int s32cc_init_early_clks(void)
return ret;
}
ret = enable_xbar_clk();
if (ret != 0) {
return ret;
}
return ret;
}