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Merge changes from topic "nxp-s32g2/add-xbar-clk" into integration

Browse source 
* changes:
  feat(nxp-clk): enable the XBAR clock
  feat(nxp-clk): add dependencies for the XBAR clock
  feat(nxp-clk): add CGM0 instance
  feat(nxp-clk): add DFS module enablement
  feat(nxp-clk): add clock objects for ARM DFS
  refactor(nxp-clk): organize early clocks in groups
This commit is contained in:
Madhukar Pappireddy 2024-08-09 16:33:51 +02:00 • committed by TrustedFirmware Code Review
commit 7322e855ec
6 changed files with 496 additions and 34 deletions
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23
drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
View file

@ -9,6 +9,8 @@
#define FXOSC_BASE_ADDR (0x40050000UL)
#define ARMPLL_BASE_ADDR (0x40038000UL)
#define ARM_DFS_BASE_ADDR (0x40054000UL)
#define CGM0_BASE_ADDR (0x40030000UL)
#define CGM1_BASE_ADDR (0x40034000UL)
/* FXOSC */
@ -83,4 +85,25 @@
#define MC_CGM_MUXn_CSS_SWIP BIT_32(16U)
#define MC_CGM_MUXn_CSS_SAFE_SW BIT_32(3U)
/* DFS */
#define DFS_PORTSR(DFS_ADDR) ((DFS_ADDR) + 0xCUL)
#define DFS_PORTOLSR(DFS_ADDR) ((DFS_ADDR) + 0x10UL)
#define DFS_PORTOLSR_LOL(N) (BIT_32(N) & GENMASK_32(5U, 0U))
#define DFS_PORTRESET(DFS_ADDR) ((DFS_ADDR) + 0x14UL)
#define DFS_PORTRESET_MASK GENMASK_32(5U, 0U)
#define DFS_PORTRESET_SET(VAL) (((VAL) & DFS_PORTRESET_MASK))
#define DFS_CTL(DFS_ADDR) ((DFS_ADDR) + 0x18UL)
#define DFS_CTL_RESET BIT_32(1U)
#define DFS_DVPORTn(DFS_ADDR, PORT) ((DFS_ADDR) + 0x1CUL + ((PORT) * 0x4UL))
#define DFS_DVPORTn_MFI_MASK GENMASK_32(15U, 8U)
#define DFS_DVPORTn_MFI_SHIFT 8U
#define DFS_DVPORTn_MFN_MASK GENMASK_32(7U, 0U)
#define DFS_DVPORTn_MFN_SHIFT 0U
#define DFS_DVPORTn_MFI(MFI) (((MFI) & DFS_DVPORTn_MFI_MASK) >> DFS_DVPORTn_MFI_SHIFT)
#define DFS_DVPORTn_MFN(MFN) (((MFN) & DFS_DVPORTn_MFN_MASK) >> DFS_DVPORTn_MFN_SHIFT)
#define DFS_DVPORTn_MFI_SET(VAL) (((VAL) << DFS_DVPORTn_MFI_SHIFT) & DFS_DVPORTn_MFI_MASK)
#define DFS_DVPORTn_MFN_SET(VAL) (((VAL) << DFS_DVPORTn_MFN_SHIFT) & DFS_DVPORTn_MFN_MASK)
#endif /* S32CC_CLK_REGS_H */

257
drivers/nxp/clk/s32cc/s32cc_clk_drv.c
View file

@ -22,6 +22,8 @@
struct s32cc_clk_drv {
uintptr_t fxosc_base;
uintptr_t armpll_base;
uintptr_t armdfs_base;
uintptr_t cgm0_base;
uintptr_t cgm1_base;
};
@ -40,6 +42,8 @@ static struct s32cc_clk_drv *get_drv(void)
static struct s32cc_clk_drv driver = {
.fxosc_base = FXOSC_BASE_ADDR,
.armpll_base = ARMPLL_BASE_ADDR,
.armdfs_base = ARM_DFS_BASE_ADDR,
.cgm0_base = CGM0_BASE_ADDR,
.cgm1_base = CGM1_BASE_ADDR,
};
@ -87,6 +91,12 @@ static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *d
case S32CC_ARM_PLL:
*base = drv->armpll_base;
break;
case S32CC_ARM_DFS:
*base = drv->armdfs_base;
break;
case S32CC_CGM0:
*base = drv->cgm0_base;
break;
case S32CC_CGM1:
*base = drv->cgm1_base;
break;
@ -542,6 +552,9 @@ static int enable_mux(const struct s32cc_clk_obj *module,
case S32CC_CGM1:
ret = enable_cgm_mux(mux, drv);
break;
case S32CC_CGM0:
ret = enable_cgm_mux(mux, drv);
break;
default:
ERROR("Unknown mux parent type: %d\n", mux->module);
ret = -EINVAL;
@ -551,6 +564,199 @@ static int enable_mux(const struct s32cc_clk_obj *module,
return ret;
}
static int enable_dfs(const struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
unsigned int *depth)
{
int ret = 0;
ret = update_stack_depth(depth);
if (ret != 0) {
return ret;
}
return 0;
}
static struct s32cc_dfs *get_div_dfs(const struct s32cc_dfs_div *dfs_div)
{
const struct s32cc_clk_obj *parent = dfs_div->parent;
if (parent->type != s32cc_dfs_t) {
ERROR("DFS DIV doesn't have a DFS as parent\n");
return NULL;
}
return s32cc_obj2dfs(parent);
}
static struct s32cc_pll *dfsdiv2pll(const struct s32cc_dfs_div *dfs_div)
{
const struct s32cc_clk_obj *parent;
const struct s32cc_dfs *dfs;
dfs = get_div_dfs(dfs_div);
if (dfs == NULL) {
return NULL;
}
parent = dfs->parent;
if (parent->type != s32cc_pll_t) {
return NULL;
}
return s32cc_obj2pll(parent);
}
static int get_dfs_mfi_mfn(unsigned long dfs_freq, const struct s32cc_dfs_div *dfs_div,
uint32_t *mfi, uint32_t *mfn)
{
uint64_t factor64, tmp64, ofreq;
uint32_t factor32;
unsigned long in = dfs_freq;
unsigned long out = dfs_div->freq;
/**
* factor = (IN / OUT) / 2
* MFI = integer(factor)
* MFN = (factor - MFI) * 36
*/
factor64 = ((((uint64_t)in) * FP_PRECISION) / ((uint64_t)out)) / 2ULL;
tmp64 = factor64 / FP_PRECISION;
if (tmp64 > UINT32_MAX) {
return -EINVAL;
}
factor32 = (uint32_t)tmp64;
*mfi = factor32;
tmp64 = ((factor64 - ((uint64_t)*mfi * FP_PRECISION)) * 36UL) / FP_PRECISION;
if (tmp64 > UINT32_MAX) {
return -EINVAL;
}
*mfn = (uint32_t)tmp64;
/* div_freq = in / (2 * (*mfi + *mfn / 36.0)) */
factor64 = (((uint64_t)*mfn) * FP_PRECISION) / 36ULL;
factor64 += ((uint64_t)*mfi) * FP_PRECISION;
factor64 *= 2ULL;
ofreq = (((uint64_t)in) * FP_PRECISION) / factor64;
if (ofreq != dfs_div->freq) {
ERROR("Failed to find MFI and MFN settings for DFS DIV freq %lu\n",
dfs_div->freq);
ERROR("Nearest freq = %" PRIx64 "\n", ofreq);
return -EINVAL;
}
return 0;
}
static int init_dfs_port(uintptr_t dfs_addr, uint32_t port,
uint32_t mfi, uint32_t mfn)
{
uint32_t portsr, portolsr;
uint32_t mask, old_mfi, old_mfn;
uint32_t dvport;
bool init_dfs;
dvport = mmio_read_32(DFS_DVPORTn(dfs_addr, port));
old_mfi = DFS_DVPORTn_MFI(dvport);
old_mfn = DFS_DVPORTn_MFN(dvport);
portsr = mmio_read_32(DFS_PORTSR(dfs_addr));
portolsr = mmio_read_32(DFS_PORTOLSR(dfs_addr));
/* Skip configuration if it's not needed */
if (((portsr & BIT_32(port)) != 0U) &&
((portolsr & BIT_32(port)) == 0U) &&
(mfi == old_mfi) && (mfn == old_mfn)) {
return 0;
}
init_dfs = (portsr == 0U);
if (init_dfs) {
mask = DFS_PORTRESET_MASK;
} else {
mask = DFS_PORTRESET_SET(BIT_32(port));
}
mmio_write_32(DFS_PORTOLSR(dfs_addr), mask);
mmio_write_32(DFS_PORTRESET(dfs_addr), mask);
while ((mmio_read_32(DFS_PORTSR(dfs_addr)) & mask) != 0U) {
}
if (init_dfs) {
mmio_write_32(DFS_CTL(dfs_addr), DFS_CTL_RESET);
}
mmio_write_32(DFS_DVPORTn(dfs_addr, port),
DFS_DVPORTn_MFI_SET(mfi) | DFS_DVPORTn_MFN_SET(mfn));
if (init_dfs) {
/* DFS clk enable programming */
mmio_clrbits_32(DFS_CTL(dfs_addr), DFS_CTL_RESET);
}
mmio_clrbits_32(DFS_PORTRESET(dfs_addr), BIT_32(port));
while ((mmio_read_32(DFS_PORTSR(dfs_addr)) & BIT_32(port)) != BIT_32(port)) {
}
portolsr = mmio_read_32(DFS_PORTOLSR(dfs_addr));
if ((portolsr & DFS_PORTOLSR_LOL(port)) != 0U) {
ERROR("Failed to lock DFS divider\n");
return -EINVAL;
}
return 0;
}
static int enable_dfs_div(const struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
unsigned int *depth)
{
const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
const struct s32cc_pll *pll;
const struct s32cc_dfs *dfs;
uintptr_t dfs_addr = 0UL;
uint32_t mfi, mfn;
int ret = 0;
ret = update_stack_depth(depth);
if (ret != 0) {
return ret;
}
dfs = get_div_dfs(dfs_div);
if (dfs == NULL) {
return -EINVAL;
}
pll = dfsdiv2pll(dfs_div);
if (pll == NULL) {
ERROR("Failed to identify DFS divider's parent\n");
return -EINVAL;
}
ret = get_base_addr(dfs->instance, drv, &dfs_addr);
if ((ret != 0) || (dfs_addr == 0UL)) {
return -EINVAL;
}
ret = get_dfs_mfi_mfn(pll->vco_freq, dfs_div, &mfi, &mfn);
if (ret != 0) {
return -EINVAL;
}
return init_dfs_port(dfs_addr, dfs_div->index, mfi, mfn);
}
static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth)
{
const struct s32cc_clk_drv *drv = get_drv();
@ -587,6 +793,12 @@ static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth
case s32cc_fixed_div_t:
ret = -ENOTSUP;
break;
case s32cc_dfs_t:
ret = enable_dfs(module, drv, depth);
break;
case s32cc_dfs_div_t:
ret = enable_dfs_div(module, drv, depth);
break;
default:
ret = -EINVAL;
break;
@ -793,6 +1005,42 @@ static int set_mux_freq(const struct s32cc_clk_obj *module, unsigned long rate,
return set_module_rate(&clk->desc, rate, orate, depth);
}
static int set_dfs_div_freq(const struct s32cc_clk_obj *module, unsigned long rate,
unsigned long *orate, unsigned int *depth)
{
struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
const struct s32cc_dfs *dfs;
int ret;
ret = update_stack_depth(depth);
if (ret != 0) {
return ret;
}
if (dfs_div->parent == NULL) {
ERROR("Failed to identify DFS divider's parent\n");
return -EINVAL;
}
/* Sanity check */
dfs = s32cc_obj2dfs(dfs_div->parent);
if (dfs->parent == NULL) {
ERROR("Failed to identify DFS's parent\n");
return -EINVAL;
}
if ((dfs_div->freq != 0U) && (dfs_div->freq != rate)) {
ERROR("DFS DIV frequency was already set to %lu\n",
dfs_div->freq);
return -EINVAL;
}
dfs_div->freq = rate;
*orate = rate;
return ret;
}
static int set_module_rate(const struct s32cc_clk_obj *module,
unsigned long rate, unsigned long *orate,
unsigned int *depth)
@ -804,6 +1052,8 @@ static int set_module_rate(const struct s32cc_clk_obj *module,
return ret;
}
ret = -EINVAL;
switch (module->type) {
case s32cc_clk_t:
ret = set_clk_freq(module, rate, orate, depth);
@ -826,8 +1076,13 @@ static int set_module_rate(const struct s32cc_clk_obj *module,
case s32cc_shared_clkmux_t:
ret = set_mux_freq(module, rate, orate, depth);
break;
case s32cc_dfs_t:
ERROR("Setting the frequency of a DFS is not allowed!");
break;
case s32cc_dfs_div_t:
ret = set_dfs_div_freq(module, rate, orate, depth);
break;
default:
ret = -EINVAL;
break;
}

54
drivers/nxp/clk/s32cc/s32cc_clk_modules.c
View file

@ -43,6 +43,45 @@ static struct s32cc_pll_out_div arm_pll_phi0_div =
static struct s32cc_clk arm_pll_phi0_clk =
S32CC_FREQ_MODULE_CLK(arm_pll_phi0_div, 0, GHZ);
/* ARM DFS */
static struct s32cc_dfs armdfs =
S32CC_DFS_INIT(armpll, S32CC_ARM_DFS);
static struct s32cc_dfs_div arm_dfs1_div =
S32CC_DFS_DIV_INIT(armdfs, 0);
static struct s32cc_clk arm_dfs1_clk =
S32CC_FREQ_MODULE_CLK(arm_dfs1_div, 0, 800 * MHZ);
/* MC_CGM0 */
static struct s32cc_clkmux cgm0_mux0 =
S32CC_SHARED_CLKMUX_INIT(S32CC_CGM0, 0, 2,
S32CC_CLK_FIRC,
S32CC_CLK_ARM_PLL_DFS1, 0, 0, 0);
static struct s32cc_clk cgm0_mux0_clk = S32CC_MODULE_CLK(cgm0_mux0);
/* XBAR */
static struct s32cc_clk xbar_2x_clk =
S32CC_CHILD_CLK(cgm0_mux0_clk, 48 * MHZ, 800 * MHZ);
static struct s32cc_fixed_div xbar_div2 =
S32CC_FIXED_DIV_INIT(cgm0_mux0_clk, 2);
static struct s32cc_clk xbar_clk =
S32CC_FREQ_MODULE_CLK(xbar_div2, 24 * MHZ, 400 * MHZ);
static struct s32cc_fixed_div xbar_div4 =
S32CC_FIXED_DIV_INIT(cgm0_mux0_clk, 4);
static struct s32cc_clk xbar_div2_clk =
S32CC_FREQ_MODULE_CLK(xbar_div4, 12 * MHZ, 200 * MHZ);
static struct s32cc_fixed_div xbar_div6 =
S32CC_FIXED_DIV_INIT(cgm0_mux0_clk, 6);
static struct s32cc_clk xbar_div3_clk =
S32CC_FREQ_MODULE_CLK(xbar_div6, 8 * MHZ, 133333333);
static struct s32cc_fixed_div xbar_div8 =
S32CC_FIXED_DIV_INIT(cgm0_mux0_clk, 8);
static struct s32cc_clk xbar_div4_clk =
S32CC_FREQ_MODULE_CLK(xbar_div8, 6 * MHZ, 100 * MHZ);
static struct s32cc_fixed_div xbar_div12 =
S32CC_FIXED_DIV_INIT(cgm0_mux0_clk, 12);
static struct s32cc_clk xbar_div6_clk =
S32CC_FREQ_MODULE_CLK(xbar_div12, 4 * MHZ, 66666666);
/* MC_CGM1 */
static struct s32cc_clkmux cgm1_mux0 =
S32CC_SHARED_CLKMUX_INIT(S32CC_CGM1, 0, 3,
@ -68,13 +107,15 @@ static struct s32cc_clk a53_core_div10_clk =
S32CC_FREQ_MODULE_CLK(a53_core_div10, S32CC_A53_MIN_FREQ / 10,
S32CC_A53_MAX_FREQ / 10);
static struct s32cc_clk *s32cc_hw_clk_list[5] = {
static struct s32cc_clk *s32cc_hw_clk_list[13] = {
/* Oscillators */
[S32CC_CLK_ID(S32CC_CLK_FIRC)] = &firc_clk,
[S32CC_CLK_ID(S32CC_CLK_SIRC)] = &sirc_clk,
[S32CC_CLK_ID(S32CC_CLK_FXOSC)] = &fxosc_clk,
/* ARM PLL */
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_PHI0)] = &arm_pll_phi0_clk,
/* ARM DFS */
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_DFS1)] = &arm_dfs1_clk,
};
static struct s32cc_clk_array s32cc_hw_clocks = {
@ -83,10 +124,19 @@ static struct s32cc_clk_array s32cc_hw_clocks = {
.n_clks = ARRAY_SIZE(s32cc_hw_clk_list),
};
static struct s32cc_clk *s32cc_arch_clk_list[6] = {
static struct s32cc_clk *s32cc_arch_clk_list[13] = {
/* ARM PLL */
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_MUX)] = &arm_pll_mux_clk,
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_VCO)] = &arm_pll_vco_clk,
/* MC_CGM0 */
[S32CC_CLK_ID(S32CC_CLK_MC_CGM0_MUX0)] = &cgm0_mux0_clk,
/* XBAR */
[S32CC_CLK_ID(S32CC_CLK_XBAR_2X)] = &xbar_2x_clk,
[S32CC_CLK_ID(S32CC_CLK_XBAR)] = &xbar_clk,
[S32CC_CLK_ID(S32CC_CLK_XBAR_DIV2)] = &xbar_div2_clk,
[S32CC_CLK_ID(S32CC_CLK_XBAR_DIV3)] = &xbar_div3_clk,
[S32CC_CLK_ID(S32CC_CLK_XBAR_DIV4)] = &xbar_div4_clk,
[S32CC_CLK_ID(S32CC_CLK_XBAR_DIV6)] = &xbar_div6_clk,
/* MC_CGM1 */
[S32CC_CLK_ID(S32CC_CLK_MC_CGM1_MUX0)] = &cgm1_mux0_clk,
/* A53 */

113
drivers/nxp/clk/s32cc/s32cc_early_clks.c
View file

@ -12,28 +12,34 @@
#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
#define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ)
#define S32CC_A53_FREQ (1U * GHZ)
#define S32CC_XBAR_2X_FREQ (800U * MHZ)
int s32cc_init_early_clks(void)
static int enable_fxosc_clk(void)
{
int ret;
s32cc_clk_register_drv();
ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL);
if (ret != 0) {
return ret;
}
ret = clk_enable(S32CC_CLK_FXOSC);
if (ret != 0) {
return ret;
}
return ret;
}
static int enable_arm_pll(void)
{
int ret;
ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC);
if (ret != 0) {
return ret;
}
ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0);
if (ret != 0) {
return ret;
}
ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL);
if (ret != 0) {
return ret;
}
ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL);
if (ret != 0) {
return ret;
@ -44,16 +50,6 @@ int s32cc_init_early_clks(void)
return ret;
}
ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL);
if (ret != 0) {
return ret;
}
ret = clk_enable(S32CC_CLK_FXOSC);
if (ret != 0) {
return ret;
}
ret = clk_enable(S32CC_CLK_ARM_PLL_VCO);
if (ret != 0) {
return ret;
@ -64,6 +60,23 @@ int s32cc_init_early_clks(void)
return ret;
}
return ret;
}
static int enable_a53_clk(void)
{
int ret;
ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0);
if (ret != 0) {
return ret;
}
ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL);
if (ret != 0) {
return ret;
}
ret = clk_enable(S32CC_CLK_A53_CORE);
if (ret != 0) {
return ret;
@ -71,3 +84,59 @@ int s32cc_init_early_clks(void)
return ret;
}
static int enable_xbar_clk(void)
{
int ret;
ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX0, S32CC_CLK_ARM_PLL_DFS1);
if (ret != 0) {
return ret;
}
ret = clk_set_rate(S32CC_CLK_XBAR_2X, S32CC_XBAR_2X_FREQ, NULL);
if (ret != 0) {
return ret;
}
ret = clk_enable(S32CC_CLK_ARM_PLL_DFS1);
if (ret != 0) {
return ret;
}
ret = clk_enable(S32CC_CLK_XBAR_2X);
if (ret != 0) {
return ret;
}
return ret;
}
int s32cc_init_early_clks(void)
{
int ret;
s32cc_clk_register_drv();
ret = enable_fxosc_clk();
if (ret != 0) {
return ret;
}
ret = enable_arm_pll();
if (ret != 0) {
return ret;
}
ret = enable_a53_clk();
if (ret != 0) {
return ret;
}
ret = enable_xbar_clk();
if (ret != 0) {
return ret;
}
return ret;
}

9
include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
View file

@ -78,4 +78,13 @@
#define S32CC_CLK_A53_CORE_DIV2 S32CC_ARCH_CLK(4)
#define S32CC_CLK_A53_CORE_DIV10 S32CC_ARCH_CLK(5)
/* XBAR clock*/
#define S32CC_CLK_MC_CGM0_MUX0 S32CC_ARCH_CLK(6)
#define S32CC_CLK_XBAR_2X S32CC_ARCH_CLK(7)
#define S32CC_CLK_XBAR S32CC_ARCH_CLK(8)
#define S32CC_CLK_XBAR_DIV2 S32CC_ARCH_CLK(9)
#define S32CC_CLK_XBAR_DIV3 S32CC_ARCH_CLK(10)
#define S32CC_CLK_XBAR_DIV4 S32CC_ARCH_CLK(11)
#define S32CC_CLK_XBAR_DIV6 S32CC_ARCH_CLK(12)
#endif /* S32CC_CLK_IDS_H */

74
include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
View file

@ -17,6 +17,8 @@ enum s32cc_clkm_type {
s32cc_clk_t,
s32cc_pll_t,
s32cc_pll_out_div_t,
s32cc_dfs_t,
s32cc_dfs_div_t,
s32cc_clkmux_t,
s32cc_shared_clkmux_t,
s32cc_fixed_div_t,
@ -27,6 +29,8 @@ enum s32cc_clk_source {
S32CC_FXOSC,
S32CC_SIRC,
S32CC_ARM_PLL,
S32CC_ARM_DFS,
S32CC_CGM0,
S32CC_CGM1,
};
@ -122,6 +126,38 @@ struct s32cc_pll_out_div {
.index = (INDEX), \
}
struct s32cc_dfs {
struct s32cc_clk_obj desc;
struct s32cc_clk_obj *parent;
enum s32cc_clk_source instance;
uintptr_t base;
};
#define S32CC_DFS_INIT(PARENT, INSTANCE) \
{ \
.desc = { \
.type = s32cc_dfs_t, \
}, \
.parent = &(PARENT).desc, \
.instance = (INSTANCE), \
}
struct s32cc_dfs_div {
struct s32cc_clk_obj desc;
struct s32cc_clk_obj *parent;
uint32_t index;
unsigned long freq;
};
#define S32CC_DFS_DIV_INIT(PARENT, INDEX) \
{ \
.desc = { \
.type = s32cc_dfs_div_t, \
}, \
.parent = &(PARENT).desc, \
.index = (INDEX), \
}
struct s32cc_fixed_div {
struct s32cc_clk_obj desc;
struct s32cc_clk_obj *parent;
@ -151,22 +187,26 @@ struct s32cc_clk_array {
size_t n_clks;
};
#define S32CC_FREQ_MODULE(PARENT_MODULE, MIN_F, MAX_F) \
{ \
.desc = { \
.type = s32cc_clk_t, \
}, \
.module = &(PARENT_MODULE).desc, \
.min_freq = (MIN_F), \
.max_freq = (MAX_F), \
#define S32CC_FREQ_CLK(PARENT_MODULE, PARENT, MIN_F, MAX_F) \
{ \
.desc = { \
.type = s32cc_clk_t, \
}, \
.pclock = (PARENT), \
.module = (PARENT_MODULE), \
.min_freq = (MIN_F), \
.max_freq = (MAX_F), \
}
#define S32CC_FREQ_MODULE_CLK(PARENT_MODULE, MIN_F, MAX_F) \
S32CC_FREQ_MODULE(PARENT_MODULE, MIN_F, MAX_F)
S32CC_FREQ_CLK(&(PARENT_MODULE).desc, NULL, MIN_F, MAX_F)
#define S32CC_MODULE_CLK(PARENT_MODULE) \
S32CC_FREQ_MODULE_CLK(PARENT_MODULE, 0, 0)
#define S32CC_CHILD_CLK(PARENT, MIN_F, MAX_F) \
S32CC_FREQ_CLK(NULL, &(PARENT), MIN_F, MAX_F)
static inline struct s32cc_osc *s32cc_obj2osc(const struct s32cc_clk_obj *mod)
{
uintptr_t osc_addr;
@ -237,4 +277,20 @@ static inline struct s32cc_fixed_div *s32cc_obj2fixeddiv(const struct s32cc_clk_
return (struct s32cc_fixed_div *)fdiv_addr;
}
static inline struct s32cc_dfs *s32cc_obj2dfs(const struct s32cc_clk_obj *mod)
{
uintptr_t dfs_addr;
dfs_addr = ((uintptr_t)mod) - offsetof(struct s32cc_dfs, desc);
return (struct s32cc_dfs *)dfs_addr;
}
static inline struct s32cc_dfs_div *s32cc_obj2dfsdiv(const struct s32cc_clk_obj *mod)
{
uintptr_t dfs_div_addr;
dfs_div_addr = ((uintptr_t)mod) - offsetof(struct s32cc_dfs_div, desc);
return (struct s32cc_dfs_div *)dfs_div_addr;
}
#endif /* S32CC_CLK_MODULES_H */