mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
Merge changes from topic "enable_a53_clk" into integration
* changes: feat(nxp-clk): enable the A53 clock feat(nxp-clk): add ARM PLL ODIV enablement feat(nxp-clk): add ARM PLL enablement feat(nxp-clk): set rate for clock muxes
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
9babc7c2d6
3 changed files with 541 additions and 8 deletions
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@ -8,6 +8,8 @@
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#include <lib/utils_def.h>
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#define FXOSC_BASE_ADDR (0x40050000UL)
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#define ARMPLL_BASE_ADDR (0x40038000UL)
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#define CGM1_BASE_ADDR (0x40034000UL)
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/* FXOSC */
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#define FXOSC_CTRL(FXOSC) ((FXOSC) + 0x0UL)
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@ -26,4 +28,59 @@
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#define FXOSC_STAT(FXOSC) ((FXOSC) + 0x4UL)
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#define FXOSC_STAT_OSC_STAT BIT_32(31U)
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/* PLL */
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#define PLLDIG_PLLCR(PLL) ((PLL) + 0x0UL)
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#define PLLDIG_PLLCR_PLLPD BIT_32(31U)
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#define PLLDIG_PLLSR(PLL) ((PLL) + 0x4UL)
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#define PLLDIG_PLLSR_LOCK BIT_32(2U)
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#define PLLDIG_PLLDV(PLL) ((PLL) + 0x8UL)
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#define PLLDIG_PLLDV_RDIV_OFFSET 12U
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#define PLLDIG_PLLDV_RDIV_MASK GENMASK_32(14U, PLLDIG_PLLDV_RDIV_OFFSET)
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#define PLLDIG_PLLDV_RDIV_SET(VAL) (PLLDIG_PLLDV_RDIV_MASK & \
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((VAL) << PLLDIG_PLLDV_RDIV_OFFSET))
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#define PLLDIG_PLLDV_MFI_MASK GENMASK_32(7U, 0U)
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#define PLLDIG_PLLDV_MFI(DIV) (PLLDIG_PLLDV_MFI_MASK & (DIV))
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#define PLLDIG_PLLFD(PLL) ((PLL) + 0x10UL)
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#define PLLDIG_PLLFD_SMDEN BIT_32(30U)
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#define PLLDIG_PLLFD_MFN_MASK GENMASK_32(14U, 0U)
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#define PLLDIG_PLLFD_MFN_SET(VAL) (PLLDIG_PLLFD_MFN_MASK & (VAL))
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#define PLLDIG_PLLCLKMUX(PLL) ((PLL) + 0x20UL)
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#define PLLDIG_PLLODIV(PLL, N) ((PLL) + 0x80UL + ((N) * 0x4UL))
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#define PLLDIG_PLLODIV_DE BIT_32(31U)
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#define PLLDIG_PLLODIV_DIV_OFFSET 16U
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#define PLLDIG_PLLODIV_DIV_MASK GENMASK_32(23U, PLLDIG_PLLODIV_DIV_OFFSET)
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#define PLLDIG_PLLODIV_DIV(VAL) (((VAL) & PLLDIG_PLLODIV_DIV_MASK) >> \
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PLLDIG_PLLODIV_DIV_OFFSET)
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#define PLLDIG_PLLODIV_DIV_SET(VAL) (PLLDIG_PLLODIV_DIV_MASK & ((VAL) << \
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PLLDIG_PLLODIV_DIV_OFFSET))
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/* MMC_CGM */
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#define CGM_MUXn_CSC(CGM_ADDR, MUX) ((CGM_ADDR) + 0x300UL + ((MUX) * 0x40UL))
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#define MC_CGM_MUXn_CSC_SELCTL_OFFSET 24U
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#define MC_CGM_MUXn_CSC_SELCTL_MASK GENMASK_32(29U, MC_CGM_MUXn_CSC_SELCTL_OFFSET)
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#define MC_CGM_MUXn_CSC_SELCTL(val) (MC_CGM_MUXn_CSC_SELCTL_MASK & ((val) \
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<< MC_CGM_MUXn_CSC_SELCTL_OFFSET))
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#define MC_CGM_MUXn_CSC_CLK_SW BIT_32(2U)
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#define MC_CGM_MUXn_CSC_SAFE_SW BIT_32(3U)
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#define CGM_MUXn_CSS(CGM_ADDR, MUX) ((CGM_ADDR) + 0x304UL + ((MUX) * 0x40UL))
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#define MC_CGM_MUXn_CSS_SELSTAT_OFFSET 24U
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#define MC_CGM_MUXn_CSS_SELSTAT_MASK GENMASK_32(29U, MC_CGM_MUXn_CSS_SELSTAT_OFFSET)
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#define MC_CGM_MUXn_CSS_SELSTAT(css) ((MC_CGM_MUXn_CSS_SELSTAT_MASK & (css))\
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>> MC_CGM_MUXn_CSS_SELSTAT_OFFSET)
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#define MC_CGM_MUXn_CSS_SWTRG(css) ((MC_CGM_MUXn_CSS_SWTRG_MASK & (css)) \
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>> MC_CGM_MUXn_CSS_SWTRG_OFFSET)
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#define MC_CGM_MUXn_CSS_SWTRG_OFFSET 17U
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#define MC_CGM_MUXn_CSS_SWTRG_MASK GENMASK_32(19U, MC_CGM_MUXn_CSS_SWTRG_OFFSET)
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#define MC_CGM_MUXn_CSS_SWTRG_SUCCESS 0x1U
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#define MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK 0x4U
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#define MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK_INACTIVE 0x5U
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#define MC_CGM_MUXn_CSS_SWIP BIT_32(16U)
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#define MC_CGM_MUXn_CSS_SAFE_SW BIT_32(3U)
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#endif /* S32CC_CLK_REGS_H */
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@ -10,13 +10,19 @@
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#include <common/debug.h>
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#include <drivers/clk.h>
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#include <lib/mmio.h>
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#include <s32cc-clk-ids.h>
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#include <s32cc-clk-modules.h>
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#include <s32cc-clk-utils.h>
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#define MAX_STACK_DEPTH (15U)
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/* This is used for floating-point precision calculations. */
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#define FP_PRECISION (100000000UL)
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struct s32cc_clk_drv {
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uintptr_t fxosc_base;
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uintptr_t armpll_base;
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uintptr_t cgm1_base;
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};
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static int update_stack_depth(unsigned int *depth)
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@ -33,6 +39,8 @@ static struct s32cc_clk_drv *get_drv(void)
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{
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static struct s32cc_clk_drv driver = {
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.fxosc_base = FXOSC_BASE_ADDR,
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.armpll_base = ARMPLL_BASE_ADDR,
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.cgm1_base = CGM1_BASE_ADDR,
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};
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return &driver;
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@ -67,6 +75,37 @@ static int enable_clk_module(const struct s32cc_clk_obj *module,
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return -EINVAL;
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}
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static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *drv,
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uintptr_t *base)
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{
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int ret = 0;
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switch (id) {
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case S32CC_FXOSC:
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*base = drv->fxosc_base;
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break;
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case S32CC_ARM_PLL:
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*base = drv->armpll_base;
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break;
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case S32CC_CGM1:
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*base = drv->cgm1_base;
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break;
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case S32CC_FIRC:
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break;
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case S32CC_SIRC:
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break;
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default:
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ret = -EINVAL;
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break;
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}
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if (ret != 0) {
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ERROR("Unknown clock source id: %u\n", id);
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}
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return ret;
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}
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static void enable_fxosc(const struct s32cc_clk_drv *drv)
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{
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uintptr_t fxosc_base = drv->fxosc_base;
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@ -121,6 +160,397 @@ static int enable_osc(const struct s32cc_clk_obj *module,
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return ret;
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}
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static int get_pll_mfi_mfn(unsigned long pll_vco, unsigned long ref_freq,
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uint32_t *mfi, uint32_t *mfn)
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{
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unsigned long vco;
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unsigned long mfn64;
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/* FRAC-N mode */
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*mfi = (uint32_t)(pll_vco / ref_freq);
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/* MFN formula : (double)(pll_vco % ref_freq) / ref_freq * 18432.0 */
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mfn64 = pll_vco % ref_freq;
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mfn64 *= FP_PRECISION;
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mfn64 /= ref_freq;
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mfn64 *= 18432UL;
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mfn64 /= FP_PRECISION;
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if (mfn64 > UINT32_MAX) {
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return -EINVAL;
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}
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*mfn = (uint32_t)mfn64;
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vco = ((unsigned long)*mfn * FP_PRECISION) / 18432UL;
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vco += (unsigned long)*mfi * FP_PRECISION;
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vco *= ref_freq;
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vco /= FP_PRECISION;
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if (vco != pll_vco) {
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ERROR("Failed to find MFI and MFN settings for PLL freq %lu. Nearest freq = %lu\n",
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pll_vco, vco);
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return -EINVAL;
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}
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return 0;
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}
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static struct s32cc_clkmux *get_pll_mux(const struct s32cc_pll *pll)
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{
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const struct s32cc_clk_obj *source = pll->source;
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const struct s32cc_clk *clk;
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if (source == NULL) {
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ERROR("Failed to identify PLL's parent\n");
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return NULL;
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}
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if (source->type != s32cc_clk_t) {
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ERROR("The parent of the PLL isn't a clock\n");
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return NULL;
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}
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clk = s32cc_obj2clk(source);
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if (clk->module == NULL) {
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ERROR("The clock isn't connected to a module\n");
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return NULL;
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}
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source = clk->module;
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if ((source->type != s32cc_clkmux_t) &&
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(source->type != s32cc_shared_clkmux_t)) {
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ERROR("The parent of the PLL isn't a MUX\n");
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return NULL;
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}
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return s32cc_obj2clkmux(source);
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}
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static void disable_odiv(uintptr_t pll_addr, uint32_t div_index)
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{
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mmio_clrbits_32(PLLDIG_PLLODIV(pll_addr, div_index), PLLDIG_PLLODIV_DE);
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}
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static void enable_odiv(uintptr_t pll_addr, uint32_t div_index)
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{
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mmio_setbits_32(PLLDIG_PLLODIV(pll_addr, div_index), PLLDIG_PLLODIV_DE);
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}
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static void disable_odivs(uintptr_t pll_addr, uint32_t ndivs)
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{
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uint32_t i;
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for (i = 0; i < ndivs; i++) {
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disable_odiv(pll_addr, i);
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}
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}
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static void enable_pll_hw(uintptr_t pll_addr)
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{
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/* Enable the PLL. */
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mmio_write_32(PLLDIG_PLLCR(pll_addr), 0x0);
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/* Poll until PLL acquires lock. */
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while ((mmio_read_32(PLLDIG_PLLSR(pll_addr)) & PLLDIG_PLLSR_LOCK) == 0U) {
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}
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}
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static void disable_pll_hw(uintptr_t pll_addr)
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{
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mmio_write_32(PLLDIG_PLLCR(pll_addr), PLLDIG_PLLCR_PLLPD);
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}
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static int program_pll(const struct s32cc_pll *pll, uintptr_t pll_addr,
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const struct s32cc_clk_drv *drv, uint32_t sclk_id,
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unsigned long sclk_freq)
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{
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uint32_t rdiv = 1, mfi, mfn;
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int ret;
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ret = get_pll_mfi_mfn(pll->vco_freq, sclk_freq, &mfi, &mfn);
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if (ret != 0) {
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return -EINVAL;
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}
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/* Disable ODIVs*/
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disable_odivs(pll_addr, pll->ndividers);
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/* Disable PLL */
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disable_pll_hw(pll_addr);
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/* Program PLLCLKMUX */
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mmio_write_32(PLLDIG_PLLCLKMUX(pll_addr), sclk_id);
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/* Program VCO */
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mmio_clrsetbits_32(PLLDIG_PLLDV(pll_addr),
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PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK,
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PLLDIG_PLLDV_RDIV_SET(rdiv) | PLLDIG_PLLDV_MFI(mfi));
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mmio_write_32(PLLDIG_PLLFD(pll_addr),
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PLLDIG_PLLFD_MFN_SET(mfn) | PLLDIG_PLLFD_SMDEN);
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enable_pll_hw(pll_addr);
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return ret;
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}
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static int enable_pll(const struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int *depth)
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{
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const struct s32cc_pll *pll = s32cc_obj2pll(module);
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const struct s32cc_clkmux *mux;
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uintptr_t pll_addr = UL(0x0);
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unsigned long sclk_freq;
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uint32_t sclk_id;
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int ret;
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ret = update_stack_depth(depth);
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if (ret != 0) {
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return ret;
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}
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mux = get_pll_mux(pll);
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if (mux == NULL) {
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return -EINVAL;
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}
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if (pll->instance != mux->module) {
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ERROR("MUX type is not in sync with PLL ID\n");
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return -EINVAL;
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}
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ret = get_base_addr(pll->instance, drv, &pll_addr);
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if (ret != 0) {
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ERROR("Failed to detect PLL instance\n");
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return ret;
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}
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switch (mux->source_id) {
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case S32CC_CLK_FIRC:
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sclk_freq = 48U * MHZ;
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sclk_id = 0;
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break;
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case S32CC_CLK_FXOSC:
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sclk_freq = 40U * MHZ;
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sclk_id = 1;
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break;
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default:
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ERROR("Invalid source selection for PLL 0x%lx\n",
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pll_addr);
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return -EINVAL;
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};
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return program_pll(pll, pll_addr, drv, sclk_id, sclk_freq);
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}
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static inline struct s32cc_pll *get_div_pll(const struct s32cc_pll_out_div *pdiv)
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{
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const struct s32cc_clk_obj *parent;
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parent = pdiv->parent;
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if (parent == NULL) {
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ERROR("Failed to identify PLL divider's parent\n");
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return NULL;
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}
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if (parent->type != s32cc_pll_t) {
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ERROR("The parent of the divider is not a PLL instance\n");
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return NULL;
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}
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return s32cc_obj2pll(parent);
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}
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static void config_pll_out_div(uintptr_t pll_addr, uint32_t div_index, uint32_t dc)
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{
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uint32_t pllodiv;
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uint32_t pdiv;
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pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, div_index));
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pdiv = PLLDIG_PLLODIV_DIV(pllodiv);
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if (((pdiv + 1U) == dc) && ((pllodiv & PLLDIG_PLLODIV_DE) != 0U)) {
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return;
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}
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if ((pllodiv & PLLDIG_PLLODIV_DE) != 0U) {
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disable_odiv(pll_addr, div_index);
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}
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pllodiv = PLLDIG_PLLODIV_DIV_SET(dc - 1U);
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mmio_write_32(PLLDIG_PLLODIV(pll_addr, div_index), pllodiv);
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enable_odiv(pll_addr, div_index);
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}
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|
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static int enable_pll_div(const struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int *depth)
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{
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const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
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uintptr_t pll_addr = 0x0ULL;
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const struct s32cc_pll *pll;
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uint32_t dc;
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int ret;
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ret = update_stack_depth(depth);
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if (ret != 0) {
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return ret;
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}
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pll = get_div_pll(pdiv);
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if (pll == NULL) {
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ERROR("The parent of the PLL DIV is invalid\n");
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return 0;
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}
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|
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ret = get_base_addr(pll->instance, drv, &pll_addr);
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if (ret != 0) {
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ERROR("Failed to detect PLL instance\n");
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return -EINVAL;
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}
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dc = (uint32_t)(pll->vco_freq / pdiv->freq);
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config_pll_out_div(pll_addr, pdiv->index, dc);
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return 0;
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}
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static int cgm_mux_clk_config(uintptr_t cgm_addr, uint32_t mux, uint32_t source,
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bool safe_clk)
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{
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uint32_t css, csc;
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css = mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux));
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/* Already configured */
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if ((MC_CGM_MUXn_CSS_SELSTAT(css) == source) &&
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(MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SUCCESS) &&
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((css & MC_CGM_MUXn_CSS_SWIP) == 0U) && !safe_clk) {
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return 0;
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}
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/* Ongoing clock switch? */
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while ((mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)) &
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MC_CGM_MUXn_CSS_SWIP) != 0U) {
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}
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csc = mmio_read_32(CGM_MUXn_CSC(cgm_addr, mux));
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/* Clear previous source. */
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csc &= ~(MC_CGM_MUXn_CSC_SELCTL_MASK);
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if (!safe_clk) {
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/* Select the clock source and trigger the clock switch. */
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csc |= MC_CGM_MUXn_CSC_SELCTL(source) | MC_CGM_MUXn_CSC_CLK_SW;
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} else {
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/* Switch to safe clock */
|
||||
csc |= MC_CGM_MUXn_CSC_SAFE_SW;
|
||||
}
|
||||
|
||||
mmio_write_32(CGM_MUXn_CSC(cgm_addr, mux), csc);
|
||||
|
||||
/* Wait for configuration bit to auto-clear. */
|
||||
while ((mmio_read_32(CGM_MUXn_CSC(cgm_addr, mux)) &
|
||||
MC_CGM_MUXn_CSC_CLK_SW) != 0U) {
|
||||
}
|
||||
|
||||
/* Is the clock switch completed? */
|
||||
while ((mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)) &
|
||||
MC_CGM_MUXn_CSS_SWIP) != 0U) {
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if the switch succeeded.
|
||||
* Check switch trigger cause and the source.
|
||||
*/
|
||||
css = mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux));
|
||||
if (!safe_clk) {
|
||||
if ((MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SUCCESS) &&
|
||||
(MC_CGM_MUXn_CSS_SELSTAT(css) == source)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
ERROR("Failed to change the source of mux %" PRIu32 " to %" PRIu32 " (CGM=%lu)\n",
|
||||
mux, source, cgm_addr);
|
||||
} else {
|
||||
if (((MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK) ||
|
||||
(MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK_INACTIVE)) &&
|
||||
((MC_CGM_MUXn_CSS_SAFE_SW & css) != 0U)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
ERROR("The switch of mux %" PRIu32 " (CGM=%lu) to safe clock failed\n",
|
||||
mux, cgm_addr);
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int enable_cgm_mux(const struct s32cc_clkmux *mux,
|
||||
const struct s32cc_clk_drv *drv)
|
||||
{
|
||||
uintptr_t cgm_addr = UL(0x0);
|
||||
uint32_t mux_hw_clk;
|
||||
int ret;
|
||||
|
||||
ret = get_base_addr(mux->module, drv, &cgm_addr);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
mux_hw_clk = (uint32_t)S32CC_CLK_ID(mux->source_id);
|
||||
|
||||
return cgm_mux_clk_config(cgm_addr, mux->index,
|
||||
mux_hw_clk, false);
|
||||
}
|
||||
|
||||
static int enable_mux(const struct s32cc_clk_obj *module,
|
||||
const struct s32cc_clk_drv *drv,
|
||||
unsigned int *depth)
|
||||
{
|
||||
const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
|
||||
const struct s32cc_clk *clk;
|
||||
int ret = 0;
|
||||
|
||||
ret = update_stack_depth(depth);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (mux == NULL) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
clk = s32cc_get_arch_clk(mux->source_id);
|
||||
if (clk == NULL) {
|
||||
ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n",
|
||||
mux->source_id, mux->index);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (mux->module) {
|
||||
/* PLL mux will be enabled by PLL setup */
|
||||
case S32CC_ARM_PLL:
|
||||
break;
|
||||
case S32CC_CGM1:
|
||||
ret = enable_cgm_mux(mux, drv);
|
||||
break;
|
||||
default:
|
||||
ERROR("Unknown mux parent type: %d\n", mux->module);
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
};
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth)
|
||||
{
|
||||
const struct s32cc_clk_drv *drv = get_drv();
|
||||
|
|
@ -142,16 +572,18 @@ static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth
|
|||
case s32cc_clk_t:
|
||||
ret = enable_clk_module(module, drv, depth);
|
||||
break;
|
||||
case s32cc_clkmux_t:
|
||||
ret = -ENOTSUP;
|
||||
break;
|
||||
case s32cc_shared_clkmux_t:
|
||||
ret = -ENOTSUP;
|
||||
break;
|
||||
case s32cc_pll_t:
|
||||
ret = -ENOTSUP;
|
||||
ret = enable_pll(module, drv, depth);
|
||||
break;
|
||||
case s32cc_pll_out_div_t:
|
||||
ret = enable_pll_div(module, drv, depth);
|
||||
break;
|
||||
case s32cc_clkmux_t:
|
||||
ret = enable_mux(module, drv, depth);
|
||||
break;
|
||||
case s32cc_shared_clkmux_t:
|
||||
ret = enable_mux(module, drv, depth);
|
||||
break;
|
||||
case s32cc_fixed_div_t:
|
||||
ret = -ENOTSUP;
|
||||
break;
|
||||
|
|
@ -340,6 +772,27 @@ static int set_fixed_div_freq(const struct s32cc_clk_obj *module, unsigned long
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int set_mux_freq(const struct s32cc_clk_obj *module, unsigned long rate,
|
||||
unsigned long *orate, unsigned int *depth)
|
||||
{
|
||||
const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
|
||||
const struct s32cc_clk *clk = s32cc_get_arch_clk(mux->source_id);
|
||||
int ret;
|
||||
|
||||
ret = update_stack_depth(depth);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (clk == NULL) {
|
||||
ERROR("Mux (id:%" PRIu8 ") without a valid source (%lu)\n",
|
||||
mux->index, mux->source_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return set_module_rate(&clk->desc, rate, orate, depth);
|
||||
}
|
||||
|
||||
static int set_module_rate(const struct s32cc_clk_obj *module,
|
||||
unsigned long rate, unsigned long *orate,
|
||||
unsigned int *depth)
|
||||
|
|
@ -368,8 +821,10 @@ static int set_module_rate(const struct s32cc_clk_obj *module,
|
|||
ret = set_fixed_div_freq(module, rate, orate, depth);
|
||||
break;
|
||||
case s32cc_clkmux_t:
|
||||
ret = set_mux_freq(module, rate, orate, depth);
|
||||
break;
|
||||
case s32cc_shared_clkmux_t:
|
||||
ret = -ENOTSUP;
|
||||
ret = set_mux_freq(module, rate, orate, depth);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#define S32CC_FXOSC_FREQ (40U * MHZ)
|
||||
#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
|
||||
#define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ)
|
||||
#define S32CC_A53_FREQ (1U * GHZ)
|
||||
|
||||
int s32cc_init_early_clks(void)
|
||||
{
|
||||
|
|
@ -43,10 +44,30 @@ int s32cc_init_early_clks(void)
|
|||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(S32CC_CLK_FXOSC);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(S32CC_CLK_ARM_PLL_VCO);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(S32CC_CLK_ARM_PLL_PHI0);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(S32CC_CLK_A53_CORE);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue