Commit graph

12770 commits

Author SHA1 Message Date
Sandrine Bailleux
1b4d99878c Merge "fix(doc): match boot-order size to implementation" into integration 2023-06-08 08:30:40 +02:00
Manish Pandey
f1a32f4978 Merge "chore(xilinx): replace ATF with TFA" into integration 2023-06-07 17:49:58 +02:00
Manish Pandey
f6bf4d6bc8 Merge changes from topic "hm/memmap-feat" into integration
* changes:
  feat(memmap): add topological memory view
  feat(memmap): add tabular memory use data
2023-06-07 17:48:14 +02:00
Manish Pandey
d4affdce80 Merge "fix(stm32mp1): add void entry in plat_def_toc_entries" into integration 2023-06-07 17:30:11 +02:00
Madhukar Pappireddy
c58a9c36fa Merge "fix(zynqmp): fix sdei arm_validate_ns_entrypoint()" into integration 2023-06-07 16:25:46 +02:00
Manish Pandey
6e1ae30725 Merge "fix(qemu): fix 32-bit builds with stack protector" into integration 2023-06-07 10:50:16 +02:00
Olivier Deprez
ab23061eb0 Merge changes from topic "bk/clearups" into integration
* changes:
  chore(rme): add make rule for SPD=spmd
  chore(bl1): remove redundant bl1_arch_next_el_setup
  chore(docs): remove control register setup section
  chore(pauth): remove redundant pauth_disable_el3() call
2023-06-07 10:13:17 +02:00
Michal Simek
3b3c70a418 fix(zynqmp): fix sdei arm_validate_ns_entrypoint()
Don't use BL31_LIMIT macro for validation logic directly but clearly
mark BL31_LIMIT as 64bit address to avoid compilation error when
-Werror=logical-op is passed.

Likely caused by ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE is in 64bit
logic 0x100000000 and compiler handles it as 32bit value. That's why
error is shown.

Use uint64_t variable for limit and also for base.

Here is command line to replicate this issue:
make realclean; make -j PLAT=zynqmp DEBUG=1 RESET_TO_BL31=1 \
SPD=tspd SDEI_SUPPORT=1 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 \
ZYNQMP_ATF_MEM_SIZE=0x00040000 all -Werror=logical-op

Also error which is coming:
plat/xilinx/zynqmp/zynqmp_sdei.c: In function
   'arm_validate_ns_entrypoint':
plat/xilinx/zynqmp/zynqmp_sdei.c:19:40: error: logical 'or' of
 collectively  exhaustive tests is always true [-Werror=logical-op]
   19 |         return (entrypoint < BL31_BASE ||
   entrypoint > BL31_LIMIT) ? 0 : -1;

Change-Id: Ie1f1b4d2cd94b977aebb72786ecace0b062da418
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-07 09:11:29 +02:00
Madhukar Pappireddy
396ea00a83 Merge changes I907f3862,Ie749ff06,If8da2bb1,I457deb0b into integration
* changes:
  fix(el3-spmc): validate shmem descriptor alignment
  refactor(el3-spmc): avoid using EINVAL
  fix(el3-spmc): avoid descriptor size calc overflow
  fix(el3-spmc): use uint64_t for 64-bit type
2023-06-06 22:12:02 +02:00
Sandrine Bailleux
201e3c78a7 Merge "chore(fconf): rename last occurences of set_fw_config_info()" into integration 2023-06-06 17:49:06 +02:00
Manish Pandey
e1c0a47267 Merge changes from topic "dummy_feat_aa32" into integration
* changes:
  feat(cpufeat): deny AArch64-only features when building for AArch32
  feat(cpufeat): add AArch32 PAN detection support
2023-06-06 16:50:36 +02:00
Manish Pandey
dbe4765c30 Merge "refactor(el3-spmc): avoid unneeded function call" into integration 2023-06-06 16:44:49 +02:00
Manish Pandey
f4c913630d Merge changes Ia052c7f9,If598680a,Ieae11722 into integration
* changes:
  refactor(el3-spmc): move function call out of loop
  refactor(el3-spmc): crash instead of reading OOB
  fix(el3-spmc): prevent total_page_count overflow
2023-06-06 16:43:53 +02:00
Madhukar Pappireddy
1d64109ece Merge changes from topic "st-fixes" into integration
* changes:
  fix(spi-nand): add Quad Enable management
  fix(st-clock): disabling CKPER clock is not functional on stm32mp13
  fix(st-uart): skip console flush if UART is disabled
  fix(st): flush UART at the end of uart_read()
  fix(stm32mp1): use the BSEC nodes compatible for stm32mp13
  fix(stm32mp13-fdts): correct the BSEC nodes compatible
  fix(stm32mp1-fdts): move /omit-if-no-ref/ to overlay files
  fix(stm32mp1): properly check PSCI functions return
2023-06-06 16:03:38 +02:00
Sandrine Bailleux
8dadc1e2a6 chore(fconf): rename last occurences of set_fw_config_info()
set_fw_config_info() interface got renamed into set_config_info() as
part of commit f441718936 ("lib/fconf:
Update 'set_fw_config_info' function"). Rename a few left-overs of the
old name.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I119719cd7f3ba544e0c4c438e5341d35c7b5bdc2
2023-06-06 14:38:34 +02:00
Sandrine Bailleux
e14b7acb49 Merge "refactor(fvp): nv ctr addr static helper function" into integration 2023-06-06 13:30:26 +02:00
Prasad Kummari
c8be2240d3 chore(xilinx): replace ATF with TFA
Since the Arm Trusted Firmware(ATF) has been renamed to Trusted
Firmware-A (TF-A), replace all the instances of ATF from code comments,
macros, variables and functions to TF-A.

Change-Id: Iab448d96158612a3effb4e49943f8d6cb43aaad5
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
2023-06-06 17:00:14 +05:30
Sandrine Bailleux
e9736a01a1 Merge changes from topic "version/0.1-gic" into integration
* changes:
  feat(qemu-sbsa): handle GIC base
  feat(qemu-sbsa): handle platform version
2023-06-06 11:08:42 +02:00
Olivier Deprez
4c8e1f9a35 Merge changes I21d65a88,I949cfce9,If4249f22,Id0451bd1,I9e930070, ... into integration
* changes:
  feat(mediatek): add APU watchdog timeout control
  feat(mt8188): add emi mpu protection for APU secure memory
  feat(mt8188): add devapc setting of apusys rcx
  feat(mt8188): add backup/restore function when power on/off
  feat(mediatek): add APU bootup control smc call
  feat(mt8188): enable apusys mailbox mpu protect
  feat(mt8188): enable apusys domain remap
  feat(mt8188): add apusys ao devapc setting
  feat(mt8188): increase TZRAM_SIZE from 192KB to 256KB
2023-06-06 09:31:05 +02:00
Chungying Lu
baa0d45ced feat(mediatek): add APU watchdog timeout control
Add APU watchdog timeout control.

Change-Id: I21d65a88d20b6b2752a75f74487b5fe6596ebdf7
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>
2023-06-06 13:45:40 +08:00
Chungying Lu
176846a50b feat(mt8188): add emi mpu protection for APU secure memory
Add emi mpu protection of APU secure memory.

Change-Id: I949cfce97565d8a313caae4ea41af60a171042a6
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>
2023-06-06 13:45:40 +08:00
Karl Li
5986ae57aa feat(mt8188): add devapc setting of apusys rcx
Apusys rcx is a subsys in apusys, and it is a basic domain of APU and
it connects several components in APU.
The devapc control of apusys rcx is also inside APU and it can only be
set when APU is powered on.
Then apusys kernel driver will trigger rcx devapc init by ATF smc call.

Change-Id: If4249f22a08690b1e4f5aa5f0cbfb54ccacf90e1
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
2023-06-06 13:45:40 +08:00
Chungying Lu
233d604f50 feat(mt8188): add backup/restore function when power on/off
Add APU backup/restore function when power on/off.

Change-Id: Id0451bd12f402e1acabeb5c12266a2e01836e9dd
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>
2023-06-06 13:45:40 +08:00
Chungying Lu
94a9e6243e feat(mediatek): add APU bootup control smc call
Add APU bootup control smc call.
The steps of bootup flow:
  1. set up APU config.
  2. reset APU.
  3. set up APU boot config.
  4. boot APU.

Change-Id: I9e930070a64c7c4dcaa3a8b3d28b897823e9f53c
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>
2023-06-06 13:45:40 +08:00
Karl Li
ad7673adef feat(mt8188): enable apusys mailbox mpu protect
Enable apusys mailbox mpu protect.

Change-Id: Idbf67084037b7ecf4926f57a901075f98540ee57
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
2023-06-06 13:45:40 +08:00
Karl Li
b5900c92a1 feat(mt8188): enable apusys domain remap
Enable apusys domain remap to protect no-protect memory.
  - Remap request which from domain 5 to domain 14.
  - Remap request which from domain 7 to domain 14.

Change-Id: Iccd188e3b8edbe916fa9767c841a844b66c6011f
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
2023-06-06 13:45:40 +08:00
Karl Li
777e3b71bb feat(mt8188): add apusys ao devapc setting
Apusys ao devapc is a set of control registers inside APU, and it
controls the access permission of APU ao domain.
Moreover, apusys ao devapc must be set after apusys power init, so
we need to place the drivers in TF-A instead of coreboot.

Change-Id: Ife849c32d4dd9dca15432d4b8a51753fde61b148
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
2023-06-06 13:45:40 +08:00
Karl Li
aa1cb279b6 feat(mt8188): increase TZRAM_SIZE from 192KB to 256KB
Increase TZRAM_SIZE to 256KB for MT8188 APUSYS.

Change-Id: Iabe1a4aeb79ba23c3e963170a8eb9ce19f2925f3
Signed-off-by: Karl Li <karl.li@mediatek.com>
2023-06-06 13:44:03 +08:00
Demi Marie Obenour
dd94372d77 fix(el3-spmc): validate shmem descriptor alignment
If the size of a shmem descriptor is not a multiple of 16, the
descriptor would be unusable, but the problem would be caught much
later.

Change-Id: I907f3862b55c6341e39a6b8b2e24784127230478
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2023-06-05 13:22:21 -04:00
Demi Marie Obenour
1198ff8424 refactor(el3-spmc): avoid unneeded function call
The information is already available inline.  No functional change
intended.

Change-Id: I13d2ad62a9315b233d7a5fd3ffcaac3dd01b055c
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2023-06-05 13:22:21 -04:00
Demi Marie Obenour
48ffc74c97 refactor(el3-spmc): move function call out of loop
Hopefully this will be a tiny speedup.  No functional change intended.

Change-Id: Ia052c7f9b24d5ece6209a6fa2903b1271215ece7
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2023-06-05 13:22:21 -04:00
Demi Marie Obenour
91567c3843 refactor(el3-spmc): avoid using EINVAL
Use proper FF-A return code instead.

Change-Id: Ie749ff06339bc137d3baa96f06f0a6160b35abed
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2023-06-05 13:22:21 -04:00
Demi Marie Obenour
9526282a7d refactor(el3-spmc): crash instead of reading OOB
If it is called on an invalid mtd, out-of-bounds memory reads are
likely.  Checks elsewhere in the code ensure that the mtd has been
validated before calling this function.

Change-Id: If598680a5b79e1786a6e0a213779ec80cbf37494
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2023-06-05 13:22:21 -04:00
Demi Marie Obenour
27c0242508 fix(el3-spmc): avoid descriptor size calc overflow
This ensures that descriptor size calculation does not overflow and
removes a bounds check that does not actually work.

Change-Id: If8da2bb1b312941b7f9d0debf3149b984fc3809a
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2023-06-05 13:22:21 -04:00
Demi Marie Obenour
2d4da8e265 fix(el3-spmc): prevent total_page_count overflow
size_t is not guaranteed to be 64 bits, although it happens to be 64
bits on all systems that el3-spmc supports.

Change-Id: Ieae11722a15448641de50233597ac35869eab574
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2023-06-05 13:22:21 -04:00
Demi Marie Obenour
43318e4a4d fix(el3-spmc): use uint64_t for 64-bit type
Using uint64_t is cleaner, even though size_t is 64 bits on all
platforms el3-spmc supports.

Change-Id: I457deb0b7f3df0749cb5368cceda1bb530d039de
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2023-06-05 13:22:21 -04:00
laurenw-arm
b695b2f16e refactor(fvp): nv ctr addr static helper function
Adding a static helper function plat_get_nv_ctr_addr() to be used by
both plat_set_nv_ctr() and plat_get_nv_ctr() to return the
non-volatile counter address stored in the platform.

Change-Id: I5124c19e4537bb369724aa0160cc55a3cb1ab7eb
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2023-06-05 11:21:51 -05:00
Manish Pandey
a0f3b552cf Merge "chore: rename Makalu to Cortex-A715" into integration 2023-06-05 16:21:47 +02:00
Soby Mathew
9027be6fae Merge "feat(xlat): detect 4KB and 16KB page support when FEAT_LPA2 is present" into integration 2023-06-05 13:04:34 +02:00
Manish Pandey
ba56ea6fed Merge "fix(fiptool): move juno plat_fiptool.mk" into integration 2023-06-05 12:42:03 +02:00
Marcin Juszkiewicz
1e67b1b17a feat(qemu-sbsa): handle GIC base
QEMU provides GIC information in DeviceTree (on platform version 0.1+).
Read it and provide to next firmware level via SMC.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I383919bd172acc8873292a0c5e4469651dc96fb9
2023-06-05 12:24:44 +02:00
Marcin Juszkiewicz
c681d02c6c feat(qemu-sbsa): handle platform version
QEMU provides platform version information via DT. We want to use it
in firmware to handle differences between platform versions.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I8def66dac9dd5d7ab0e459baa40e27a11b65f0ba
2023-06-05 11:24:35 +01:00
Javier Almansa Sobrino
bff074dd94 feat(xlat): detect 4KB and 16KB page support when FEAT_LPA2 is present
At the moment, TF-A does not need to access VAs or PAs larger than
48 bits, so this patch just enables proper detection of support
for 4KB and 16KB granularity with 52 bits address support.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iccebbd5acc21f09dbb234ef21a802300e290ec18
2023-06-05 11:05:02 +01:00
Sandrine Bailleux
7f126ccff6 Merge changes from topic "cot_cca_nvctr" into integration
* changes:
  feat(fvp): mock support for CCA NV ctr
  feat(auth): add CCA NV ctr to CCA CoT
  feat(build): pass CCA NV ctr option to cert_create
  feat(cert-create): add new option for CCA NV ctr
2023-06-05 08:13:33 +02:00
Sandrine Bailleux
463655cc81 Merge "fix(measured-boot): don't strip last non-0 char" into integration 2023-06-02 10:02:47 +02:00
Sandrine Bailleux
9b5c0fcdba Merge changes from topic "hm/memmap-feat" into integration
* changes:
  build(bl32): add symbols for memory layout
  build(bl31): add symbols for memory layout
  build(bl2): add symbols for memory layout
  build(bl1): add symbols for memory layout
  refactor: improve readability of symbol table
2023-06-01 14:36:46 +02:00
Sandrine Bailleux
ff31094a0d Merge changes from topic "sb/maintainters-process" into integration
* changes:
  docs: clarify maintainers election process
  docs: consolidate code review process documentation
2023-06-01 13:42:16 +02:00
Sandrine Bailleux
0df5cf1893 docs: clarify maintainers election process
Add a new page in TF-A documentation for clarifying the process to
elect a new maintainer. This builds on top of the Trusted Firmware
process [1], with the following TF-A specific details:

 - Must have contributed to the project for at least a couple of years.
 - Must dedicate at least 2 hours a week for maintainer duties.
 - Details about the election process. In particular, setting a
   one-calendar-week deadline for other maintainers to raise
   objections.

[1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Ibef08bbbd4d18cd7aea13e01ba570972a7ee808d
2023-06-01 13:41:09 +02:00
Sandrine Bailleux
ca4febac0c docs: consolidate code review process documentation
From the page listing the maintainers and code owners [1], add a link
to the code review guidelines page [2], which in turn has a link to
the tf.org code review process [3].

Before that patch, both pages [1] and [2] had a link to
[3]. Hopefully, this change will guide the reader better so they don't
miss out on any information.

Additionally, move some of the information from the top of page [1]
into page [2] and add extra details about the code review process used
in TF-A and how that get translated in Gerrit.

[1] https://trustedfirmware-a.readthedocs.io/en/latest/about/maintainers.html
[2] https://trustedfirmware-a.readthedocs.io/en/latest/process/code-review-guidelines.html
[3] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I56562a72443f03fff16077dadc411ef4ee78666d
2023-06-01 13:41:09 +02:00
Lauren Wehrmeister
0cfa06b22b Merge changes from topic "bk/errata_refactor" into integration
* changes:
  feat(cpus): wrappers to propagate AArch32 errata info
  feat(cpus): add a way to automatically report errata
  feat(cpus): add a concise way to implement AArch64 errata
  refactor(cpus): convert print_errata_status to C
  refactor(cpus): rename errata_report.h to errata.h
  refactor(cpus): move cpu_ops field defines to a header
2023-05-31 23:06:53 +02:00