mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-27 07:15:20 +00:00
Merge changes I21d65a88,I949cfce9,If4249f22,Id0451bd1,I9e930070, ... into integration
* changes: feat(mediatek): add APU watchdog timeout control feat(mt8188): add emi mpu protection for APU secure memory feat(mt8188): add devapc setting of apusys rcx feat(mt8188): add backup/restore function when power on/off feat(mediatek): add APU bootup control smc call feat(mt8188): enable apusys mailbox mpu protect feat(mt8188): enable apusys domain remap feat(mt8188): add apusys ao devapc setting feat(mt8188): increase TZRAM_SIZE from 192KB to 256KB
This commit is contained in:
Olivier Deprez
TrustedFirmware Code Review
commit
4c8e1f9a35
22 changed files with 1355 additions and 9 deletions
plat/mediatek
drivers
apusys
apusys.capusys.h
apusys_rv/2.0
devapc
mt8188
apusys_devapc.capusys_devapc.hapusys_devapc_def.hapusys_power.capusys_power.hapusys_security_ctrl_plat.capusys_security_ctrl_plat.hrules.mk
rules.mkemi_mpu
mt8188/include
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@ -9,7 +9,10 @@
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/* Vendor header */
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#include "apusys.h"
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#include "apusys_devapc.h"
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#include "apusys_power.h"
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#include "apusys_rv.h"
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#include "apusys_security_ctrl_plat.h"
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#include <lib/mtk_init/mtk_init.h>
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#include <mtk_sip_svc.h>
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@ -32,6 +35,39 @@ static u_register_t apusys_kernel_handler(u_register_t x1,
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case MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF:
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ret = apusys_kernel_apusys_pwr_top_off();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_REVISER:
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ret = apusys_kernel_apusys_rv_setup_reviser();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_RESET_MP:
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ret = apusys_kernel_apusys_rv_reset_mp();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_BOOT:
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ret = apusys_kernel_apusys_rv_setup_boot();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_START_MP:
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ret = apusys_kernel_apusys_rv_start_mp();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_STOP_MP:
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ret = apusys_kernel_apusys_rv_stop_mp();
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break;
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case MTK_APUSYS_KERNEL_OP_DEVAPC_INIT_RCX:
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ret = apusys_devapc_rcx_init();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_SEC_MEM:
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ret = apusys_kernel_apusys_rv_setup_sec_mem();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_DISABLE_WDT_ISR:
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ret = apusys_kernel_apusys_rv_disable_wdt_isr();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_CLEAR_WDT_ISR:
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ret = apusys_kernel_apusys_rv_clear_wdt_isr();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_GATING:
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ret = apusys_kernel_apusys_rv_cg_gating();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_UNGATING:
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ret = apusys_kernel_apusys_rv_cg_ungating();
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break;
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default:
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ERROR(MODULE_TAG "%s unknown request_ops = %x\n", MODULE_TAG, request_ops);
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break;
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@ -43,7 +79,17 @@ DECLARE_SMC_HANDLER(MTK_SIP_APUSYS_CONTROL, apusys_kernel_handler);
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int apusys_init(void)
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{
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apusys_power_init();
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if (apusys_power_init() != 0) {
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return -1;
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}
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if (apusys_devapc_ao_init() != 0) {
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return -1;
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}
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apusys_security_ctrl_init();
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apusys_rv_mbox_mpu_init();
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return 0;
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}
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MTK_PLAT_SETUP_1_INIT(apusys_init);
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@ -10,8 +10,19 @@
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#define MODULE_TAG "[APUSYS]"
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enum MTK_APUSYS_KERNEL_OP {
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MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON, /* 0 */
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MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF,/* 1 */
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MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON, /* 0 */
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MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF, /* 1 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_REVISER, /* 2 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_RESET_MP, /* 3 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_BOOT, /* 4 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_START_MP, /* 5 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_STOP_MP, /* 6 */
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MTK_APUSYS_KERNEL_OP_DEVAPC_INIT_RCX, /* 7 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_SEC_MEM, /* 8 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_DISABLE_WDT_ISR, /* 9 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_CLEAR_WDT_ISR, /* 10 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_GATING, /* 11 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_UNGATING, /* 12 */
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MTK_APUSYS_KERNEL_OP_NUM,
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};
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257
plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
Normal file
257
plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
Normal file
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@ -0,0 +1,257 @@
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/*
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* Copyright (c) 2023, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* TF-A system header */
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/spinlock.h>
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/* Vendor header */
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#include "apusys.h"
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#include "apusys_rv.h"
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#include "apusys_rv_mbox_mpu.h"
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#include "emi_mpu.h"
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static spinlock_t apusys_rv_lock;
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void apusys_rv_mbox_mpu_init(void)
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{
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int i;
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for (i = 0; i < APU_MBOX_NUM; i++) {
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mmio_write_32(APU_MBOX_FUNC_CFG(i),
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(MBOX_CTRL_LOCK |
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(mbox_mpu_setting_tab[i].no_mpu << MBOX_NO_MPU_SHIFT)));
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mmio_write_32(APU_MBOX_DOMAIN_CFG(i),
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(MBOX_CTRL_LOCK |
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(mbox_mpu_setting_tab[i].rx_ns << MBOX_RX_NS_SHIFT) |
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(mbox_mpu_setting_tab[i].rx_domain << MBOX_RX_DOMAIN_SHIFT) |
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(mbox_mpu_setting_tab[i].tx_ns << MBOX_TX_NS_SHIFT) |
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(mbox_mpu_setting_tab[i].tx_domain << MBOX_TX_DOMAIN_SHIFT)));
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}
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}
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int apusys_kernel_apusys_rv_setup_reviser(void)
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{
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static bool apusys_rv_setup_reviser_called;
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spin_lock(&apusys_rv_lock);
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if (apusys_rv_setup_reviser_called) {
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WARN(MODULE_TAG "%s: already initialized\n", __func__);
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spin_unlock(&apusys_rv_lock);
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return -1;
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}
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apusys_rv_setup_reviser_called = true;
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mmio_write_32(USERFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
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mmio_write_32(SECUREFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
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mmio_write_32(UP_IOMMU_CTRL, MMU_CTRL_LOCK | MMU_CTRL | MMU_EN);
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mmio_write_32(UP_NORMAL_DOMAIN_NS,
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(UP_NORMAL_DOMAIN << UP_DOMAIN_SHIFT) | (UP_NORMAL_NS << UP_NS_SHIFT));
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mmio_write_32(UP_PRI_DOMAIN_NS,
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(UP_PRI_DOMAIN << UP_DOMAIN_SHIFT) | (UP_PRI_NS << UP_NS_SHIFT));
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mmio_write_32(UP_CORE0_VABASE0,
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VLD | PARTIAL_ENABLE | (THREAD_NUM_PRI << THREAD_NUM_SHIFT));
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mmio_write_32(UP_CORE0_MVABASE0, VASIZE_1MB | (APU_SEC_FW_IOVA >> MVA_34BIT_SHIFT));
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mmio_write_32(UP_CORE0_VABASE1,
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VLD | PARTIAL_ENABLE | (THREAD_NUM_NORMAL << THREAD_NUM_SHIFT));
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mmio_write_32(UP_CORE0_MVABASE1, VASIZE_1MB | (APU_SEC_FW_IOVA >> MVA_34BIT_SHIFT));
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spin_unlock(&apusys_rv_lock);
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return 0;
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}
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int apusys_kernel_apusys_rv_reset_mp(void)
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{
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static bool apusys_rv_reset_mp_called;
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spin_lock(&apusys_rv_lock);
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if (apusys_rv_reset_mp_called) {
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WARN(MODULE_TAG "%s: already initialized\n", __func__);
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spin_unlock(&apusys_rv_lock);
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return -1;
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}
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apusys_rv_reset_mp_called = true;
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mmio_write_32(MD32_SYS_CTRL, MD32_SYS_CTRL_RST);
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udelay(RESET_DEALY_US);
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mmio_write_32(MD32_SYS_CTRL, MD32_G2B_CG_EN | MD32_DBG_EN | MD32_DM_AWUSER_IOMMU_EN |
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MD32_DM_ARUSER_IOMMU_EN | MD32_PM_AWUSER_IOMMU_EN | MD32_PM_ARUSER_IOMMU_EN |
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MD32_SOFT_RSTN);
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mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN);
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mmio_write_32(UP_WAKE_HOST_MASK0, WDT_IRQ_EN);
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mmio_write_32(UP_WAKE_HOST_MASK1, MBOX0_IRQ_EN | MBOX1_IRQ_EN | MBOX2_IRQ_EN);
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spin_unlock(&apusys_rv_lock);
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return 0;
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}
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int apusys_kernel_apusys_rv_setup_boot(void)
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{
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static bool apusys_rv_setup_boot_called;
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spin_lock(&apusys_rv_lock);
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if (apusys_rv_setup_boot_called) {
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WARN(MODULE_TAG "%s: already initialized\n", __func__);
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spin_unlock(&apusys_rv_lock);
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return -1;
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}
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apusys_rv_setup_boot_called = true;
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mmio_write_32(MD32_BOOT_CTRL, APU_SEC_FW_IOVA);
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mmio_write_32(MD32_PRE_DEFINE, (PREDEFINE_CACHE_TCM << PREDEF_1G_OFS) |
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(PREDEFINE_CACHE << PREDEF_2G_OFS) | (PREDEFINE_CACHE << PREDEF_3G_OFS) |
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(PREDEFINE_CACHE << PREDEF_4G_OFS));
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spin_unlock(&apusys_rv_lock);
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return 0;
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}
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int apusys_kernel_apusys_rv_start_mp(void)
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{
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static bool apusys_rv_start_mp_called;
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spin_lock(&apusys_rv_lock);
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if (apusys_rv_start_mp_called) {
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WARN(MODULE_TAG "%s: already initialized\n", __func__);
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spin_unlock(&apusys_rv_lock);
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return -1;
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}
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apusys_rv_start_mp_called = true;
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mmio_write_32(MD32_RUNSTALL, MD32_RUN);
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spin_unlock(&apusys_rv_lock);
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|
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return 0;
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}
|
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|
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static bool watch_dog_is_timeout(void)
|
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{
|
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if (mmio_read_32(WDT_INT) != WDT_INT_W1C) {
|
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ERROR(MODULE_TAG "%s: WDT does not timeout\n", __func__);
|
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return false;
|
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}
|
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return true;
|
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}
|
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|
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int apusys_kernel_apusys_rv_stop_mp(void)
|
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{
|
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static bool apusys_rv_stop_mp_called;
|
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|
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spin_lock(&apusys_rv_lock);
|
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|
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if (apusys_rv_stop_mp_called) {
|
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WARN(MODULE_TAG "%s: already initialized\n", __func__);
|
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spin_unlock(&apusys_rv_lock);
|
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return -1;
|
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}
|
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|
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if (watch_dog_is_timeout() == false) {
|
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spin_unlock(&apusys_rv_lock);
|
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return -1;
|
||||
}
|
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|
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apusys_rv_stop_mp_called = true;
|
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|
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mmio_write_32(MD32_RUNSTALL, MD32_STALL);
|
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|
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spin_unlock(&apusys_rv_lock);
|
||||
|
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return 0;
|
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}
|
||||
|
||||
int apusys_kernel_apusys_rv_setup_sec_mem(void)
|
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{
|
||||
static bool apusys_rv_setup_sec_mem_called;
|
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int ret;
|
||||
|
||||
spin_lock(&apusys_rv_lock);
|
||||
|
||||
if (apusys_rv_setup_sec_mem_called) {
|
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WARN(MODULE_TAG "%s: already initialized\n", __func__);
|
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spin_unlock(&apusys_rv_lock);
|
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return -1;
|
||||
}
|
||||
|
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apusys_rv_setup_sec_mem_called = true;
|
||||
|
||||
ret = set_apu_emi_mpu_region();
|
||||
if (ret != 0) {
|
||||
ERROR(MODULE_TAG "%s: set emimpu protection failed\n", __func__);
|
||||
}
|
||||
|
||||
spin_unlock(&apusys_rv_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int apusys_kernel_apusys_rv_disable_wdt_isr(void)
|
||||
{
|
||||
spin_lock(&apusys_rv_lock);
|
||||
mmio_clrbits_32(WDT_CTRL0, WDT_EN);
|
||||
spin_unlock(&apusys_rv_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int apusys_kernel_apusys_rv_clear_wdt_isr(void)
|
||||
{
|
||||
spin_lock(&apusys_rv_lock);
|
||||
mmio_clrbits_32(UP_INT_EN2, DBG_APB_EN);
|
||||
mmio_write_32(WDT_INT, WDT_INT_W1C);
|
||||
spin_unlock(&apusys_rv_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int apusys_kernel_apusys_rv_cg_gating(void)
|
||||
{
|
||||
spin_lock(&apusys_rv_lock);
|
||||
|
||||
if (watch_dog_is_timeout() == false) {
|
||||
spin_unlock(&apusys_rv_lock);
|
||||
return -1;
|
||||
}
|
||||
|
||||
mmio_write_32(MD32_CLK_CTRL, MD32_CLK_DIS);
|
||||
spin_unlock(&apusys_rv_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int apusys_kernel_apusys_rv_cg_ungating(void)
|
||||
{
|
||||
spin_lock(&apusys_rv_lock);
|
||||
|
||||
if (watch_dog_is_timeout() == false) {
|
||||
spin_unlock(&apusys_rv_lock);
|
||||
return -1;
|
||||
}
|
||||
|
||||
mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN);
|
||||
spin_unlock(&apusys_rv_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
120
plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h
Normal file
120
plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef APUSYS_RV_H
|
||||
#define APUSYS_RV_H
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#define APU_SEC_FW_IOVA (0x200000UL)
|
||||
|
||||
/* APU_SCTRL_REVISER */
|
||||
#define UP_NORMAL_DOMAIN_NS (APU_REVISER + 0x0000)
|
||||
#define UP_PRI_DOMAIN_NS (APU_REVISER + 0x0004)
|
||||
#define UP_IOMMU_CTRL (APU_REVISER + 0x0008)
|
||||
#define UP_CORE0_VABASE0 (APU_REVISER + 0x000c)
|
||||
#define UP_CORE0_MVABASE0 (APU_REVISER + 0x0010)
|
||||
#define UP_CORE0_VABASE1 (APU_REVISER + 0x0014)
|
||||
#define UP_CORE0_MVABASE1 (APU_REVISER + 0x0018)
|
||||
#define UP_CORE0_VABASE2 (APU_REVISER + 0x001c)
|
||||
#define UP_CORE0_MVABASE2 (APU_REVISER + 0x0020)
|
||||
#define UP_CORE0_VABASE3 (APU_REVISER + 0x0024)
|
||||
#define UP_CORE0_MVABASE3 (APU_REVISER + 0x0028)
|
||||
#define USERFW_CTXT (APU_REVISER + 0x1000)
|
||||
#define SECUREFW_CTXT (APU_REVISER + 0x1004)
|
||||
#define UP_NORMAL_DOMAIN (7)
|
||||
#define UP_NORMAL_NS (1)
|
||||
#define UP_PRI_DOMAIN (5)
|
||||
#define UP_PRI_NS (1)
|
||||
#define UP_DOMAIN_SHIFT (0)
|
||||
#define UP_NS_SHIFT (4)
|
||||
#define MMU_EN BIT(0)
|
||||
#define MMU_CTRL BIT(1)
|
||||
#define MMU_CTRL_LOCK BIT(2)
|
||||
#define VLD BIT(0)
|
||||
#define PARTIAL_ENABLE BIT(1)
|
||||
#define THREAD_NUM_PRI (1)
|
||||
#define THREAD_NUM_NORMAL (0)
|
||||
#define THREAD_NUM_SHIFT (2)
|
||||
#define VASIZE_1MB BIT(0)
|
||||
#define CFG_4GB_SEL_EN BIT(2)
|
||||
#define CFG_4GB_SEL (0)
|
||||
#define MVA_34BIT_SHIFT (2)
|
||||
|
||||
/* APU_MD32_SYSCTRL */
|
||||
#define MD32_SYS_CTRL (APU_MD32_SYSCTRL + 0x0000)
|
||||
#define UP_INT_EN2 (APU_MD32_SYSCTRL + 0x000c)
|
||||
#define MD32_CLK_CTRL (APU_MD32_SYSCTRL + 0x00b8)
|
||||
#define UP_WAKE_HOST_MASK0 (APU_MD32_SYSCTRL + 0x00bc)
|
||||
#define UP_WAKE_HOST_MASK1 (APU_MD32_SYSCTRL + 0x00c0)
|
||||
#define MD32_SYS_CTRL_RST (0)
|
||||
#define MD32_G2B_CG_EN BIT(11)
|
||||
#define MD32_DBG_EN BIT(10)
|
||||
#define MD32_DM_AWUSER_IOMMU_EN BIT(9)
|
||||
#define MD32_DM_ARUSER_IOMMU_EN BIT(7)
|
||||
#define MD32_PM_AWUSER_IOMMU_EN BIT(5)
|
||||
#define MD32_PM_ARUSER_IOMMU_EN BIT(3)
|
||||
#define MD32_SOFT_RSTN BIT(0)
|
||||
#define MD32_CLK_EN (1)
|
||||
#define MD32_CLK_DIS (0)
|
||||
#define WDT_IRQ_EN BIT(0)
|
||||
#define MBOX0_IRQ_EN BIT(21)
|
||||
#define MBOX1_IRQ_EN BIT(22)
|
||||
#define MBOX2_IRQ_EN BIT(23)
|
||||
#define RESET_DEALY_US (10)
|
||||
#define DBG_APB_EN BIT(31)
|
||||
|
||||
/* APU_AO_CTRL */
|
||||
#define MD32_PRE_DEFINE (APU_AO_CTRL + 0x0000)
|
||||
#define MD32_BOOT_CTRL (APU_AO_CTRL + 0x0004)
|
||||
#define MD32_RUNSTALL (APU_AO_CTRL + 0x0008)
|
||||
#define PREDEFINE_NON_CACHE (0)
|
||||
#define PREDEFINE_TCM (1)
|
||||
#define PREDEFINE_CACHE (2)
|
||||
#define PREDEFINE_CACHE_TCM (3)
|
||||
#define PREDEF_1G_OFS (0)
|
||||
#define PREDEF_2G_OFS (2)
|
||||
#define PREDEF_3G_OFS (4)
|
||||
#define PREDEF_4G_OFS (6)
|
||||
#define MD32_RUN (0)
|
||||
#define MD32_STALL (1)
|
||||
|
||||
/* APU_MD32_WDT */
|
||||
#define WDT_INT (APU_MD32_WDT + 0x0)
|
||||
#define WDT_CTRL0 (APU_MD32_WDT + 0x4)
|
||||
#define WDT_INT_W1C (1)
|
||||
#define WDT_EN BIT(31)
|
||||
|
||||
/* APU MBOX */
|
||||
#define MBOX_FUNC_CFG (0xb0)
|
||||
#define MBOX_DOMAIN_CFG (0xe0)
|
||||
#define MBOX_CTRL_LOCK BIT(0)
|
||||
#define MBOX_NO_MPU_SHIFT (16)
|
||||
#define MBOX_RX_NS_SHIFT (16)
|
||||
#define MBOX_RX_DOMAIN_SHIFT (17)
|
||||
#define MBOX_TX_NS_SHIFT (24)
|
||||
#define MBOX_TX_DOMAIN_SHIFT (25)
|
||||
#define MBOX_SIZE (0x100)
|
||||
#define MBOX_NUM (8)
|
||||
|
||||
#define APU_MBOX(i) (((i) < MBOX_NUM) ? (APU_MBOX0 + MBOX_SIZE * (i)) : \
|
||||
(APU_MBOX1 + MBOX_SIZE * ((i) - MBOX_NUM)))
|
||||
#define APU_MBOX_FUNC_CFG(i) (APU_MBOX(i) + MBOX_FUNC_CFG)
|
||||
#define APU_MBOX_DOMAIN_CFG(i) (APU_MBOX(i) + MBOX_DOMAIN_CFG)
|
||||
|
||||
void apusys_rv_mbox_mpu_init(void);
|
||||
int apusys_kernel_apusys_rv_setup_reviser(void);
|
||||
int apusys_kernel_apusys_rv_reset_mp(void);
|
||||
int apusys_kernel_apusys_rv_setup_boot(void);
|
||||
int apusys_kernel_apusys_rv_start_mp(void);
|
||||
int apusys_kernel_apusys_rv_stop_mp(void);
|
||||
int apusys_kernel_apusys_rv_setup_sec_mem(void);
|
||||
int apusys_kernel_apusys_rv_disable_wdt_isr(void);
|
||||
int apusys_kernel_apusys_rv_clear_wdt_isr(void);
|
||||
int apusys_kernel_apusys_rv_cg_gating(void);
|
||||
int apusys_kernel_apusys_rv_cg_ungating(void);
|
||||
|
||||
#endif /* APUSYS_RV_H */
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef APUSYS_RV_MBOX_MPU_H
|
||||
#define APUSYS_RV_MBOX_MPU_H
|
||||
|
||||
#define MPU_EN (0)
|
||||
#define MPU_DIS (1)
|
||||
#define MBOX0_TX_DOMAIN (0)
|
||||
#define MBOX0_TX_NS (1)
|
||||
#define MBOX4_RX_DOMAIN (0)
|
||||
#define MBOX4_RX_NS (0)
|
||||
#define MBOX5_TX_DOMAIN (3)
|
||||
#define MBOX5_TX_NS (0)
|
||||
#define MBOXN_RX_DOMAIN (5)
|
||||
#define MBOXN_RX_NS (1)
|
||||
#define MBOXN_TX_DOMAIN (0)
|
||||
#define MBOXN_TX_NS (0)
|
||||
|
||||
struct mbox_mpu_setting {
|
||||
uint32_t no_mpu;
|
||||
uint32_t rx_ns;
|
||||
uint32_t rx_domain;
|
||||
uint32_t tx_ns;
|
||||
uint32_t tx_domain;
|
||||
};
|
||||
|
||||
static const struct mbox_mpu_setting mbox_mpu_setting_tab[] = {
|
||||
{ MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX0_TX_NS, MBOX0_TX_DOMAIN },
|
||||
{ MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
|
||||
{ MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
|
||||
{ MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
|
||||
{ MPU_DIS, MBOX4_RX_NS, MBOX4_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
|
||||
{ MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX5_TX_NS, MBOX5_TX_DOMAIN },
|
||||
{ MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
|
||||
{ MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
|
||||
{ MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
|
||||
{ MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
|
||||
};
|
||||
|
||||
#define APU_MBOX_NUM ARRAY_SIZE(mbox_mpu_setting_tab)
|
||||
|
||||
#endif /* APUSYS_RV_MBOX_MPU_H */
|
||||
15
plat/mediatek/drivers/apusys/apusys_rv/2.0/rules.mk
Normal file
15
plat/mediatek/drivers/apusys/apusys_rv/2.0/rules.mk
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
#
|
||||
# Copyright (c) 2023, MediaTek Inc. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
LOCAL_DIR := $(call GET_LOCAL_DIR)
|
||||
|
||||
MODULE := apusys_rv_${MTK_SOC}
|
||||
|
||||
PLAT_INCLUDES += -I${MTK_PLAT}/drivers/apusys/${MTK_SOC}
|
||||
|
||||
LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_rv.c
|
||||
|
||||
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
|
||||
68
plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.c
Normal file
68
plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.c
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/* TF-A system header */
|
||||
#include <common/debug.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Vendor header */
|
||||
#include "apusys.h"
|
||||
#include "apusys_dapc_v1.h"
|
||||
#include <platform_def.h>
|
||||
|
||||
enum apusys_apc_err_status set_apusys_dapc_v1(const struct apc_dom_16 *dapc,
|
||||
uint32_t size, dapc_cfg_func cfg)
|
||||
{
|
||||
enum apusys_apc_err_status ret = APUSYS_APC_OK;
|
||||
uint32_t i;
|
||||
|
||||
if ((dapc == NULL) || (cfg == NULL)) {
|
||||
return APUSYS_APC_ERR_GENERIC;
|
||||
}
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
ret += cfg(i, DOMAIN_0, dapc[i].d0_permission);
|
||||
ret += cfg(i, DOMAIN_1, dapc[i].d1_permission);
|
||||
ret += cfg(i, DOMAIN_2, dapc[i].d2_permission);
|
||||
ret += cfg(i, DOMAIN_3, dapc[i].d3_permission);
|
||||
ret += cfg(i, DOMAIN_4, dapc[i].d4_permission);
|
||||
ret += cfg(i, DOMAIN_5, dapc[i].d5_permission);
|
||||
ret += cfg(i, DOMAIN_6, dapc[i].d6_permission);
|
||||
ret += cfg(i, DOMAIN_7, dapc[i].d7_permission);
|
||||
ret += cfg(i, DOMAIN_8, dapc[i].d8_permission);
|
||||
ret += cfg(i, DOMAIN_9, dapc[i].d9_permission);
|
||||
ret += cfg(i, DOMAIN_10, dapc[i].d10_permission);
|
||||
ret += cfg(i, DOMAIN_11, dapc[i].d11_permission);
|
||||
ret += cfg(i, DOMAIN_12, dapc[i].d12_permission);
|
||||
ret += cfg(i, DOMAIN_13, dapc[i].d13_permission);
|
||||
ret += cfg(i, DOMAIN_14, dapc[i].d14_permission);
|
||||
ret += cfg(i, DOMAIN_15, dapc[i].d15_permission);
|
||||
}
|
||||
|
||||
if (ret != APUSYS_APC_OK) {
|
||||
ret = APUSYS_APC_ERR_GENERIC;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void dump_apusys_dapc_v1(const char *name, uintptr_t base, uint32_t reg_num, uint32_t dom_num)
|
||||
{
|
||||
uint32_t d, i;
|
||||
|
||||
if ((name == NULL) || (base == 0)) {
|
||||
return;
|
||||
}
|
||||
|
||||
for (d = 0; d < dom_num; d++) {
|
||||
for (i = 0; i <= reg_num; i++) {
|
||||
INFO(MODULE_TAG "[%s] D%d_APC_%d: 0x%x\n", name, d, i,
|
||||
mmio_read_32(base + d * DEVAPC_DOM_SIZE + i * DEVAPC_REG_SIZE));
|
||||
}
|
||||
}
|
||||
|
||||
INFO(MODULE_TAG "[%s] APC_CON: 0x%x\n", name, mmio_read_32(APUSYS_DAPC_CON(base)));
|
||||
}
|
||||
173
plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.h
Normal file
173
plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.h
Normal file
|
|
@ -0,0 +1,173 @@
|
|||
/*
|
||||
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef APUSYS_DAPC_V1_H
|
||||
#define APUSYS_DAPC_V1_H
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
/******************************************************************************
|
||||
* STRUCTURE DEFINITION
|
||||
******************************************************************************/
|
||||
enum apusys_apc_err_status {
|
||||
APUSYS_APC_OK = 0x0,
|
||||
APUSYS_APC_ERR_GENERIC = 0x1,
|
||||
};
|
||||
|
||||
enum apusys_apc_perm_type {
|
||||
NO_PROTECTION = 0,
|
||||
SEC_RW_ONLY = 1,
|
||||
SEC_RW_NS_R = 2,
|
||||
FORBIDDEN = 3,
|
||||
PERM_NUM = 4,
|
||||
};
|
||||
|
||||
enum apusys_apc_domain_id {
|
||||
DOMAIN_0 = 0,
|
||||
DOMAIN_1 = 1,
|
||||
DOMAIN_2 = 2,
|
||||
DOMAIN_3 = 3,
|
||||
DOMAIN_4 = 4,
|
||||
DOMAIN_5 = 5,
|
||||
DOMAIN_6 = 6,
|
||||
DOMAIN_7 = 7,
|
||||
DOMAIN_8 = 8,
|
||||
DOMAIN_9 = 9,
|
||||
DOMAIN_10 = 10,
|
||||
DOMAIN_11 = 11,
|
||||
DOMAIN_12 = 12,
|
||||
DOMAIN_13 = 13,
|
||||
DOMAIN_14 = 14,
|
||||
DOMAIN_15 = 15,
|
||||
};
|
||||
|
||||
struct apc_dom_16 {
|
||||
unsigned char d0_permission;
|
||||
unsigned char d1_permission;
|
||||
unsigned char d2_permission;
|
||||
unsigned char d3_permission;
|
||||
unsigned char d4_permission;
|
||||
unsigned char d5_permission;
|
||||
unsigned char d6_permission;
|
||||
unsigned char d7_permission;
|
||||
unsigned char d8_permission;
|
||||
unsigned char d9_permission;
|
||||
unsigned char d10_permission;
|
||||
unsigned char d11_permission;
|
||||
unsigned char d12_permission;
|
||||
unsigned char d13_permission;
|
||||
unsigned char d14_permission;
|
||||
unsigned char d15_permission;
|
||||
};
|
||||
|
||||
#define APUSYS_APC_AO_ATTR(DEV_NAME, \
|
||||
PERM_ATTR0, PERM_ATTR1, PERM_ATTR2, PERM_ATTR3, \
|
||||
PERM_ATTR4, PERM_ATTR5, PERM_ATTR6, PERM_ATTR7, \
|
||||
PERM_ATTR8, PERM_ATTR9, PERM_ATTR10, PERM_ATTR11, \
|
||||
PERM_ATTR12, PERM_ATTR13, PERM_ATTR14, PERM_ATTR15) \
|
||||
{(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
|
||||
(unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
|
||||
(unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
|
||||
(unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \
|
||||
(unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \
|
||||
(unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \
|
||||
(unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \
|
||||
(unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15}
|
||||
|
||||
typedef enum apusys_apc_err_status (*dapc_cfg_func)(uint32_t slave,
|
||||
enum apusys_apc_domain_id domain_id,
|
||||
enum apusys_apc_perm_type perm);
|
||||
|
||||
/* Register */
|
||||
#define DEVAPC_DOM_SIZE (0x40)
|
||||
#define DEVAPC_REG_SIZE (4)
|
||||
|
||||
/* APUSYS APC offsets */
|
||||
#define APUSYS_DAPC_CON_VIO_MASK (0x80000000)
|
||||
#define APUSYS_DAPC_CON(base) ((base) + 0x00f00)
|
||||
|
||||
/******************************************************************************
|
||||
* DAPC Common Function
|
||||
******************************************************************************/
|
||||
#define SET_APUSYS_DAPC_V1(dapc, cfg) \
|
||||
set_apusys_dapc_v1(dapc, ARRAY_SIZE(dapc), cfg)
|
||||
|
||||
#define DUMP_APUSYS_DAPC_V1(apc) \
|
||||
dump_apusys_dapc_v1(#apc, apc##_BASE, \
|
||||
(apc##_SLAVE_NUM / apc##_SLAVE_NUM_IN_1_DOM), apc##_DOM_NUM)
|
||||
|
||||
enum apusys_apc_err_status set_apusys_dapc_v1(const struct apc_dom_16 *dapc,
|
||||
uint32_t size, dapc_cfg_func cfg);
|
||||
|
||||
void dump_apusys_dapc_v1(const char *name, uintptr_t base, uint32_t reg_num, uint32_t dom_num);
|
||||
|
||||
/******************************************************************************
|
||||
* DAPC Permission Policy
|
||||
******************************************************************************/
|
||||
#define SLAVE_FORBID_EXCEPT_D0_SEC_RW(domain) \
|
||||
APUSYS_APC_AO_ATTR(domain, \
|
||||
SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
|
||||
|
||||
#define SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT(domain) \
|
||||
APUSYS_APC_AO_ATTR(domain, \
|
||||
SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
|
||||
|
||||
#define SLAVE_FORBID_EXCEPT_D5_NO_PROTECT(domain) \
|
||||
APUSYS_APC_AO_ATTR(domain, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
|
||||
|
||||
#define SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT(domain) \
|
||||
APUSYS_APC_AO_ATTR(domain, \
|
||||
SEC_RW_NS_R, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
|
||||
|
||||
#define SLAVE_FORBID_EXCEPT_D7_NO_PROTECT(domain) \
|
||||
APUSYS_APC_AO_ATTR(domain, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
|
||||
|
||||
#define SLAVE_FORBID_EXCEPT_D5_D7_NO_PROTECT(domain) \
|
||||
APUSYS_APC_AO_ATTR(domain, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, NO_PROTECTION, FORBIDDEN, NO_PROTECTION, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
|
||||
|
||||
#define SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT(domain) \
|
||||
APUSYS_APC_AO_ATTR(domain, \
|
||||
NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
|
||||
|
||||
#define SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW(domain) \
|
||||
APUSYS_APC_AO_ATTR(domain, \
|
||||
NO_PROTECTION, FORBIDDEN, FORBIDDEN, SEC_RW_ONLY, \
|
||||
FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
|
||||
|
||||
#define SLAVE_FORBID_EXCEPT_D0_D3_SEC_RW_D5_NO_PROTECT(domain) \
|
||||
APUSYS_APC_AO_ATTR(domain, \
|
||||
SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, SEC_RW_ONLY, \
|
||||
FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
|
||||
|
||||
#endif /* APUSYS_DAPC_V1_H */
|
||||
13
plat/mediatek/drivers/apusys/devapc/rules.mk
Normal file
13
plat/mediatek/drivers/apusys/devapc/rules.mk
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
#
|
||||
# Copyright (c) 2023, MediaTek Inc. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
LOCAL_DIR := $(call GET_LOCAL_DIR)
|
||||
|
||||
MODULE := apusys_devapc
|
||||
|
||||
LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_dapc_v1.c
|
||||
|
||||
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
|
||||
307
plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
Normal file
307
plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
Normal file
|
|
@ -0,0 +1,307 @@
|
|||
/*
|
||||
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/* TF-A system header */
|
||||
#include <common/debug.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Vendor header */
|
||||
#include "apusys.h"
|
||||
#include "apusys_devapc.h"
|
||||
#include "apusys_devapc_def.h"
|
||||
#include <platform_def.h>
|
||||
|
||||
#define DUMP_APUSYS_DAPC (0)
|
||||
|
||||
static const struct apc_dom_16 APU_NOC_DAPC_RCX[] = {
|
||||
/* ctrl index = 0 */
|
||||
SLAVE_MD32_SRAM("slv16-0"),
|
||||
SLAVE_MD32_SRAM("slv16-1"),
|
||||
SLAVE_MD32_SRAM("slv16-2"),
|
||||
SLAVE_MD32_SRAM("slv16-3"),
|
||||
SLAVE_MD32_SRAM("slv16-4"),
|
||||
};
|
||||
|
||||
static const struct apc_dom_16 APU_CTRL_DAPC_AO[] = {
|
||||
/* ctrl index = 0 */
|
||||
SLAVE_VCORE("apu_ao_ctl_o-0"),
|
||||
SLAVE_RPC("apu_ao_ctl_o-2"),
|
||||
SLAVE_PCU("apu_ao_ctl_o-3"),
|
||||
SLAVE_AO_CTRL("apu_ao_ctl_o-4"),
|
||||
SLAVE_PLL("apu_ao_ctl_o-5"),
|
||||
SLAVE_ACC("apu_ao_ctl_o-6"),
|
||||
SLAVE_SEC("apu_ao_ctl_o-7"),
|
||||
SLAVE_ARE0("apu_ao_ctl_o-8"),
|
||||
SLAVE_ARE1("apu_ao_ctl_o-9"),
|
||||
SLAVE_ARE2("apu_ao_ctl_o-10"),
|
||||
|
||||
/* ctrl index = 10 */
|
||||
SLAVE_UNKNOWN("apu_ao_ctl_o-11"),
|
||||
SLAVE_AO_BCRM("apu_ao_ctl_o-12"),
|
||||
SLAVE_AO_DAPC_WRAP("apu_ao_ctl_o-13"),
|
||||
SLAVE_AO_DAPC_CON("apu_ao_ctl_o-14"),
|
||||
SLAVE_RCX_ACX_BULK("apu_ao_ctl_o-15"),
|
||||
SLAVE_UNKNOWN("apu_ao_ctl_o-16"),
|
||||
SLAVE_UNKNOWN("apu_ao_ctl_o-17"),
|
||||
SLAVE_APU_BULK("apu_ao_ctl_o-18"),
|
||||
SLAVE_ACX0_BCRM("apu_ao_ctl_o-20"),
|
||||
SLAVE_RPCTOP_LITE_ACX0("apu_ao_ctl_o-21"),
|
||||
|
||||
/* ctrl index = 20 */
|
||||
SLAVE_ACX1_BCRM("apu_ao_ctl_o-22"),
|
||||
SLAVE_RPCTOP_LITE_ACX1("apu_ao_ctl_o-23"),
|
||||
SLAVE_RCX_TO_ACX0_0("apu_rcx2acx0_o-0"),
|
||||
SLAVE_RCX_TO_ACX0_1("apu_rcx2acx0_o-1"),
|
||||
SLAVE_SAE_TO_ACX0_0("apu_sae2acx0_o-0"),
|
||||
SLAVE_SAE_TO_ACX0_1("apu_sae2acx0_o-1"),
|
||||
SLAVE_RCX_TO_ACX1_0("apu_rcx2acx1_o-0"),
|
||||
SLAVE_RCX_TO_ACX1_1("apu_rcx2acx1_o-1"),
|
||||
SLAVE_SAE_TO_ACX1_0("apu_sae2acx1_o-0"),
|
||||
SLAVE_SAE_TO_ACX1_1("apu_sae2acx1_o-1"),
|
||||
};
|
||||
|
||||
static const struct apc_dom_16 APU_CTRL_DAPC_RCX[] = {
|
||||
/* ctrl index = 0 */
|
||||
SLAVE_MD32_SYSCTRL0("md32_apb_s-0"),
|
||||
SLAVE_MD32_SYSCTRL1("md32_apb_s-1"),
|
||||
SLAVE_MD32_WDT("md32_apb_s-2"),
|
||||
SLAVE_MD32_CACHE("md32_apb_s-3"),
|
||||
SLAVE_RPC("apusys_ao-0"),
|
||||
SLAVE_PCU("apusys_ao-1"),
|
||||
SLAVE_AO_CTRL("apusys_ao-2"),
|
||||
SLAVE_PLL("apusys_ao-3"),
|
||||
SLAVE_ACC("apusys_ao-4"),
|
||||
SLAVE_SEC("apusys_ao-5"),
|
||||
|
||||
/* ctrl index = 10 */
|
||||
SLAVE_ARE0("apusys_ao-6"),
|
||||
SLAVE_ARE1("apusys_ao-7"),
|
||||
SLAVE_ARE2("apusys_ao-8"),
|
||||
SLAVE_UNKNOWN("apusys_ao-9"),
|
||||
SLAVE_AO_BCRM("apusys_ao-10"),
|
||||
SLAVE_AO_DAPC_WRAP("apusys_ao-11"),
|
||||
SLAVE_AO_DAPC_CON("apusys_ao-12"),
|
||||
SLAVE_VCORE("apusys_ao-13"),
|
||||
SLAVE_ACX0_BCRM("apusys_ao-15"),
|
||||
SLAVE_ACX1_BCRM("apusys_ao-16"),
|
||||
|
||||
/* ctrl index = 20 */
|
||||
SLAVE_NOC_AXI("noc_axi"),
|
||||
SLAVE_MD32_DBG("md32_dbg"),
|
||||
SLAVE_DBG_CRTL("apb_infra_dbg"),
|
||||
SLAVE_IOMMU0_BANK0("apu_n_mmu_r0"),
|
||||
SLAVE_IOMMU0_BANK1("apu_n_mmu_r1"),
|
||||
SLAVE_IOMMU0_BANK2("apu_n_mmu_r2"),
|
||||
SLAVE_IOMMU0_BANK3("apu_n_mmu_r3"),
|
||||
SLAVE_IOMMU0_BANK4("apu_n_mmu_r4"),
|
||||
SLAVE_IOMMU1_BANK0("apu_s_mmu_r0"),
|
||||
SLAVE_IOMMU1_BANK1("apu_s_mmu_r1"),
|
||||
|
||||
/* ctrl index = 30 */
|
||||
SLAVE_IOMMU1_BANK2("apu_s_mmu_r2"),
|
||||
SLAVE_IOMMU1_BANK3("apu_s_mmu_r3"),
|
||||
SLAVE_IOMMU1_BANK4("apu_s_mmu_r4"),
|
||||
SLAVE_S0_SSC("apu_s0_ssc_cfg"),
|
||||
SLAVE_N0_SSC("apu_n0_ssc_cfg"),
|
||||
SLAVE_ACP_SSC("apu_acp_ssc_cfg"),
|
||||
SLAVE_S1_SSC("apu_s1_ssc_cfg"),
|
||||
SLAVE_N1_SSC("apu_n1_ssc_cfg"),
|
||||
SLAVE_CFG("apu_rcx_cfg"),
|
||||
SLAVE_SEMA_STIMER("apu_sema_stimer"),
|
||||
|
||||
/* ctrl index = 40 */
|
||||
SLAVE_EMI_CFG("apu_emi_cfg"),
|
||||
SLAVE_LOG("apu_logtop"),
|
||||
SLAVE_CPE_SENSOR("apu_cpe_sensor"),
|
||||
SLAVE_CPE_COEF("apu_cpe_coef"),
|
||||
SLAVE_CPE_CTRL("apu_cpe_ctrl"),
|
||||
SLAVE_UNKNOWN("apu_xpu_rsi"),
|
||||
SLAVE_DFD_REG_SOC("apu_dfd"),
|
||||
SLAVE_SENSOR_WRAP_ACX0_DLA0("apu_sen_ac0_dla0"),
|
||||
SLAVE_SENSOR_WRAP_ACX0_DLA1("apu_sen_ac0_dla1"),
|
||||
SLAVE_SENSOR_WRAP_ACX0_VPU0("apu_sen_ac0_vpu"),
|
||||
|
||||
/* ctrl index = 50 */
|
||||
SLAVE_SENSOR_WRAP_ACX1_DLA0("apu_sen_ac1_dla0"),
|
||||
SLAVE_SENSOR_WRAP_ACX1_DLA1("apu_sen_ac1_dla1"),
|
||||
SLAVE_SENSOR_WRAP_ACX1_VPU0("apu_sen_ac1_vpu"),
|
||||
SLAVE_REVISER("noc_cfg-0"),
|
||||
SLAVE_NOC("noc_cfg-1"),
|
||||
SLAVE_BCRM("infra_bcrm"),
|
||||
SLAVE_DAPC_WRAP("infra_dapc_wrap"),
|
||||
SLAVE_DAPC_CON("infra_dapc_con"),
|
||||
SLAVE_NOC_DAPC_WRAP("noc_dapc_wrap"),
|
||||
SLAVE_NOC_DAPC_CON("noc_dapc_con"),
|
||||
|
||||
/* ctrl index = 60 */
|
||||
SLAVE_NOC_BCRM("noc_bcrm"),
|
||||
SLAVE_ACS("apu_rcx_acs"),
|
||||
SLAVE_HSE("apu_hse"),
|
||||
};
|
||||
|
||||
static enum apusys_apc_err_status set_slave_ao_ctrl_apc(uint32_t slave,
|
||||
enum apusys_apc_domain_id domain_id,
|
||||
enum apusys_apc_perm_type perm)
|
||||
{
|
||||
uint32_t apc_register_index;
|
||||
uint32_t apc_set_index;
|
||||
uint32_t base;
|
||||
uint32_t clr_bit;
|
||||
uint32_t set_bit;
|
||||
|
||||
if ((perm < 0) || (perm >= PERM_NUM)) {
|
||||
ERROR(MODULE_TAG "%s: permission type:0x%x is not supported!\n", __func__, perm);
|
||||
return APUSYS_APC_ERR_GENERIC;
|
||||
}
|
||||
|
||||
if ((slave >= APU_CTRL_DAPC_AO_SLAVE_NUM) ||
|
||||
((domain_id < 0) || (domain_id >= APU_CTRL_DAPC_AO_DOM_NUM))) {
|
||||
ERROR(MODULE_TAG "%s: out of boundary, slave:0x%x, domain_id:0x%x\n",
|
||||
__func__, slave, domain_id);
|
||||
return APUSYS_APC_ERR_GENERIC;
|
||||
}
|
||||
|
||||
apc_register_index = slave / APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM;
|
||||
apc_set_index = slave % APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM;
|
||||
|
||||
clr_bit = (DEVAPC_MASK << (apc_set_index * DEVAPC_DOM_SHIFT));
|
||||
set_bit = (uint32_t)perm << (apc_set_index * DEVAPC_DOM_SHIFT);
|
||||
|
||||
base = (APU_CTRL_DAPC_AO_BASE + domain_id * DEVAPC_DOM_SIZE +
|
||||
apc_register_index * DEVAPC_REG_SIZE);
|
||||
|
||||
mmio_clrsetbits_32(base, clr_bit, set_bit);
|
||||
return APUSYS_APC_OK;
|
||||
}
|
||||
|
||||
static enum apusys_apc_err_status set_slave_noc_dapc_rcx(uint32_t slave,
|
||||
enum apusys_apc_domain_id domain_id,
|
||||
enum apusys_apc_perm_type perm)
|
||||
{
|
||||
uint32_t apc_register_index;
|
||||
uint32_t apc_set_index;
|
||||
uint32_t base;
|
||||
uint32_t clr_bit;
|
||||
uint32_t set_bit;
|
||||
|
||||
if ((perm >= PERM_NUM) || (perm < 0)) {
|
||||
ERROR(MODULE_TAG "%s: permission type:0x%x is not supported!\n", __func__, perm);
|
||||
return APUSYS_APC_ERR_GENERIC;
|
||||
}
|
||||
|
||||
if ((slave >= APU_NOC_DAPC_RCX_SLAVE_NUM) ||
|
||||
((domain_id < 0) || (domain_id >= APU_NOC_DAPC_RCX_DOM_NUM))) {
|
||||
ERROR(MODULE_TAG "%s: out of boundary, slave:0x%x, domain_id:0x%x\n",
|
||||
__func__, slave, domain_id);
|
||||
return APUSYS_APC_ERR_GENERIC;
|
||||
}
|
||||
|
||||
apc_register_index = slave / APU_NOC_DAPC_RCX_SLAVE_NUM_IN_1_DOM;
|
||||
apc_set_index = slave % APU_NOC_DAPC_RCX_SLAVE_NUM_IN_1_DOM;
|
||||
|
||||
clr_bit = (DEVAPC_MASK << (apc_set_index * DEVAPC_DOM_SHIFT));
|
||||
set_bit = ((uint32_t)perm) << (apc_set_index * DEVAPC_DOM_SHIFT);
|
||||
base = (APU_NOC_DAPC_RCX_BASE + domain_id * DEVAPC_DOM_SIZE +
|
||||
apc_register_index * DEVAPC_REG_SIZE);
|
||||
|
||||
mmio_clrsetbits_32(base, clr_bit, set_bit);
|
||||
return APUSYS_APC_OK;
|
||||
}
|
||||
|
||||
static enum apusys_apc_err_status set_slave_rcx_ctrl_apc(uint32_t slave,
|
||||
enum apusys_apc_domain_id domain_id,
|
||||
enum apusys_apc_perm_type perm)
|
||||
{
|
||||
uint32_t apc_register_index;
|
||||
uint32_t apc_set_index;
|
||||
uint32_t base;
|
||||
uint32_t clr_bit;
|
||||
uint32_t set_bit;
|
||||
|
||||
if ((perm < 0) || (perm >= PERM_NUM)) {
|
||||
ERROR(MODULE_TAG "%s: permission type:0x%x is not supported!\n", __func__, perm);
|
||||
return APUSYS_APC_ERR_GENERIC;
|
||||
}
|
||||
|
||||
if ((slave >= APU_CTRL_DAPC_RCX_SLAVE_NUM) ||
|
||||
((domain_id < 0) || (domain_id >= APU_CTRL_DAPC_RCX_DOM_NUM))) {
|
||||
ERROR(MODULE_TAG "%s: out of boundary, slave:0x%x, domain_id:0x%x\n",
|
||||
__func__, slave, domain_id);
|
||||
return APUSYS_APC_ERR_GENERIC;
|
||||
}
|
||||
|
||||
apc_register_index = slave / APU_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM;
|
||||
apc_set_index = slave % APU_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM;
|
||||
|
||||
clr_bit = (DEVAPC_MASK << (apc_set_index * DEVAPC_DOM_SHIFT));
|
||||
set_bit = (uint32_t)perm << (apc_set_index * DEVAPC_DOM_SHIFT);
|
||||
base = (APU_CTRL_DAPC_RCX_BASE + domain_id * DEVAPC_DOM_SIZE +
|
||||
apc_register_index * DEVAPC_REG_SIZE);
|
||||
|
||||
mmio_clrsetbits_32(base, clr_bit, set_bit);
|
||||
return APUSYS_APC_OK;
|
||||
}
|
||||
|
||||
static void apusys_devapc_init(const char *name, uint32_t base)
|
||||
{
|
||||
mmio_write_32(APUSYS_DAPC_CON(base), APUSYS_DAPC_CON_VIO_MASK);
|
||||
}
|
||||
|
||||
int apusys_devapc_ao_init(void)
|
||||
{
|
||||
enum apusys_apc_err_status ret;
|
||||
|
||||
apusys_devapc_init("APUAPC_CTRL_AO", APU_CTRL_DAPC_AO_BASE);
|
||||
|
||||
ret = SET_APUSYS_DAPC_V1(APU_CTRL_DAPC_AO, set_slave_ao_ctrl_apc);
|
||||
if (ret != APUSYS_APC_OK) {
|
||||
ERROR(MODULE_TAG "%s: set_apusys_ao_ctrl_dap FAILED!\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
#if DUMP_APUSYS_DAPC
|
||||
DUMP_APUSYS_DAPC_V1(APU_CTRL_DAPC_AO);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int apusys_devapc_rcx_init(void)
|
||||
{
|
||||
static bool apusys_devapc_rcx_init_called;
|
||||
enum apusys_apc_err_status ret;
|
||||
|
||||
if (apusys_devapc_rcx_init_called == true) {
|
||||
INFO(MODULE_TAG "%s: init more than once!\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
apusys_devapc_rcx_init_called = true;
|
||||
|
||||
apusys_devapc_init("APUAPC_CTRL_RCX", APU_CTRL_DAPC_RCX_BASE);
|
||||
apusys_devapc_init("APUAPC_NOC_RCX", APU_NOC_DAPC_RCX_BASE);
|
||||
|
||||
ret = SET_APUSYS_DAPC_V1(APU_CTRL_DAPC_RCX, set_slave_rcx_ctrl_apc);
|
||||
if (ret != APUSYS_APC_OK) {
|
||||
ERROR(MODULE_TAG "%s: set_slave_rcx_ctrl_apc FAILED!\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
#if DUMP_APUSYS_DAPC
|
||||
DUMP_APUSYS_DAPC_V1(APU_CTRL_DAPC_RCX);
|
||||
#endif
|
||||
|
||||
ret = SET_APUSYS_DAPC_V1(APU_NOC_DAPC_RCX, set_slave_noc_dapc_rcx);
|
||||
if (ret != APUSYS_APC_OK) {
|
||||
ERROR(MODULE_TAG "%s: set_slave_noc_dapc_rcx FAILED\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
#if DUMP_APUSYS_DAPC
|
||||
DUMP_APUSYS_DAPC_V1(APU_NOC_DAPC_RCX);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
13
plat/mediatek/drivers/apusys/mt8188/apusys_devapc.h
Normal file
13
plat/mediatek/drivers/apusys/mt8188/apusys_devapc.h
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef APUSYS_DEVAPC_H
|
||||
#define APUSYS_DEVAPC_H
|
||||
|
||||
int apusys_devapc_ao_init(void);
|
||||
int apusys_devapc_rcx_init(void);
|
||||
|
||||
#endif /* APUSYS_DEVAPC_H */
|
||||
109
plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h
Normal file
109
plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef APUSYS_DEVAPC_DEF_H
|
||||
#define APUSYS_DEVAPC_DEF_H
|
||||
|
||||
#include <lib/mmio.h>
|
||||
#include "../devapc/apusys_dapc_v1.h"
|
||||
|
||||
/* NoC */
|
||||
#define SLAVE_MD32_SRAM SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
|
||||
/* Control */
|
||||
#define SLAVE_VCORE SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_RPC SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
|
||||
#define SLAVE_PCU SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_AO_CTRL SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_PLL SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
|
||||
#define SLAVE_ACC SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_SEC SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_ARE0 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_ARE1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_ARE2 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_UNKNOWN SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_APU_BULK SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_AO_BCRM SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_AO_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_AO_DAPC_CON SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_RCX_ACX_BULK SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
|
||||
#define SLAVE_ACX0_BCRM SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
|
||||
#define SLAVE_RPCTOP_LITE_ACX0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
|
||||
#define SLAVE_ACX1_BCRM SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
|
||||
#define SLAVE_RPCTOP_LITE_ACX1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
|
||||
#define SLAVE_RCX_TO_ACX0_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
|
||||
#define SLAVE_RCX_TO_ACX0_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
|
||||
#define SLAVE_SAE_TO_ACX0_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
|
||||
#define SLAVE_SAE_TO_ACX0_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
|
||||
#define SLAVE_RCX_TO_ACX1_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
|
||||
#define SLAVE_RCX_TO_ACX1_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
|
||||
#define SLAVE_SAE_TO_ACX1_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
|
||||
#define SLAVE_SAE_TO_ACX1_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
|
||||
#define SLAVE_MD32_SYSCTRL0 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_MD32_SYSCTRL1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
|
||||
#define SLAVE_MD32_WDT SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_MD32_CACHE SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_NOC_AXI SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
|
||||
#define SLAVE_MD32_DBG SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
|
||||
#define SLAVE_DBG_CRTL SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_IOMMU0_BANK0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
|
||||
#define SLAVE_IOMMU0_BANK1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_IOMMU0_BANK2 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_IOMMU0_BANK3 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_IOMMU0_BANK4 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_IOMMU1_BANK0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
|
||||
#define SLAVE_IOMMU1_BANK1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_IOMMU1_BANK2 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_IOMMU1_BANK3 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_IOMMU1_BANK4 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_S0_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_N0_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_ACP_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_S1_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_N1_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_CFG SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
|
||||
#define SLAVE_SEMA_STIMER SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_EMI_CFG SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_LOG SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
|
||||
#define SLAVE_CPE_SENSOR SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_CPE_COEF SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_CPE_CTRL SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_DFD_REG_SOC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_SENSOR_WRAP_ACX0_DLA0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_SENSOR_WRAP_ACX0_DLA1 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_SENSOR_WRAP_ACX0_VPU0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_SENSOR_WRAP_ACX1_DLA0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_SENSOR_WRAP_ACX1_DLA1 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_SENSOR_WRAP_ACX1_VPU0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_REVISER SLAVE_FORBID_EXCEPT_D0_SEC_RW
|
||||
#define SLAVE_NOC SLAVE_FORBID_EXCEPT_D0_D3_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_BCRM SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_DAPC_CON SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_NOC_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_NOC_DAPC_CON SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_NOC_BCRM SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
#define SLAVE_ACS SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
|
||||
#define SLAVE_HSE SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
|
||||
|
||||
|
||||
/* Power Domain: AO */
|
||||
#define APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM (16)
|
||||
#define APU_CTRL_DAPC_AO_DOM_NUM (16)
|
||||
#define APU_CTRL_DAPC_AO_SLAVE_NUM (30)
|
||||
#define DEVAPC_MASK (0x3U)
|
||||
#define DEVAPC_DOM_SHIFT (2)
|
||||
|
||||
/* Power Domain: RCX */
|
||||
#define APU_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM (16)
|
||||
#define APU_CTRL_DAPC_RCX_DOM_NUM (16)
|
||||
#define APU_CTRL_DAPC_RCX_SLAVE_NUM (63)
|
||||
|
||||
#define APU_NOC_DAPC_RCX_SLAVE_NUM_IN_1_DOM (16)
|
||||
#define APU_NOC_DAPC_RCX_DOM_NUM (16)
|
||||
#define APU_NOC_DAPC_RCX_SLAVE_NUM (5)
|
||||
|
||||
#endif /* APUSYS_DEVAPC_DEF_H */
|
||||
|
|
@ -17,6 +17,7 @@
|
|||
/* Vendor header */
|
||||
#include "apusys.h"
|
||||
#include "apusys_power.h"
|
||||
#include "apusys_rv.h"
|
||||
#include <mtk_mmap_pool.h>
|
||||
|
||||
static spinlock_t apu_lock;
|
||||
|
|
@ -47,6 +48,43 @@ static int apu_poll(uintptr_t reg, uint32_t mask, uint32_t value, uint32_t timeo
|
|||
return -1;
|
||||
}
|
||||
|
||||
static void apu_backup_restore(enum APU_BACKUP_RESTORE_CTRL ctrl)
|
||||
{
|
||||
int i;
|
||||
static struct apu_restore_data apu_restore_data[] = {
|
||||
{ UP_NORMAL_DOMAIN_NS, 0 },
|
||||
{ UP_PRI_DOMAIN_NS, 0 },
|
||||
{ UP_IOMMU_CTRL, 0 },
|
||||
{ UP_CORE0_VABASE0, 0 },
|
||||
{ UP_CORE0_MVABASE0, 0 },
|
||||
{ UP_CORE0_VABASE1, 0 },
|
||||
{ UP_CORE0_MVABASE1, 0 },
|
||||
{ UP_CORE0_VABASE2, 0 },
|
||||
{ UP_CORE0_MVABASE2, 0 },
|
||||
{ UP_CORE0_VABASE3, 0 },
|
||||
{ UP_CORE0_MVABASE3, 0 },
|
||||
{ MD32_SYS_CTRL, 0 },
|
||||
{ MD32_CLK_CTRL, 0 },
|
||||
{ UP_WAKE_HOST_MASK0, 0 }
|
||||
};
|
||||
|
||||
switch (ctrl) {
|
||||
case APU_CTRL_BACKUP:
|
||||
for (i = 0; i < ARRAY_SIZE(apu_restore_data); i++) {
|
||||
apu_restore_data[i].data = mmio_read_32(apu_restore_data[i].reg);
|
||||
}
|
||||
break;
|
||||
case APU_CTRL_RESTORE:
|
||||
for (i = 0; i < ARRAY_SIZE(apu_restore_data); i++) {
|
||||
mmio_write_32(apu_restore_data[i].reg, apu_restore_data[i].data);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
ERROR(MODULE_TAG "%s invalid op: %d\n", __func__, ctrl);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void apu_xpu2apusys_d4_slv_en(enum APU_D4_SLV_CTRL en)
|
||||
{
|
||||
switch (en) {
|
||||
|
|
@ -120,6 +158,8 @@ int apusys_kernel_apusys_pwr_top_on(void)
|
|||
|
||||
apu_xpu2apusys_d4_slv_en(D4_SLV_OFF);
|
||||
|
||||
apu_backup_restore(APU_CTRL_RESTORE);
|
||||
|
||||
apusys_top_on = true;
|
||||
|
||||
spin_unlock(&apu_lock);
|
||||
|
|
@ -153,6 +193,8 @@ int apusys_kernel_apusys_pwr_top_off(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
apu_backup_restore(APU_CTRL_BACKUP);
|
||||
|
||||
apu_xpu2apusys_d4_slv_en(D4_SLV_ON);
|
||||
|
||||
if (mmio_read_32(APU_MBOX0_BASE + PWR_FLOW_SYNC_REG) == 0) {
|
||||
|
|
|
|||
|
|
@ -29,6 +29,16 @@ enum APU_D4_SLV_CTRL {
|
|||
D4_SLV_ON,
|
||||
};
|
||||
|
||||
enum APU_BACKUP_RESTORE_CTRL {
|
||||
APU_CTRL_BACKUP = 0,
|
||||
APU_CTRL_RESTORE = 1,
|
||||
};
|
||||
|
||||
struct apu_restore_data {
|
||||
uint32_t reg;
|
||||
uint32_t data;
|
||||
};
|
||||
|
||||
#define APU_POLL_STEP_US (5)
|
||||
|
||||
#define OUT_CLK_FREQ_MIN (1500)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/* TF-A system header */
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
/* Vendor header */
|
||||
#include "apusys_security_ctrl_plat.h"
|
||||
|
||||
static void apusys_domain_remap_init(void)
|
||||
{
|
||||
const uint32_t remap_domains[] = {
|
||||
D0_REMAP_DOMAIN, D1_REMAP_DOMAIN, D2_REMAP_DOMAIN, D3_REMAP_DOMAIN,
|
||||
D4_REMAP_DOMAIN, D5_REMAP_DOMAIN, D6_REMAP_DOMAIN, D7_REMAP_DOMAIN,
|
||||
D8_REMAP_DOMAIN, D9_REMAP_DOMAIN, D10_REMAP_DOMAIN, D11_REMAP_DOMAIN,
|
||||
D12_REMAP_DOMAIN, D13_REMAP_DOMAIN, D14_REMAP_DOMAIN, D15_REMAP_DOMAIN
|
||||
};
|
||||
uint32_t lower_domain = 0;
|
||||
uint32_t higher_domain = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(remap_domains); i++) {
|
||||
if (i < REG_DOMAIN_NUM) {
|
||||
lower_domain |= (remap_domains[i] << (i * REG_DOMAIN_BITS));
|
||||
} else {
|
||||
higher_domain |= (remap_domains[i] <<
|
||||
((i - REG_DOMAIN_NUM) * REG_DOMAIN_BITS));
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(SOC2APU_SET1_0, lower_domain);
|
||||
mmio_write_32(SOC2APU_SET1_1, higher_domain);
|
||||
mmio_setbits_32(APU_SEC_CON, DOMAIN_REMAP_SEL);
|
||||
}
|
||||
|
||||
void apusys_security_ctrl_init(void)
|
||||
{
|
||||
apusys_domain_remap_init();
|
||||
}
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef APUSYS_SECURITY_CTRL_PLAT_H
|
||||
#define APUSYS_SECURITY_CTRL_PLAT_H
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#define SOC2APU_SET1_0 (APU_SEC_CON + 0x0c)
|
||||
#define SOC2APU_SET1_1 (APU_SEC_CON + 0x10)
|
||||
|
||||
#define REG_DOMAIN_NUM (8)
|
||||
#define REG_DOMAIN_BITS (4)
|
||||
#define DOMAIN_REMAP_SEL BIT(6)
|
||||
|
||||
#define D0_REMAP_DOMAIN (0)
|
||||
#define D1_REMAP_DOMAIN (1)
|
||||
#define D2_REMAP_DOMAIN (2)
|
||||
#define D3_REMAP_DOMAIN (3)
|
||||
#define D4_REMAP_DOMAIN (4)
|
||||
#define D5_REMAP_DOMAIN (14)
|
||||
#define D6_REMAP_DOMAIN (6)
|
||||
#define D7_REMAP_DOMAIN (14)
|
||||
#define D8_REMAP_DOMAIN (8)
|
||||
#define D9_REMAP_DOMAIN (9)
|
||||
#define D10_REMAP_DOMAIN (10)
|
||||
#define D11_REMAP_DOMAIN (11)
|
||||
#define D12_REMAP_DOMAIN (12)
|
||||
#define D13_REMAP_DOMAIN (13)
|
||||
#define D14_REMAP_DOMAIN (14)
|
||||
#define D15_REMAP_DOMAIN (15)
|
||||
|
||||
void apusys_security_ctrl_init(void);
|
||||
|
||||
#endif /* APUSYS_SECURITY_CTRL_PLAT_H */
|
||||
|
|
@ -8,6 +8,8 @@ LOCAL_DIR := $(call GET_LOCAL_DIR)
|
|||
|
||||
MODULE := apusys_${MTK_SOC}
|
||||
|
||||
LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_power.c
|
||||
LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_devapc.c
|
||||
LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_power.c
|
||||
LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_security_ctrl_plat.c
|
||||
|
||||
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
|
||||
|
|
|
|||
|
|
@ -10,10 +10,12 @@ MODULE := apusys
|
|||
|
||||
LOCAL_SRCS-y:= ${LOCAL_DIR}/apusys.c
|
||||
|
||||
PLAT_INCLUDES += -I${LOCAL_DIR} -I${LOCAL_DIR}/${MTK_SOC}
|
||||
PLAT_INCLUDES += -I${LOCAL_DIR} -I${LOCAL_DIR}/${MTK_SOC} -I${LOCAL_DIR}/apusys_rv/2.0
|
||||
|
||||
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
|
||||
|
||||
SUB_RULES-y := ${LOCAL_DIR}/${MTK_SOC}
|
||||
SUB_RULES-y += ${LOCAL_DIR}/devapc
|
||||
SUB_RULES-y += ${LOCAL_DIR}/apusys_rv/2.0
|
||||
|
||||
$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y)))
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -60,5 +60,6 @@ struct emi_region_info_t {
|
|||
int emi_mpu_init(void);
|
||||
int emi_mpu_set_protection(struct emi_region_info_t *region_info);
|
||||
void set_emi_mpu_regions(void);
|
||||
int set_apu_emi_mpu_region(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -12,3 +12,20 @@ void set_emi_mpu_regions(void)
|
|||
/* TODO: set emi mpu region */
|
||||
INFO("%s, emi mpu is not setting currently\n", __func__);
|
||||
}
|
||||
|
||||
int set_apu_emi_mpu_region(void)
|
||||
{
|
||||
struct emi_region_info_t region_info;
|
||||
|
||||
region_info.start = (unsigned long long)APUSYS_SEC_BUF_PA;
|
||||
region_info.end = (unsigned long long)(APUSYS_SEC_BUF_PA + APUSYS_SEC_BUF_SZ) - 1;
|
||||
region_info.region = APUSYS_SEC_BUF_EMI_REGION;
|
||||
|
||||
SET_ACCESS_PERMISSION(region_info.apc, UNLOCK,
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
|
||||
NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
|
||||
FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
|
||||
|
||||
return emi_mpu_set_protection(®ion_info);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -42,4 +42,9 @@
|
|||
|
||||
#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8)
|
||||
|
||||
/* APU EMI MPU Setting */
|
||||
#define APUSYS_SEC_BUF_EMI_REGION (21)
|
||||
#define APUSYS_SEC_BUF_PA (0x55000000)
|
||||
#define APUSYS_SEC_BUF_SZ (0x100000)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -28,17 +28,25 @@
|
|||
* APUSYS related constants
|
||||
******************************************************************************/
|
||||
#define BCRM_FMEM_PDN_BASE (IO_PHYS + 0x00276000)
|
||||
#define APU_MD32_SYSCTRL (IO_PHYS + 0x09001000)
|
||||
#define APU_MD32_WDT (IO_PHYS + 0x09002000)
|
||||
#define APU_RCX_CONFIG (IO_PHYS + 0x09020000)
|
||||
#define APU_CTRL_DAPC_RCX_BASE (IO_PHYS + 0x09034000)
|
||||
#define APU_NOC_DAPC_RCX_BASE (IO_PHYS + 0x09038000)
|
||||
#define APU_REVISER (IO_PHYS + 0x0903c000)
|
||||
#define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090e0000)
|
||||
#define APU_MBOX0 (IO_PHYS + 0x090e1000)
|
||||
#define APU_MBOX1 (IO_PHYS + 0x090e2000)
|
||||
#define APU_RPCTOP (IO_PHYS + 0x090f0000)
|
||||
#define APU_PCUTOP (IO_PHYS + 0x090f1000)
|
||||
#define APU_AO_CTRL (IO_PHYS + 0x090f2000)
|
||||
#define APU_PLL (IO_PHYS + 0x090f3000)
|
||||
#define APU_ACC (IO_PHYS + 0x090f4000)
|
||||
#define APU_SEC_CON (IO_PHYS + 0x090f5000)
|
||||
#define APU_ARETOP_ARE0 (IO_PHYS + 0x090f6000)
|
||||
#define APU_ARETOP_ARE1 (IO_PHYS + 0x090f7000)
|
||||
#define APU_ARETOP_ARE2 (IO_PHYS + 0x090f8000)
|
||||
#define APU_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090fc000)
|
||||
#define APU_ACX0_RPC_LITE (IO_PHYS + 0x09140000)
|
||||
#define BCRM_FMEM_PDN_SIZE (0x1000)
|
||||
|
||||
|
|
@ -193,7 +201,7 @@
|
|||
* Platform memory map related constants
|
||||
******************************************************************************/
|
||||
#define TZRAM_BASE (0x54600000)
|
||||
#define TZRAM_SIZE (0x00030000)
|
||||
#define TZRAM_SIZE (0x00040000)
|
||||
|
||||
/*******************************************************************************
|
||||
* BL31 specific defines.
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue