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feat(mediatek): add APU watchdog timeout control

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Add APU watchdog timeout control.

Change-Id: I21d65a88d20b6b2752a75f74487b5fe6596ebdf7
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>
This commit is contained in:
Chungying Lu 2023-05-12 18:37:32 +08:00 • committed by Karl Li
parent 176846a50b
commit baa0d45ced
4 changed files with 74 additions and 0 deletions
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12
plat/mediatek/drivers/apusys/apusys.c
View file

@ -56,6 +56,18 @@ static u_register_t apusys_kernel_handler(u_register_t x1,
case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_SEC_MEM:
ret = apusys_kernel_apusys_rv_setup_sec_mem();
break;
case MTK_APUSYS_KERNEL_OP_APUSYS_RV_DISABLE_WDT_ISR:
ret = apusys_kernel_apusys_rv_disable_wdt_isr();
break;
case MTK_APUSYS_KERNEL_OP_APUSYS_RV_CLEAR_WDT_ISR:
ret = apusys_kernel_apusys_rv_clear_wdt_isr();
break;
case MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_GATING:
ret = apusys_kernel_apusys_rv_cg_gating();
break;
case MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_UNGATING:
ret = apusys_kernel_apusys_rv_cg_ungating();
break;
default:
ERROR(MODULE_TAG "%s unknown request_ops = %x\n", MODULE_TAG, request_ops);
break;

4
plat/mediatek/drivers/apusys/apusys.h
View file

@ -19,6 +19,10 @@ enum MTK_APUSYS_KERNEL_OP {
MTK_APUSYS_KERNEL_OP_APUSYS_RV_STOP_MP, /* 6 */
MTK_APUSYS_KERNEL_OP_DEVAPC_INIT_RCX, /* 7 */
MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_SEC_MEM, /* 8 */
MTK_APUSYS_KERNEL_OP_APUSYS_RV_DISABLE_WDT_ISR, /* 9 */
MTK_APUSYS_KERNEL_OP_APUSYS_RV_CLEAR_WDT_ISR, /* 10 */
MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_GATING, /* 11 */
MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_UNGATING, /* 12 */
MTK_APUSYS_KERNEL_OP_NUM,
};

49
plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
View file

@ -206,3 +206,52 @@ int apusys_kernel_apusys_rv_setup_sec_mem(void)
spin_unlock(&apusys_rv_lock);
return ret;
}
int apusys_kernel_apusys_rv_disable_wdt_isr(void)
{
spin_lock(&apusys_rv_lock);
mmio_clrbits_32(WDT_CTRL0, WDT_EN);
spin_unlock(&apusys_rv_lock);
return 0;
}
int apusys_kernel_apusys_rv_clear_wdt_isr(void)
{
spin_lock(&apusys_rv_lock);
mmio_clrbits_32(UP_INT_EN2, DBG_APB_EN);
mmio_write_32(WDT_INT, WDT_INT_W1C);
spin_unlock(&apusys_rv_lock);
return 0;
}
int apusys_kernel_apusys_rv_cg_gating(void)
{
spin_lock(&apusys_rv_lock);
if (watch_dog_is_timeout() == false) {
spin_unlock(&apusys_rv_lock);
return -1;
}
mmio_write_32(MD32_CLK_CTRL, MD32_CLK_DIS);
spin_unlock(&apusys_rv_lock);
return 0;
}
int apusys_kernel_apusys_rv_cg_ungating(void)
{
spin_lock(&apusys_rv_lock);
if (watch_dog_is_timeout() == false) {
spin_unlock(&apusys_rv_lock);
return -1;
}
mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN);
spin_unlock(&apusys_rv_lock);
return 0;
}

9
plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h
View file

@ -46,6 +46,7 @@
/* APU_MD32_SYSCTRL */
#define MD32_SYS_CTRL (APU_MD32_SYSCTRL + 0x0000)
#define UP_INT_EN2 (APU_MD32_SYSCTRL + 0x000c)
#define MD32_CLK_CTRL (APU_MD32_SYSCTRL + 0x00b8)
#define UP_WAKE_HOST_MASK0 (APU_MD32_SYSCTRL + 0x00bc)
#define UP_WAKE_HOST_MASK1 (APU_MD32_SYSCTRL + 0x00c0)
@ -58,11 +59,13 @@
#define MD32_PM_ARUSER_IOMMU_EN BIT(3)
#define MD32_SOFT_RSTN BIT(0)
#define MD32_CLK_EN (1)
#define MD32_CLK_DIS (0)
#define WDT_IRQ_EN BIT(0)
#define MBOX0_IRQ_EN BIT(21)
#define MBOX1_IRQ_EN BIT(22)
#define MBOX2_IRQ_EN BIT(23)
#define RESET_DEALY_US (10)
#define DBG_APB_EN BIT(31)
/* APU_AO_CTRL */
#define MD32_PRE_DEFINE (APU_AO_CTRL + 0x0000)
@ -81,7 +84,9 @@
/* APU_MD32_WDT */
#define WDT_INT (APU_MD32_WDT + 0x0)
#define WDT_CTRL0 (APU_MD32_WDT + 0x4)
#define WDT_INT_W1C (1)
#define WDT_EN BIT(31)
/* APU MBOX */
#define MBOX_FUNC_CFG (0xb0)
@ -107,5 +112,9 @@ int apusys_kernel_apusys_rv_setup_boot(void);
int apusys_kernel_apusys_rv_start_mp(void);
int apusys_kernel_apusys_rv_stop_mp(void);
int apusys_kernel_apusys_rv_setup_sec_mem(void);
int apusys_kernel_apusys_rv_disable_wdt_isr(void);
int apusys_kernel_apusys_rv_clear_wdt_isr(void);
int apusys_kernel_apusys_rv_cg_gating(void);
int apusys_kernel_apusys_rv_cg_ungating(void);
#endif /* APUSYS_RV_H */