mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-18 02:24:18 +00:00
feat(mediatek): add APU bootup control smc call
Add APU bootup control smc call. The steps of bootup flow: 1. set up APU config. 2. reset APU. 3. set up APU boot config. 4. boot APU. Change-Id: I9e930070a64c7c4dcaa3a8b3d28b897823e9f53c Signed-off-by: Chungying Lu <chungying.lu@mediatek.com> Signed-off-by: Karl Li <karl.li@mediatek.com>
This commit is contained in:
Chungying Lu
Karl Li
parent
ad7673adef
commit
94a9e6243e
5 changed files with 263 additions and 12 deletions
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@ -35,6 +35,21 @@ static u_register_t apusys_kernel_handler(u_register_t x1,
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case MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF:
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ret = apusys_kernel_apusys_pwr_top_off();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_REVISER:
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ret = apusys_kernel_apusys_rv_setup_reviser();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_RESET_MP:
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ret = apusys_kernel_apusys_rv_reset_mp();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_BOOT:
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ret = apusys_kernel_apusys_rv_setup_boot();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_START_MP:
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ret = apusys_kernel_apusys_rv_start_mp();
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break;
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case MTK_APUSYS_KERNEL_OP_APUSYS_RV_STOP_MP:
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ret = apusys_kernel_apusys_rv_stop_mp();
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break;
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default:
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ERROR(MODULE_TAG "%s unknown request_ops = %x\n", MODULE_TAG, request_ops);
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break;
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@ -10,8 +10,13 @@
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#define MODULE_TAG "[APUSYS]"
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enum MTK_APUSYS_KERNEL_OP {
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MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON, /* 0 */
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MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF,/* 1 */
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MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON, /* 0 */
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MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF, /* 1 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_REVISER, /* 2 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_RESET_MP, /* 3 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_BOOT, /* 4 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_START_MP, /* 5 */
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MTK_APUSYS_KERNEL_OP_APUSYS_RV_STOP_MP, /* 6 */
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MTK_APUSYS_KERNEL_OP_NUM,
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};
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@ -6,12 +6,17 @@
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/* TF-A system header */
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/spinlock.h>
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/* Vendor header */
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#include "apusys.h"
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#include "apusys_rv.h"
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#include "apusys_rv_mbox_mpu.h"
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static spinlock_t apusys_rv_lock;
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void apusys_rv_mbox_mpu_init(void)
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{
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int i;
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@ -28,3 +33,151 @@ void apusys_rv_mbox_mpu_init(void)
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(mbox_mpu_setting_tab[i].tx_domain << MBOX_TX_DOMAIN_SHIFT)));
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}
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}
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int apusys_kernel_apusys_rv_setup_reviser(void)
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{
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static bool apusys_rv_setup_reviser_called;
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spin_lock(&apusys_rv_lock);
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if (apusys_rv_setup_reviser_called) {
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WARN(MODULE_TAG "%s: already initialized\n", __func__);
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spin_unlock(&apusys_rv_lock);
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return -1;
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}
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apusys_rv_setup_reviser_called = true;
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mmio_write_32(USERFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
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mmio_write_32(SECUREFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
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mmio_write_32(UP_IOMMU_CTRL, MMU_CTRL_LOCK | MMU_CTRL | MMU_EN);
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mmio_write_32(UP_NORMAL_DOMAIN_NS,
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(UP_NORMAL_DOMAIN << UP_DOMAIN_SHIFT) | (UP_NORMAL_NS << UP_NS_SHIFT));
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mmio_write_32(UP_PRI_DOMAIN_NS,
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(UP_PRI_DOMAIN << UP_DOMAIN_SHIFT) | (UP_PRI_NS << UP_NS_SHIFT));
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mmio_write_32(UP_CORE0_VABASE0,
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VLD | PARTIAL_ENABLE | (THREAD_NUM_PRI << THREAD_NUM_SHIFT));
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mmio_write_32(UP_CORE0_MVABASE0, VASIZE_1MB | (APU_SEC_FW_IOVA >> MVA_34BIT_SHIFT));
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mmio_write_32(UP_CORE0_VABASE1,
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VLD | PARTIAL_ENABLE | (THREAD_NUM_NORMAL << THREAD_NUM_SHIFT));
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mmio_write_32(UP_CORE0_MVABASE1, VASIZE_1MB | (APU_SEC_FW_IOVA >> MVA_34BIT_SHIFT));
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spin_unlock(&apusys_rv_lock);
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return 0;
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}
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int apusys_kernel_apusys_rv_reset_mp(void)
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{
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static bool apusys_rv_reset_mp_called;
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spin_lock(&apusys_rv_lock);
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if (apusys_rv_reset_mp_called) {
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WARN(MODULE_TAG "%s: already initialized\n", __func__);
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spin_unlock(&apusys_rv_lock);
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return -1;
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}
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apusys_rv_reset_mp_called = true;
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mmio_write_32(MD32_SYS_CTRL, MD32_SYS_CTRL_RST);
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udelay(RESET_DEALY_US);
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mmio_write_32(MD32_SYS_CTRL, MD32_G2B_CG_EN | MD32_DBG_EN | MD32_DM_AWUSER_IOMMU_EN |
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MD32_DM_ARUSER_IOMMU_EN | MD32_PM_AWUSER_IOMMU_EN | MD32_PM_ARUSER_IOMMU_EN |
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MD32_SOFT_RSTN);
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mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN);
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mmio_write_32(UP_WAKE_HOST_MASK0, WDT_IRQ_EN);
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mmio_write_32(UP_WAKE_HOST_MASK1, MBOX0_IRQ_EN | MBOX1_IRQ_EN | MBOX2_IRQ_EN);
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spin_unlock(&apusys_rv_lock);
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return 0;
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}
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int apusys_kernel_apusys_rv_setup_boot(void)
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{
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static bool apusys_rv_setup_boot_called;
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spin_lock(&apusys_rv_lock);
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if (apusys_rv_setup_boot_called) {
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WARN(MODULE_TAG "%s: already initialized\n", __func__);
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spin_unlock(&apusys_rv_lock);
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return -1;
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}
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apusys_rv_setup_boot_called = true;
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mmio_write_32(MD32_BOOT_CTRL, APU_SEC_FW_IOVA);
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mmio_write_32(MD32_PRE_DEFINE, (PREDEFINE_CACHE_TCM << PREDEF_1G_OFS) |
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(PREDEFINE_CACHE << PREDEF_2G_OFS) | (PREDEFINE_CACHE << PREDEF_3G_OFS) |
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(PREDEFINE_CACHE << PREDEF_4G_OFS));
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spin_unlock(&apusys_rv_lock);
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return 0;
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}
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int apusys_kernel_apusys_rv_start_mp(void)
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{
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static bool apusys_rv_start_mp_called;
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spin_lock(&apusys_rv_lock);
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if (apusys_rv_start_mp_called) {
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WARN(MODULE_TAG "%s: already initialized\n", __func__);
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spin_unlock(&apusys_rv_lock);
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return -1;
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}
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apusys_rv_start_mp_called = true;
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mmio_write_32(MD32_RUNSTALL, MD32_RUN);
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spin_unlock(&apusys_rv_lock);
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return 0;
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}
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static bool watch_dog_is_timeout(void)
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{
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if (mmio_read_32(WDT_INT) != WDT_INT_W1C) {
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ERROR(MODULE_TAG "%s: WDT does not timeout\n", __func__);
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return false;
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}
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return true;
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}
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int apusys_kernel_apusys_rv_stop_mp(void)
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{
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static bool apusys_rv_stop_mp_called;
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spin_lock(&apusys_rv_lock);
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if (apusys_rv_stop_mp_called) {
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WARN(MODULE_TAG "%s: already initialized\n", __func__);
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spin_unlock(&apusys_rv_lock);
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return -1;
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}
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if (watch_dog_is_timeout() == false) {
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spin_unlock(&apusys_rv_lock);
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return -1;
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}
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apusys_rv_stop_mp_called = true;
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mmio_write_32(MD32_RUNSTALL, MD32_STALL);
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spin_unlock(&apusys_rv_lock);
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return 0;
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}
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@ -9,17 +9,87 @@
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#include <platform_def.h>
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#define APU_SEC_FW_IOVA (0x200000UL)
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/* APU_SCTRL_REVISER */
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#define UP_NORMAL_DOMAIN_NS (APU_REVISER + 0x0000)
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#define UP_PRI_DOMAIN_NS (APU_REVISER + 0x0004)
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#define UP_IOMMU_CTRL (APU_REVISER + 0x0008)
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#define UP_CORE0_VABASE0 (APU_REVISER + 0x000c)
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#define UP_CORE0_MVABASE0 (APU_REVISER + 0x0010)
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#define UP_CORE0_VABASE1 (APU_REVISER + 0x0014)
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#define UP_CORE0_MVABASE1 (APU_REVISER + 0x0018)
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#define USERFW_CTXT (APU_REVISER + 0x1000)
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#define SECUREFW_CTXT (APU_REVISER + 0x1004)
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#define UP_NORMAL_DOMAIN (7)
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#define UP_NORMAL_NS (1)
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#define UP_PRI_DOMAIN (5)
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#define UP_PRI_NS (1)
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#define UP_DOMAIN_SHIFT (0)
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#define UP_NS_SHIFT (4)
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#define MMU_EN BIT(0)
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#define MMU_CTRL BIT(1)
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#define MMU_CTRL_LOCK BIT(2)
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#define VLD BIT(0)
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#define PARTIAL_ENABLE BIT(1)
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#define THREAD_NUM_PRI (1)
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#define THREAD_NUM_NORMAL (0)
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#define THREAD_NUM_SHIFT (2)
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#define VASIZE_1MB BIT(0)
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#define CFG_4GB_SEL_EN BIT(2)
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#define CFG_4GB_SEL (0)
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#define MVA_34BIT_SHIFT (2)
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/* APU_MD32_SYSCTRL */
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#define MD32_SYS_CTRL (APU_MD32_SYSCTRL + 0x0000)
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#define MD32_CLK_CTRL (APU_MD32_SYSCTRL + 0x00b8)
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#define UP_WAKE_HOST_MASK0 (APU_MD32_SYSCTRL + 0x00bc)
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#define UP_WAKE_HOST_MASK1 (APU_MD32_SYSCTRL + 0x00c0)
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#define MD32_SYS_CTRL_RST (0)
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#define MD32_G2B_CG_EN BIT(11)
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#define MD32_DBG_EN BIT(10)
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#define MD32_DM_AWUSER_IOMMU_EN BIT(9)
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#define MD32_DM_ARUSER_IOMMU_EN BIT(7)
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#define MD32_PM_AWUSER_IOMMU_EN BIT(5)
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#define MD32_PM_ARUSER_IOMMU_EN BIT(3)
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#define MD32_SOFT_RSTN BIT(0)
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#define MD32_CLK_EN (1)
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#define WDT_IRQ_EN BIT(0)
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#define MBOX0_IRQ_EN BIT(21)
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#define MBOX1_IRQ_EN BIT(22)
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#define MBOX2_IRQ_EN BIT(23)
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#define RESET_DEALY_US (10)
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/* APU_AO_CTRL */
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#define MD32_PRE_DEFINE (APU_AO_CTRL + 0x0000)
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#define MD32_BOOT_CTRL (APU_AO_CTRL + 0x0004)
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#define MD32_RUNSTALL (APU_AO_CTRL + 0x0008)
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#define PREDEFINE_NON_CACHE (0)
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#define PREDEFINE_TCM (1)
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#define PREDEFINE_CACHE (2)
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#define PREDEFINE_CACHE_TCM (3)
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#define PREDEF_1G_OFS (0)
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#define PREDEF_2G_OFS (2)
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#define PREDEF_3G_OFS (4)
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#define PREDEF_4G_OFS (6)
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#define MD32_RUN (0)
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#define MD32_STALL (1)
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/* APU_MD32_WDT */
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#define WDT_INT (APU_MD32_WDT + 0x0)
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#define WDT_INT_W1C (1)
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/* APU MBOX */
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#define MBOX_FUNC_CFG (0xb0)
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#define MBOX_DOMAIN_CFG (0xe0)
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#define MBOX_CTRL_LOCK BIT(0)
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#define MBOX_NO_MPU_SHIFT (16)
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#define MBOX_RX_NS_SHIFT (16)
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#define MBOX_RX_DOMAIN_SHIFT (17)
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#define MBOX_TX_NS_SHIFT (24)
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#define MBOX_TX_DOMAIN_SHIFT (25)
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#define MBOX_SIZE (0x100)
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#define MBOX_NUM (8)
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#define MBOX_FUNC_CFG (0xb0)
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#define MBOX_DOMAIN_CFG (0xe0)
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#define MBOX_CTRL_LOCK BIT(0)
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#define MBOX_NO_MPU_SHIFT (16)
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#define MBOX_RX_NS_SHIFT (16)
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#define MBOX_RX_DOMAIN_SHIFT (17)
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#define MBOX_TX_NS_SHIFT (24)
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#define MBOX_TX_DOMAIN_SHIFT (25)
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#define MBOX_SIZE (0x100)
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#define MBOX_NUM (8)
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#define APU_MBOX(i) (((i) < MBOX_NUM) ? (APU_MBOX0 + MBOX_SIZE * (i)) : \
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(APU_MBOX1 + MBOX_SIZE * ((i) - MBOX_NUM)))
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@ -27,5 +97,10 @@
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#define APU_MBOX_DOMAIN_CFG(i) (APU_MBOX(i) + MBOX_DOMAIN_CFG)
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void apusys_rv_mbox_mpu_init(void);
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int apusys_kernel_apusys_rv_setup_reviser(void);
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int apusys_kernel_apusys_rv_reset_mp(void);
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int apusys_kernel_apusys_rv_setup_boot(void);
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int apusys_kernel_apusys_rv_start_mp(void);
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int apusys_kernel_apusys_rv_stop_mp(void);
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#endif /* APUSYS_RV_H */
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@ -28,7 +28,10 @@
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* APUSYS related constants
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******************************************************************************/
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#define BCRM_FMEM_PDN_BASE (IO_PHYS + 0x00276000)
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#define APU_MD32_SYSCTRL (IO_PHYS + 0x09001000)
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#define APU_MD32_WDT (IO_PHYS + 0x09002000)
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#define APU_RCX_CONFIG (IO_PHYS + 0x09020000)
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#define APU_REVISER (IO_PHYS + 0x0903c000)
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#define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090e0000)
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#define APU_MBOX0 (IO_PHYS + 0x090e1000)
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#define APU_MBOX1 (IO_PHYS + 0x090e2000)
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