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Merge changes from topic "st-fixes" into integration

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* changes:
  fix(spi-nand): add Quad Enable management
  fix(st-clock): disabling CKPER clock is not functional on stm32mp13
  fix(st-uart): skip console flush if UART is disabled
  fix(st): flush UART at the end of uart_read()
  fix(stm32mp1): use the BSEC nodes compatible for stm32mp13
  fix(stm32mp13-fdts): correct the BSEC nodes compatible
  fix(stm32mp1-fdts): move /omit-if-no-ref/ to overlay files
  fix(stm32mp1): properly check PSCI functions return
This commit is contained in:
Madhukar Pappireddy 2023-06-06 16:03:38 +02:00 • committed by TrustedFirmware Code Review
commit 1d64109ece
13 changed files with 130 additions and 54 deletions

5
drivers/mtd/nand/spi_nand.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
* Copyright (c) 2019-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,7 +17,6 @@
#define SPI_NAND_MAX_ID_LEN 4U
#define DELAY_US_400MS 400000U
#define MACRONIX_ID 0xC2U
static struct spinand_device spinand_dev;
@ -91,7 +90,7 @@ static int spi_nand_quad_enable(uint8_t manufacturer_id)
{
bool enable = false;
if (manufacturer_id != MACRONIX_ID) {
if ((spinand_dev.flags & SPI_NAND_HAS_QE_BIT) == 0U) {
return 0;
}

4
drivers/st/clk/clk-stm32mp13.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
* Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@ -1216,7 +1216,7 @@ static int stm32_clk_source_configure(struct stm32_clk_priv *priv)
* => deactivate CKPER only after switching clock
*/
if (ckper_disabled) {
ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED & CMD_MASK);
ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED);
if (ret != 0) {
return ret;
}

7
drivers/st/uart/aarch32/stm32_console.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -234,11 +234,16 @@ func console_stm32_core_flush
cmp r0, #0
ASM_ASSERT(ne)
#endif /* ENABLE_ASSERTIONS */
/* Skip flush if UART is not enabled */
ldr r1, [r0, #USART_CR1]
ands r1, r1, #USART_CR1_UE
beq 1f
/* Check Transmit Data Register Empty */
txe_loop_3:
ldr r1, [r0, #USART_ISR]
tst r1, #USART_ISR_TXE
beq txe_loop_3
1:
bx lr
endfunc console_stm32_core_flush

9
fdts/stm32mp13-bl2.dtsi
View file

@ -3,6 +3,15 @@
* Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved
*/
/omit-if-no-ref/ &i2c4_pins_a;
/omit-if-no-ref/ &sdmmc1_b4_pins_a;
/omit-if-no-ref/ &sdmmc1_clk_pins_a;
/omit-if-no-ref/ &sdmmc2_b4_pins_a;
/omit-if-no-ref/ &sdmmc2_clk_pins_a;
/omit-if-no-ref/ &uart4_pins_a;
/omit-if-no-ref/ &uart8_pins_a;
/omit-if-no-ref/ &usart1_pins_a;
/ {
aliases {
#if !STM32MP_EMMC && !STM32MP_SDMMC

16
fdts/stm32mp13-pinctrl.dtsi
View file

@ -6,7 +6,7 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
/omit-if-no-ref/ i2c4_pins_a: i2c4-0 {
i2c4_pins_a: i2c4-0 {
pins {
pinmux = <STM32_PINMUX('E', 15, AF6)>, /* I2C4_SCL */
<STM32_PINMUX('B', 9, AF6)>; /* I2C4_SDA */
@ -16,7 +16,7 @@
};
};
/omit-if-no-ref/ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
@ -29,7 +29,7 @@
};
};
/omit-if-no-ref/ sdmmc1_clk_pins_a: sdmmc1-clk-0 {
sdmmc1_clk_pins_a: sdmmc1-clk-0 {
pins {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
slew-rate = <1>;
@ -38,7 +38,7 @@
};
};
/omit-if-no-ref/ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
@ -51,7 +51,7 @@
};
};
/omit-if-no-ref/ sdmmc2_clk_pins_a: sdmmc2-clk-0 {
sdmmc2_clk_pins_a: sdmmc2-clk-0 {
pins {
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
slew-rate = <1>;
@ -60,7 +60,7 @@
};
};
/omit-if-no-ref/ uart4_pins_a: uart4-0 {
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
bias-disable;
@ -73,7 +73,7 @@
};
};
/omit-if-no-ref/ usart1_pins_a: usart1-0 {
usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
<STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
@ -88,7 +88,7 @@
};
};
/omit-if-no-ref/ uart8_pins_a: uart8-0 {
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
bias-disable;

2
fdts/stm32mp131.dtsi
View file

@ -416,7 +416,7 @@
};
bsec: efuse@5c005000 {
compatible = "st,stm32mp15-bsec";
compatible = "st,stm32mp13-bsec";
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;

29
fdts/stm32mp15-bl2.dtsi
View file

@ -3,8 +3,37 @@
* Copyright (c) 2020-2023, STMicroelectronics - All Rights Reserved
*/
/omit-if-no-ref/ &fmc_pins_a;
/omit-if-no-ref/ &i2c2_pins_a;
/omit-if-no-ref/ &i2c4_pins_a;
/omit-if-no-ref/ &i2c6;
/omit-if-no-ref/ &qspi_bk1_pins_a;
/omit-if-no-ref/ &qspi_bk2_pins_a;
/omit-if-no-ref/ &qspi_clk_pins_a;
/omit-if-no-ref/ &sdmmc1_b4_pins_a;
/omit-if-no-ref/ &sdmmc1_dir_pins_a;
/omit-if-no-ref/ &sdmmc1_dir_pins_b;
/omit-if-no-ref/ &sdmmc2_b4_pins_a;
/omit-if-no-ref/ &sdmmc2_b4_pins_b;
/omit-if-no-ref/ &sdmmc2_d47_pins_a;
/omit-if-no-ref/ &sdmmc2_d47_pins_b;
/omit-if-no-ref/ &sdmmc2_d47_pins_c;
/omit-if-no-ref/ &sdmmc2_d47_pins_d;
/omit-if-no-ref/ &spi6;
/omit-if-no-ref/ &uart4_pins_a;
/omit-if-no-ref/ &uart4_pins_b;
/omit-if-no-ref/ &uart7_pins_a;
/omit-if-no-ref/ &uart7_pins_b;
/omit-if-no-ref/ &uart7_pins_c;
/omit-if-no-ref/ &uart8_pins_a;
/omit-if-no-ref/ &usart2_pins_a;
/omit-if-no-ref/ &usart2_pins_b;
/omit-if-no-ref/ &usart2_pins_c;
/omit-if-no-ref/ &usart3_pins_a;
/omit-if-no-ref/ &usart3_pins_b;
/omit-if-no-ref/ &usart3_pins_c;
/omit-if-no-ref/ &usbotg_fs_dp_dm_pins_a;
/omit-if-no-ref/ &usbotg_hs_pins_a;
/ {
#if !STM32MP_EMMC && !STM32MP_SDMMC

29
fdts/stm32mp15-bl32.dtsi
View file

@ -3,8 +3,37 @@
* Copyright (c) 2020-2023, STMicroelectronics - All Rights Reserved
*/
/omit-if-no-ref/ &fmc_pins_a;
/omit-if-no-ref/ &i2c2_pins_a;
/omit-if-no-ref/ &i2c4_pins_a;
/omit-if-no-ref/ &i2c6;
/omit-if-no-ref/ &qspi_bk1_pins_a;
/omit-if-no-ref/ &qspi_bk2_pins_a;
/omit-if-no-ref/ &qspi_clk_pins_a;
/omit-if-no-ref/ &sdmmc1_b4_pins_a;
/omit-if-no-ref/ &sdmmc1_dir_pins_a;
/omit-if-no-ref/ &sdmmc1_dir_pins_b;
/omit-if-no-ref/ &sdmmc2_b4_pins_a;
/omit-if-no-ref/ &sdmmc2_b4_pins_b;
/omit-if-no-ref/ &sdmmc2_d47_pins_a;
/omit-if-no-ref/ &sdmmc2_d47_pins_b;
/omit-if-no-ref/ &sdmmc2_d47_pins_c;
/omit-if-no-ref/ &sdmmc2_d47_pins_d;
/omit-if-no-ref/ &spi6;
/omit-if-no-ref/ &uart4_pins_a;
/omit-if-no-ref/ &uart4_pins_b;
/omit-if-no-ref/ &uart7_pins_a;
/omit-if-no-ref/ &uart7_pins_b;
/omit-if-no-ref/ &uart7_pins_c;
/omit-if-no-ref/ &uart8_pins_a;
/omit-if-no-ref/ &usart2_pins_a;
/omit-if-no-ref/ &usart2_pins_b;
/omit-if-no-ref/ &usart2_pins_c;
/omit-if-no-ref/ &usart3_pins_a;
/omit-if-no-ref/ &usart3_pins_b;
/omit-if-no-ref/ &usart3_pins_c;
/omit-if-no-ref/ &usbotg_fs_dp_dm_pins_a;
/omit-if-no-ref/ &usbotg_hs_pins_a;
/ {
aliases {

58
fdts/stm32mp15-pinctrl.dtsi
View file

@ -6,7 +6,7 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
/omit-if-no-ref/ fmc_pins_a: fmc-0 {
fmc_pins_a: fmc-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
<STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
@ -31,7 +31,7 @@
};
};
/omit-if-no-ref/ i2c2_pins_a: i2c2-0 {
i2c2_pins_a: i2c2-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
<STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
@ -41,7 +41,7 @@
};
};
/omit-if-no-ref/ qspi_clk_pins_a: qspi-clk-0 {
qspi_clk_pins_a: qspi-clk-0 {
pins {
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
bias-disable;
@ -50,7 +50,7 @@
};
};
/omit-if-no-ref/ qspi_bk1_pins_a: qspi-bk1-0 {
qspi_bk1_pins_a: qspi-bk1-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
@ -68,7 +68,7 @@
};
};
/omit-if-no-ref/ qspi_bk2_pins_a: qspi-bk2-0 {
qspi_bk2_pins_a: qspi-bk2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
@ -86,7 +86,7 @@
};
};
/omit-if-no-ref/ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
@ -105,7 +105,7 @@
};
};
/omit-if-no-ref/ sdmmc1_dir_pins_a: sdmmc1-dir-0 {
sdmmc1_dir_pins_a: sdmmc1-dir-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
@ -120,7 +120,7 @@
};
};
/omit-if-no-ref/ sdmmc1_dir_pins_b: sdmmc1-dir-1 {
sdmmc1_dir_pins_b: sdmmc1-dir-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */
@ -135,7 +135,7 @@
};
};
/omit-if-no-ref/ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
@ -154,7 +154,7 @@
};
};
/omit-if-no-ref/ sdmmc2_b4_pins_b: sdmmc2-b4-1 {
sdmmc2_b4_pins_b: sdmmc2-b4-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
@ -173,7 +173,7 @@
};
};
/omit-if-no-ref/ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
sdmmc2_d47_pins_a: sdmmc2-d47-0 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
@ -185,7 +185,7 @@
};
};
/omit-if-no-ref/ sdmmc2_d47_pins_b: sdmmc2-d47-1 {
sdmmc2_d47_pins_b: sdmmc2-d47-1 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
@ -197,7 +197,7 @@
};
};
/omit-if-no-ref/ sdmmc2_d47_pins_c: sdmmc2-d47-2 {
sdmmc2_d47_pins_c: sdmmc2-d47-2 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
@ -209,7 +209,7 @@
};
};
/omit-if-no-ref/ sdmmc2_d47_pins_d: sdmmc2-d47-3 {
sdmmc2_d47_pins_d: sdmmc2-d47-3 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
@ -218,7 +218,7 @@
};
};
/omit-if-no-ref/ uart4_pins_a: uart4-0 {
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
bias-disable;
@ -231,7 +231,7 @@
};
};
/omit-if-no-ref/ uart4_pins_b: uart4-1 {
uart4_pins_b: uart4-1 {
pins1 {
pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
bias-disable;
@ -244,7 +244,7 @@
};
};
/omit-if-no-ref/ uart7_pins_a: uart7-0 {
uart7_pins_a: uart7-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
bias-disable;
@ -259,7 +259,7 @@
};
};
/omit-if-no-ref/ uart7_pins_b: uart7-1 {
uart7_pins_b: uart7-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
bias-disable;
@ -272,7 +272,7 @@
};
};
/omit-if-no-ref/ uart7_pins_c: uart7-2 {
uart7_pins_c: uart7-2 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
bias-disable;
@ -285,7 +285,7 @@
};
};
/omit-if-no-ref/ uart8_pins_a: uart8-0 {
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
bias-disable;
@ -298,7 +298,7 @@
};
};
/omit-if-no-ref/ usart2_pins_a: usart2-0 {
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
@ -313,7 +313,7 @@
};
};
/omit-if-no-ref/ usart2_pins_b: usart2-1 {
usart2_pins_b: usart2-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
@ -328,7 +328,7 @@
};
};
/omit-if-no-ref/ usart2_pins_c: usart2-2 {
usart2_pins_c: usart2-2 {
pins1 {
pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
@ -343,7 +343,7 @@
};
};
/omit-if-no-ref/ usart3_pins_a: usart3-0 {
usart3_pins_a: usart3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
bias-disable;
@ -356,7 +356,7 @@
};
};
/omit-if-no-ref/ usart3_pins_b: usart3-1 {
usart3_pins_b: usart3-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
@ -371,7 +371,7 @@
};
};
/omit-if-no-ref/ usart3_pins_c: usart3-2 {
usart3_pins_c: usart3-2 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
@ -386,13 +386,13 @@
};
};
/omit-if-no-ref/ usbotg_hs_pins_a: usbotg-hs-0 {
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
};
};
/omit-if-no-ref/ usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
pins {
pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
<STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
@ -401,7 +401,7 @@
};
&pinctrl_z {
/omit-if-no-ref/ i2c4_pins_a: i2c4-0 {
i2c4_pins_a: i2c4-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */

6
include/drivers/spi_nand.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2019-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -29,9 +29,13 @@
#define SPI_NAND_STATUS_BUSY BIT(0)
#define SPI_NAND_STATUS_ECC_UNCOR BIT(5)
/* Flags for specific configuration */
#define SPI_NAND_HAS_QE_BIT BIT(0)
struct spinand_device {
struct nand_device *nand_dev;
struct spi_mem_op spi_read_cache_op;
uint32_t flags;
uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */
};

4
plat/st/common/stm32cubeprogrammer_uart.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
* Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -481,6 +481,8 @@ static int uart_read(uint8_t id, uintptr_t buffer, size_t length)
}
}
stm32_uart_flush(&handle.uart);
return 0;
}

5
plat/st/stm32mp1/stm32mp1_def.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -647,11 +647,12 @@ static inline uintptr_t tamp_bkpr(uint32_t idx)
/*******************************************************************************
* Device Tree defines
******************************************************************************/
#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
#if STM32MP13
#define DT_BSEC_COMPAT "st,stm32mp13-bsec"
#define DT_DDR_COMPAT "st,stm32mp13-ddr"
#endif
#if STM32MP15
#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
#define DT_DDR_COMPAT "st,stm32mp1-ddr"
#endif
#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"

10
plat/st/stm32mp1/stm32mp1_pm.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -161,17 +161,15 @@ static void __dead2 stm32_system_reset(void)
static int stm32_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state)
{
int pstate = psci_get_pstate_type(power_state);
if (pstate != 0) {
if (psci_get_pstate_type(power_state) != 0U) {
return PSCI_E_INVALID_PARAMS;
}
if (psci_get_pstate_pwrlvl(power_state)) {
if (psci_get_pstate_pwrlvl(power_state) != 0U) {
return PSCI_E_INVALID_PARAMS;
}
if (psci_get_pstate_id(power_state)) {
if (psci_get_pstate_id(power_state) != 0U) {
return PSCI_E_INVALID_PARAMS;
}