mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-07 21:33:54 +00:00
Merge changes from topic "bk/clearups" into integration
* changes: chore(rme): add make rule for SPD=spmd chore(bl1): remove redundant bl1_arch_next_el_setup chore(docs): remove control register setup section chore(pauth): remove redundant pauth_disable_el3() call
This commit is contained in:
Olivier Deprez
TrustedFirmware Code Review
commit
ab23061eb0
7 changed files with 6 additions and 100 deletions
5
Makefile
5
Makefile
|
|
@ -646,6 +646,11 @@ endif
|
|||
ifeq ($(SPMC_AT_EL3),1)
|
||||
$(error SPMC_AT_EL3 and ENABLE_RME cannot both be enabled.)
|
||||
endif
|
||||
ifneq (${SPD}, none)
|
||||
ifneq (${SPD}, spmd)
|
||||
$(error ENABLE_RME is incompatible with SPD=${SPD}. Use SPD=spmd)
|
||||
endif
|
||||
endif
|
||||
include services/std_svc/rmmd/rmmd.mk
|
||||
$(warning "RME is an experimental feature")
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -17,19 +17,3 @@ void bl1_arch_setup(void)
|
|||
/* Set the next EL to be AArch64 */
|
||||
write_scr_el3(read_scr_el3() | SCR_RW_BIT);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Set the Secure EL1 required architectural state
|
||||
******************************************************************************/
|
||||
void bl1_arch_next_el_setup(void)
|
||||
{
|
||||
u_register_t next_sctlr;
|
||||
|
||||
/* Use the same endianness than the current BL */
|
||||
next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT);
|
||||
|
||||
/* Set SCTLR Secure EL1 */
|
||||
next_sctlr |= SCTLR_EL1_RES1;
|
||||
|
||||
write_sctlr_el1(next_sctlr);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,7 +17,6 @@ extern entry_point_info_t *bl2_ep_info;
|
|||
* Function prototypes
|
||||
*****************************************/
|
||||
void bl1_arch_setup(void);
|
||||
void bl1_arch_next_el_setup(void);
|
||||
|
||||
void bl1_prepare_next_image(unsigned int image_id);
|
||||
void bl1_run_bl2_in_root(void);
|
||||
|
|
|
|||
|
|
@ -24,15 +24,6 @@ func bl2_run_next_image
|
|||
tlbi alle3
|
||||
bl bl2_el3_plat_prepare_exit
|
||||
|
||||
#if ENABLE_PAUTH
|
||||
/* ---------------------------------------------
|
||||
* Disable pointer authentication before jumping
|
||||
* to next boot image.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl pauth_disable_el3
|
||||
#endif /* ENABLE_PAUTH */
|
||||
|
||||
ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
|
||||
msr elr_el3, x0
|
||||
msr spsr_el3, x1
|
||||
|
|
|
|||
|
|
@ -245,63 +245,6 @@ BL1 performs minimal architectural initialization as follows.
|
|||
specific reset handler function (see the section: "CPU specific operations
|
||||
framework").
|
||||
|
||||
- Control register setup (for AArch64)
|
||||
|
||||
- ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I``
|
||||
bit. Alignment and stack alignment checking is enabled by setting the
|
||||
``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to
|
||||
little-endian by clearing the ``SCTLR_EL3.EE`` bit.
|
||||
|
||||
- ``SCR_EL3``. The register width of the next lower exception level is set
|
||||
to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap
|
||||
both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
|
||||
also set to disable instruction fetches from Non-secure memory when in
|
||||
secure state.
|
||||
|
||||
- ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the
|
||||
``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by
|
||||
clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is
|
||||
configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit.
|
||||
Instructions that access the registers associated with Floating Point
|
||||
and Advanced SIMD execution are configured to not trap to EL3 by
|
||||
clearing the ``CPTR_EL3.TFP`` bit.
|
||||
|
||||
- ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt
|
||||
mask bit.
|
||||
|
||||
- ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and
|
||||
``MDCR_EL3.TPM``, are set so that accesses to the registers they control
|
||||
do not trap to EL3. AArch64 Secure self-hosted debug is disabled by
|
||||
setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to
|
||||
disable AArch32 Secure self-hosted privileged debug from S-EL1.
|
||||
|
||||
- Control register setup (for AArch32)
|
||||
|
||||
- ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit.
|
||||
Alignment checking is enabled by setting the ``SCTLR.A`` bit.
|
||||
Exception endianness is set to little-endian by clearing the
|
||||
``SCTLR.EE`` bit.
|
||||
|
||||
- ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from
|
||||
Non-secure memory when in secure state.
|
||||
|
||||
- ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1,
|
||||
by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality
|
||||
is configured not to trap to undefined mode by clearing the
|
||||
``CPACR.TRCDIS`` bit.
|
||||
|
||||
- ``NSACR``. Enable non-secure access to Advanced SIMD functionality and
|
||||
system register access to implemented trace registers.
|
||||
|
||||
- ``FPEXC``. Enable access to the Advanced SIMD and floating-point
|
||||
functionality from all Exception levels.
|
||||
|
||||
- ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing
|
||||
the Asynchronous data abort interrupt mask bit.
|
||||
|
||||
- ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure
|
||||
self-hosted privileged debug.
|
||||
|
||||
Platform initialization
|
||||
^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ func pauth_init_enable_el1
|
|||
endfunc pauth_init_enable_el1
|
||||
|
||||
/* -------------------------------------------------------------
|
||||
* Disable pointer authentication in EL3
|
||||
* Disable pointer authentication in EL1
|
||||
* -------------------------------------------------------------
|
||||
*/
|
||||
func pauth_disable_el1
|
||||
|
|
|
|||
|
|
@ -17,19 +17,3 @@ void bl1_arch_setup(void)
|
|||
{
|
||||
/* v8-R64 does not include SCRs. */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Set the Secure EL1 required architectural state
|
||||
******************************************************************************/
|
||||
void bl1_arch_next_el_setup(void)
|
||||
{
|
||||
u_register_t next_sctlr;
|
||||
|
||||
/* Use the same endianness than the current BL */
|
||||
next_sctlr = (read_sctlr_el2() & SCTLR_EE_BIT);
|
||||
|
||||
/* Set SCTLR Secure EL1 */
|
||||
next_sctlr |= SCTLR_EL1_RES1;
|
||||
|
||||
write_sctlr_el1(next_sctlr);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue