Corrected the comment for the size of NRD_CSS_DRAM1_CARVEOUT_SIZE
(0x0C000000) from 117MB to 192MB
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I289d37f50e70b936f717d4579d73882fac28ee95
Extend board detection with saving information about PS,
PMC and RTL versions. Variables can be use to cover
different behavior based on version and version
information is also printed for chip identification.
Change-Id: Ia37418f6a31426a5763fb89fc76fef91d09df155
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
EXTLLC bit in CPUECTLR_EL1(for non-gelas cpus) and in CPUECTLR2_EL1
register for gelas cpu enables external Last-level cache in the system,
External LLC is present on TC4 systems in MCN but it is not enabled in
CPU registers so enable it.
On TC4, Gelas vs Non-Gelas CPUs have different bits to enable EXTLLC
so take care of that as well.
Change-Id: Ic6a74b4af110a3c34d19131676e51901ea2bf6e3
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
This patch adds the routing table addresses required for LCA
enablement on RD-N2-Cfg2. CMN on RD-N2-Cfg2 uses AXI Stream IDs
to route LCA connections to the correct downstream tx_cxs_a4s
port. The data programmed in the routing table are the A4S IDs
of each chip.
Change-Id: I46e558f3be7f0d51b768b7c5586f15e6bc517f3a
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>
This patch adds the routing table addresses required for LCA
enablement on RD-V3-Cfg2. Since LCA connection on rdv3 uses ACE5L
instead of A4S, the addresses programmed in the routing table is
the address of memory mapped HNI with chip offset.
Change-Id: Ic235983d63e8ab3492ae566b68841d0659724e45
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>
This patch adds support for Local Chip Addressing (LCA). In a multi-chip
system, enablig LCA allows each GIC Distributor to maintain its own
version of routing table. This feature is activated when the
GICD_CFGID.LCA bit is set to 1.
The existing `gic600_multichip_data` data structure did not account for
the LCA feature. To support LCA:
- `rt_owner_base` is replaced by `base_addrs[]`. This is required
because each GICD in the system needs to be configured independently,
and their base addresses must be passed to the driver.
- `chip_addrs` is changed from 1D to 2D array to store the routing table
for each chip's GICD. The entries in `chip_addrs` are configuration
dependent, as the GIC specification does not enforce this.
On a multi-chip platform with chip count N where LCA is enabled by
default, the `gic600_multichip_data` structure should contain all copies
of the routing table (N*N entries). On platforms where LCA is not
supported, only the first sub-array with N entries is required. The
function signature of `gic600_multichip_init` remains unchanged, but if
the LCA feature is enabled, the driver will expect the routing table
configuration in the described format.
Change-Id: I8830c2cf90db6a0cae78e99914cd32c637284a2b
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>
* changes:
fix(versal2): modify function to have single return
fix(versal-net): modify function to have single return
fix(versal): modify function to have single return
fix(xilinx): modify function to have single return
fix(zynqmp): modify function to have single return
fix(versal-net): add unsigned suffix to match data type
fix(versal): add unsigned suffix to match data type
fix(versal2): add missing curly braces
fix(versal-net): add missing curly braces
fix(zynqmp): add missing curly braces
- VCORE DVFS is the feature to change VCORE/DDR Freq for power saving
- When there are no requests for using Vcore/DRAM, Vcore DVFS will
- lower the voltage and frequency of Vcore/DRAM to achieve power saving.
Signed-off-by: Kunlong Wang <kunlong.wang@mediatek.com>
Change-Id: I1126311e8b3943cc54fb13e15973b9e1b74c129e
LPM means low power module, it will connect idle and SPM to achieve
lower power consumption in some scenarios, and this patch is LPM
second version
Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.corp-partner.google.com>
Change-Id: I6ae5b5b4c2056d08c29efab5116be3a92351d8f1
This patch provides common APIs for communication with other subsystems
as well as common APIs for collecting the clock and power status of
each subsystem.
Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: I1b907256f53578a58d74d66beec7140edf41f687
This patch mainly initializes the SPM and provides common APIs for SPM
to enable the use of its various features.
Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: I9facb6bf9962bb2d5fcacd945846bfaeb4c87a55
This patch mainly collects and organizes SPM state information to
facilitate debugging when issues arise.
Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: Ie51cffeb1d683d65d88701fc63c426b20b22492f
When the system is in idle or suspend state, SPM will turn off some
unused system resources. This patch enables this feature to achieve
power saving.
Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: Ia9764b91073c4765d41fe7fcd8e4a21372c290f1
During suspend, it is necessary to set some power rails of the PMIC
to enter low power mode to achieve power saving.
Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: Iaeadd15270e0209f027fab80f478ad621bd59ea7
This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.
Change-Id: Ib152831e84f5ead5b57fd713ebfedb1f3340a727
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.
Change-Id: Ib8b3339f32031a3657f6c349763a20a99fd828e7
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.
Change-Id: Iffbd8770fd4ff2f2176062469d22961cbaa160b4
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.
Change-Id: Ice3eb939664ffc62c1f586b641e37481f10ffff6
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
Add MCDI driver to manage CPU idle states and optimize power consumption.
Signed-off-by: Kai Liang <kai.liang@mediatek.com>
Change-Id: I3a2e163730dd997dd72f2ebc1375dea38d728cb7
And mcusys drivers to enhance CPU power state control.
Signed-off-by: Kai Liang <kai.liang@mediatek.com>
Change-Id: I7d84407cebc16a5ab23359781574e9d02e90c58b
Add Centralized Power Control (CPC) module to manage CPU power states.
Signed-off-by: Kai Liang <kai.liang@mediatek.com>
Change-Id: I212155143018141c89427032f6a7d21243e750b7
Add topology module to support CPU power state control.
Signed-off-by: Kai Liang <kai.liang@mediatek.com>
Change-Id: I0cc1e5a426762b1b29bff1e940e077643da02e5e
Add SPMI and PMIF driver for PMIC communication
Change-Id: Iad1d90381d6dad6b3e92fd9d6a3ce02fa11d15f1
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
The commit a6485b2b3b ("refactor(delay-timer): add timer
callback functions") is breaking DCC console due to uninitialized
timer ops structure. Fix it by moving generic delay timer init
prior to console setup to make sure that time is setup before DCC
console setup.
Fixes: a6485b2b3b ("refactor(delay-timer): add timer callback
functions")
Change-Id: I67910332773741c0b08f02feb232efab6356db12
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
Move console_switch_state(CONSOLE_FLAG_RUNTIME) to sp_min_main() so
that this becomes the last call before bl32/sp_min exits. This also
ensures that console_flush() is called before switching console state
to runtime.
This patch mimics the behavior of console_switch_state() call in BL31
per this patch
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/26771/4.
Change-Id: I5b562d02706b19bb8b14154be97b6e9ef4e2fd3b
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
* changes:
perf(psci): pass my_core_pos around instead of calling it repeatedly
refactor(psci): move timestamp collection to psci_pwrdown_cpu
refactor(psci): factor common code out of the standby finisher
refactor(psci): don't use PSCI_INVALID_PWR_LVL to signal OFF state
docs(psci): drop outdated cache maintenance comment
This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.
Change-Id: Ibff3df16b4c591384467771bc7cb316f1773f1ea
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
Update DDR address map of BL32, BL33 and transfer list to support
AMD Versal Gen 2 platform's new memory map.
Change-Id: I757b2f67270034c8a3140e4bb0ac4d7e88b5d055
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
The build macro no longer coverts variable names to uppercase.
We need to convert it to uppercase to pass it on.
Change-Id: If808fc77bce71d575e2d43ff83c4d9bcdcc52326
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
FEAT_MOPS, mandatory from Arm v8.8, is typically managed in EL2.
However, in configurations where NS_EL2 is not enabled,
EL3 must set the HCRX_EL2.MSCEn bit to 1 to enable the feature.
This patch ensures FEAT_MOPS is enabled by setting HCRX_EL2.MSCEn to 1.
Change-Id: Ic4960e0cc14a44279156b79ded50de475b3b21c5
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
For a couple of releases now we have officially withdrawn support for
building TF-A on Windows using the native environment, relying instead
on POSIX emulation layers like MSYS2, Mingw64, Cygwin or WSL.
This change removes the remainder of the OS compatibility layer
entirely, and migrates the build system over to explicitly relying on a
POSIX environment.
Change-Id: I8fb60d998162422e958009afd17eab826e3bc39b
Signed-off-by: Chris Kay <chris.kay@arm.com>
Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.
Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Enable the MMU and add two entries to map the BL31 code and data
regions. Additional mappings will be added dynamically, enhancing
flexibility and modularity during the porting process.
Change-Id: I333c34c58274a115f62f54730bba5b71165e3e36
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Dynamically add entries for the GIC distributor and all its
redistributors for the cases when the platform is booted using enabled
MMU.
Change-Id: Ia810ec2329993057173e8fc25620a3df59b1e55d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Enable the MMU and add two entries to map the BL2 code and data regions.
Additional mappings will be added dynamically, enhancing flexibility and
modularity during the porting process.
Change-Id: I107abf944dfdce9dcff47b08272a5001484de8a9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Dynamically map the remaining regions part of the BL2 stages using
dynamic regions.
Change-Id: Ia81666920b941218ddaa7d3244dfa5212525c75d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The regions used by the stages loaded by BL2 must be mapped before they
can be used.
Change-Id: Ia70f8c5f35d7930e2b20f1a26be0ad2cdfea2b1a
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Increase the maximum number of regions allocated by the translation
table library to accommodate the entries added in the next commits.
Change-Id: Ib0dd2d0dbc9b4a574367141a7c96d76dd08e2c7f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
On some platforms plat_my_core_pos is a nontrivial function that takes a
bit of time and the compiler really doesn't like to inline. In the PSCI
library, at least, we have no need to keep repeatedly calling it and we
can instead pass it around as an argument. This saves on a lot of
redundant calls, speeding the library up a bit.
Change-Id: I137f69bea80d7cac90d7a20ffe98e1ba8d77246f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
