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feat(mt8196): add vcore dvfs drivers
- VCORE DVFS is the feature to change VCORE/DDR Freq for power saving - When there are no requests for using Vcore/DRAM, Vcore DVFS will - lower the voltage and frequency of Vcore/DRAM to achieve power saving. Signed-off-by: Kunlong Wang <kunlong.wang@mediatek.com> Change-Id: I1126311e8b3943cc54fb13e15973b9e1b74c129e
This commit is contained in:
Kunlong Wang
Wenzhen Yu
parent
da8cc41bc8
commit
f0dce79600
14 changed files with 2215 additions and 0 deletions
609
plat/mediatek/drivers/spm/mt8196/mt_spm_vcorefs.c
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609
plat/mediatek/drivers/spm/mt8196/mt_spm_vcorefs.c
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/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stddef.h>
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#include <stdio.h>
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#include <string.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <drivers/spmi_api.h>
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#include <lib/pm/mtk_pm.h>
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#include <mt_plat_spm_setting.h>
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#include <mt_spm.h>
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#include <mt_spm_internal.h>
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#include <mt_spm_reg.h>
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#include <pmic_wrap/inc/mt_spm_pmic_wrap.h>
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#define VCORE_BASE_UV 0
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#ifdef MT8196_VCORE_SUPPORT
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#define VCORE_STEP_UV 6250
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#else
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#define VCORE_STEP_UV 5000
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#endif
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#define VCORE_UV_TO_PMIC(uv) /* pmic >= uv */ \
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((((uv) - VCORE_BASE_UV) + (VCORE_STEP_UV - 1)) / VCORE_STEP_UV)
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#define VCORE_PMIC_TO_UV(pmic) \
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(((pmic) * VCORE_STEP_UV) + VCORE_BASE_UV)
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#define VSRAM_BASE_UV 0
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#define VSRAM_STEP_UV 6250
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#define VSRAM_UV_TO_PMIC(uv) /* pmic >= uv */ \
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((((uv) - VSRAM_BASE_UV) + (VSRAM_STEP_UV - 1)) / VSRAM_STEP_UV)
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#define VSRAM_PMIC_TO_UV(pmic) \
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(((pmic) * VSRAM_STEP_UV) + VSRAM_BASE_UV)
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static int spm_dvfs_init_done;
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static struct pwr_ctrl vcorefs_ctrl = {
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.wake_src = R12_CPU_WAKEUP,
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/* default VCORE DVFS is disabled */
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.pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO |
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SPM_FLAG_DISABLE_VCORE_DVS |
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SPM_FLAG_DISABLE_DDR_DFS |
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SPM_FLAG_DISABLE_EMI_DFS | SPM_FLAG_DISABLE_BUS_DFS),
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/* SPM_SRC_REQ */
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.reg_spm_adsp_mailbox_req = 0,
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.reg_spm_apsrc_req = 0,
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.reg_spm_ddren_req = 0,
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.reg_spm_dvfs_req = 0,
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.reg_spm_emi_req = 0,
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.reg_spm_f26m_req = 0,
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.reg_spm_infra_req = 0,
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.reg_spm_pmic_req = 0,
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.reg_spm_scp_mailbox_req = 0,
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.reg_spm_sspm_mailbox_req = 0,
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.reg_spm_sw_mailbox_req = 0,
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.reg_spm_vcore_req = 1,
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.reg_spm_vrf18_req = 0,
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.adsp_mailbox_state = 0,
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.apsrc_state = 0,
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.ddren_state = 0,
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.dvfs_state = 0,
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.emi_state = 0,
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.f26m_state = 0,
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.infra_state = 0,
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.pmic_state = 0,
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.scp_mailbox_state = 0,
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.sspm_mailbox_state = 0,
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.sw_mailbox_state = 0,
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.vcore_state = 0,
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.vrf18_state = 0,
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/* SPM_SRC_MASK_0 */
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.reg_apifr_apsrc_rmb = 0,
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.reg_apifr_ddren_rmb = 0,
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.reg_apifr_emi_rmb = 0,
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.reg_apifr_infra_rmb = 0,
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.reg_apifr_pmic_rmb = 0,
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.reg_apifr_srcclkena_mb = 0,
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.reg_apifr_vcore_rmb = 0,
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.reg_apifr_vrf18_rmb = 0,
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.reg_apu_apsrc_rmb = 1,
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.reg_apu_ddren_rmb = 0,
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.reg_apu_emi_rmb = 1,
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.reg_apu_infra_rmb = 1,
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.reg_apu_pmic_rmb = 1,
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.reg_apu_srcclkena_mb = 1,
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.reg_apu_vcore_rmb = 1,
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.reg_apu_vrf18_rmb = 1,
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.reg_audio_apsrc_rmb = 1,
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.reg_audio_ddren_rmb = 0,
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.reg_audio_emi_rmb = 1,
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.reg_audio_infra_rmb = 1,
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.reg_audio_pmic_rmb = 1,
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.reg_audio_srcclkena_mb = 1,
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.reg_audio_vcore_rmb = 1,
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.reg_audio_vrf18_rmb = 1,
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/* SPM_SRC_MASK_1 */
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.reg_audio_dsp_apsrc_rmb = 1,
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.reg_audio_dsp_ddren_rmb = 0,
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.reg_audio_dsp_emi_rmb = 1,
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.reg_audio_dsp_infra_rmb = 1,
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.reg_audio_dsp_pmic_rmb = 1,
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.reg_audio_dsp_srcclkena_mb = 1,
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.reg_audio_dsp_vcore_rmb = 1,
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.reg_audio_dsp_vrf18_rmb = 1,
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.reg_cam_apsrc_rmb = 0,
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.reg_cam_ddren_rmb = 0,
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.reg_cam_emi_rmb = 0,
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.reg_cam_infra_rmb = 0,
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.reg_cam_pmic_rmb = 0,
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.reg_cam_srcclkena_mb = 0,
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.reg_cam_vrf18_rmb = 0,
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.reg_ccif_apsrc_rmb = 0xfff,
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/* SPM_SRC_MASK_2 */
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.reg_ccif_emi_rmb = 0xfff,
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.reg_ccif_infra_rmb = 0xfff,
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/* SPM_SRC_MASK_3 */
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.reg_ccif_pmic_rmb = 0xfff,
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.reg_ccif_srcclkena_mb = 0xfff,
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/* SPM_SRC_MASK_4 */
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.reg_ccif_vcore_rmb = 0xfff,
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.reg_ccif_vrf18_rmb = 0xfff,
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.reg_ccu_apsrc_rmb = 0,
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.reg_ccu_ddren_rmb = 0,
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.reg_ccu_emi_rmb = 0,
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.reg_ccu_infra_rmb = 0,
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.reg_ccu_pmic_rmb = 0,
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.reg_ccu_srcclkena_mb = 0,
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.reg_ccu_vrf18_rmb = 0,
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.reg_cg_check_apsrc_rmb = 0,
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/* SPM_SRC_MASK_5 */
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.reg_cg_check_ddren_rmb = 0,
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.reg_cg_check_emi_rmb = 0,
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.reg_cg_check_infra_rmb = 0,
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.reg_cg_check_pmic_rmb = 0,
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.reg_cg_check_srcclkena_mb = 0,
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.reg_cg_check_vcore_rmb = 1,
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.reg_cg_check_vrf18_rmb = 0,
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.reg_cksys_apsrc_rmb = 1,
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.reg_cksys_ddren_rmb = 0,
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.reg_cksys_emi_rmb = 1,
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.reg_cksys_infra_rmb = 1,
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.reg_cksys_pmic_rmb = 1,
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.reg_cksys_srcclkena_mb = 1,
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.reg_cksys_vcore_rmb = 1,
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.reg_cksys_vrf18_rmb = 1,
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.reg_cksys_1_apsrc_rmb = 1,
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.reg_cksys_1_ddren_rmb = 0,
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.reg_cksys_1_emi_rmb = 1,
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.reg_cksys_1_infra_rmb = 1,
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.reg_cksys_1_pmic_rmb = 1,
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.reg_cksys_1_srcclkena_mb = 1,
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.reg_cksys_1_vcore_rmb = 1,
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.reg_cksys_1_vrf18_rmb = 1,
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/* SPM_SRC_MASK_6 */
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.reg_cksys_2_apsrc_rmb = 1,
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.reg_cksys_2_ddren_rmb = 0,
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.reg_cksys_2_emi_rmb = 1,
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.reg_cksys_2_infra_rmb = 1,
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.reg_cksys_2_pmic_rmb = 1,
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.reg_cksys_2_srcclkena_mb = 1,
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.reg_cksys_2_vcore_rmb = 1,
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.reg_cksys_2_vrf18_rmb = 1,
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.reg_conn_apsrc_rmb = 1,
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.reg_conn_ddren_rmb = 0,
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.reg_conn_emi_rmb = 1,
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.reg_conn_infra_rmb = 1,
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.reg_conn_pmic_rmb = 1,
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.reg_conn_srcclkena_mb = 1,
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.reg_conn_srcclkenb_mb = 1,
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.reg_conn_vcore_rmb = 1,
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.reg_conn_vrf18_rmb = 1,
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.reg_corecfg_apsrc_rmb = 0,
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.reg_corecfg_ddren_rmb = 0,
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.reg_corecfg_emi_rmb = 0,
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.reg_corecfg_infra_rmb = 0,
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.reg_corecfg_pmic_rmb = 0,
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.reg_corecfg_srcclkena_mb = 0,
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.reg_corecfg_vcore_rmb = 0,
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.reg_corecfg_vrf18_rmb = 0,
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/* SPM_SRC_MASK_7 */
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.reg_cpueb_apsrc_rmb = 1,
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.reg_cpueb_ddren_rmb = 0,
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.reg_cpueb_emi_rmb = 1,
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.reg_cpueb_infra_rmb = 1,
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.reg_cpueb_pmic_rmb = 1,
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.reg_cpueb_srcclkena_mb = 1,
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.reg_cpueb_vcore_rmb = 1,
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.reg_cpueb_vrf18_rmb = 1,
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.reg_disp0_apsrc_rmb = 0,
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.reg_disp0_ddren_rmb = 0,
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.reg_disp0_emi_rmb = 0,
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.reg_disp0_infra_rmb = 0,
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.reg_disp0_pmic_rmb = 0,
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.reg_disp0_srcclkena_mb = 0,
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.reg_disp0_vrf18_rmb = 0,
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.reg_disp1_apsrc_rmb = 0,
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.reg_disp1_ddren_rmb = 0,
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.reg_disp1_emi_rmb = 0,
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.reg_disp1_infra_rmb = 0,
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.reg_disp1_pmic_rmb = 0,
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.reg_disp1_srcclkena_mb = 0,
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.reg_disp1_vrf18_rmb = 0,
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.reg_dpm_apsrc_rmb = 0xf,
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.reg_dpm_ddren_rmb = 0xf,
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/* SPM_SRC_MASK_8 */
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.reg_dpm_emi_rmb = 0xf,
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.reg_dpm_infra_rmb = 0xf,
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.reg_dpm_pmic_rmb = 0xf,
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.reg_dpm_srcclkena_mb = 0xf,
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.reg_dpm_vcore_rmb = 0xf,
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.reg_dpm_vrf18_rmb = 0xf,
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.reg_dpmaif_apsrc_rmb = 1,
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.reg_dpmaif_ddren_rmb = 0,
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.reg_dpmaif_emi_rmb = 1,
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.reg_dpmaif_infra_rmb = 1,
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.reg_dpmaif_pmic_rmb = 1,
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.reg_dpmaif_srcclkena_mb = 1,
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.reg_dpmaif_vcore_rmb = 1,
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.reg_dpmaif_vrf18_rmb = 1,
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/* SPM_SRC_MASK_9 */
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.reg_dvfsrc_level_rmb = 1,
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.reg_emisys_apsrc_rmb = 0,
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.reg_emisys_ddren_rmb = 0,
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.reg_emisys_emi_rmb = 0,
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.reg_emisys_infra_rmb = 0,
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.reg_emisys_pmic_rmb = 0,
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.reg_emisys_srcclkena_mb = 0,
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.reg_emisys_vcore_rmb = 0,
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.reg_emisys_vrf18_rmb = 0,
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.reg_gce_apsrc_rmb = 0,
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.reg_gce_ddren_rmb = 0,
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.reg_gce_emi_rmb = 0,
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.reg_gce_infra_rmb = 0,
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.reg_gce_pmic_rmb = 0,
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.reg_gce_srcclkena_mb = 0,
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.reg_gce_vcore_rmb = 0,
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.reg_gce_vrf18_rmb = 0,
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.reg_gpueb_apsrc_rmb = 1,
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.reg_gpueb_ddren_rmb = 0,
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.reg_gpueb_emi_rmb = 1,
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.reg_gpueb_infra_rmb = 1,
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.reg_gpueb_pmic_rmb = 1,
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.reg_gpueb_srcclkena_mb = 1,
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.reg_gpueb_vcore_rmb = 1,
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.reg_gpueb_vrf18_rmb = 1,
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.reg_hwccf_apsrc_rmb = 1,
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.reg_hwccf_ddren_rmb = 0,
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.reg_hwccf_emi_rmb = 1,
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.reg_hwccf_infra_rmb = 1,
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.reg_hwccf_pmic_rmb = 1,
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.reg_hwccf_srcclkena_mb = 1,
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.reg_hwccf_vcore_rmb = 1,
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/* SPM_SRC_MASK_10 */
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.reg_hwccf_vrf18_rmb = 1,
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.reg_img_apsrc_rmb = 0,
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.reg_img_ddren_rmb = 0,
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.reg_img_emi_rmb = 0,
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.reg_img_infra_rmb = 0,
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.reg_img_pmic_rmb = 0,
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.reg_img_srcclkena_mb = 0,
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.reg_img_vrf18_rmb = 0,
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.reg_infrasys_apsrc_rmb = 0,
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.reg_infrasys_ddren_rmb = 0,
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.reg_infrasys_emi_rmb = 0,
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.reg_infrasys_infra_rmb = 0,
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.reg_infrasys_pmic_rmb = 0,
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.reg_infrasys_srcclkena_mb = 0,
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.reg_infrasys_vcore_rmb = 0,
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.reg_infrasys_vrf18_rmb = 0,
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.reg_ipic_infra_rmb = 1,
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.reg_ipic_vrf18_rmb = 1,
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.reg_mcu_apsrc_rmb = 1,
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.reg_mcu_ddren_rmb = 0,
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.reg_mcu_emi_rmb = 1,
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.reg_mcu_infra_rmb = 1,
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.reg_mcu_pmic_rmb = 1,
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.reg_mcu_srcclkena_mb = 1,
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.reg_mcu_vcore_rmb = 1,
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.reg_mcu_vrf18_rmb = 1,
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.reg_md_apsrc_rmb = 1,
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.reg_md_ddren_rmb = 0,
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.reg_md_emi_rmb = 1,
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.reg_md_infra_rmb = 1,
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.reg_md_pmic_rmb = 1,
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.reg_md_srcclkena_mb = 1,
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/* SPM_SRC_MASK_11 */
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.reg_md_srcclkena1_mb = 1,
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.reg_md_vcore_rmb = 1,
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.reg_md_vrf18_rmb = 1,
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.reg_mm_proc_apsrc_rmb = 1,
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.reg_mm_proc_ddren_rmb = 0,
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.reg_mm_proc_emi_rmb = 1,
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.reg_mm_proc_infra_rmb = 1,
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.reg_mm_proc_pmic_rmb = 1,
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.reg_mm_proc_srcclkena_mb = 1,
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.reg_mm_proc_vcore_rmb = 1,
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.reg_mm_proc_vrf18_rmb = 1,
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.reg_mml0_apsrc_rmb = 0,
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.reg_mml0_ddren_rmb = 0,
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.reg_mml0_emi_rmb = 0,
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.reg_mml0_infra_rmb = 0,
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.reg_mml0_pmic_rmb = 0,
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.reg_mml0_srcclkena_mb = 0,
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.reg_mml0_vrf18_rmb = 0,
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.reg_mml1_apsrc_rmb = 0,
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.reg_mml1_ddren_rmb = 0,
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.reg_mml1_emi_rmb = 0,
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.reg_mml1_infra_rmb = 0,
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.reg_mml1_pmic_rmb = 0,
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.reg_mml1_srcclkena_mb = 0,
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.reg_mml1_vrf18_rmb = 0,
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.reg_ovl0_apsrc_rmb = 0,
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.reg_ovl0_ddren_rmb = 0,
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.reg_ovl0_emi_rmb = 0,
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.reg_ovl0_infra_rmb = 0,
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.reg_ovl0_pmic_rmb = 0,
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.reg_ovl0_srcclkena_mb = 0,
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.reg_ovl0_vrf18_rmb = 0,
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/* SPM_SRC_MASK_12 */
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.reg_ovl1_apsrc_rmb = 0,
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.reg_ovl1_ddren_rmb = 0,
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.reg_ovl1_emi_rmb = 0,
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.reg_ovl1_infra_rmb = 0,
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.reg_ovl1_pmic_rmb = 0,
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.reg_ovl1_srcclkena_mb = 0,
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.reg_ovl1_vrf18_rmb = 0,
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.reg_pcie0_apsrc_rmb = 1,
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.reg_pcie0_ddren_rmb = 0,
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.reg_pcie0_emi_rmb = 1,
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.reg_pcie0_infra_rmb = 1,
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.reg_pcie0_pmic_rmb = 1,
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.reg_pcie0_srcclkena_mb = 1,
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.reg_pcie0_vcore_rmb = 1,
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.reg_pcie0_vrf18_rmb = 1,
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.reg_pcie1_apsrc_rmb = 1,
|
||||
.reg_pcie1_ddren_rmb = 0,
|
||||
.reg_pcie1_emi_rmb = 1,
|
||||
.reg_pcie1_infra_rmb = 1,
|
||||
.reg_pcie1_pmic_rmb = 1,
|
||||
.reg_pcie1_srcclkena_mb = 1,
|
||||
.reg_pcie1_vcore_rmb = 1,
|
||||
.reg_pcie1_vrf18_rmb = 1,
|
||||
.reg_perisys_apsrc_rmb = 1,
|
||||
.reg_perisys_ddren_rmb = 0,
|
||||
.reg_perisys_emi_rmb = 1,
|
||||
.reg_perisys_infra_rmb = 1,
|
||||
.reg_perisys_pmic_rmb = 1,
|
||||
.reg_perisys_srcclkena_mb = 1,
|
||||
.reg_perisys_vcore_rmb = 1,
|
||||
.reg_perisys_vrf18_rmb = 1,
|
||||
.reg_pmsr_apsrc_rmb = 1,
|
||||
|
||||
/* SPM_SRC_MASK_13 */
|
||||
.reg_pmsr_ddren_rmb = 0,
|
||||
.reg_pmsr_emi_rmb = 1,
|
||||
.reg_pmsr_infra_rmb = 1,
|
||||
.reg_pmsr_pmic_rmb = 1,
|
||||
.reg_pmsr_srcclkena_mb = 1,
|
||||
.reg_pmsr_vcore_rmb = 1,
|
||||
.reg_pmsr_vrf18_rmb = 1,
|
||||
.reg_scp_apsrc_rmb = 1,
|
||||
.reg_scp_ddren_rmb = 0,
|
||||
.reg_scp_emi_rmb = 1,
|
||||
.reg_scp_infra_rmb = 1,
|
||||
.reg_scp_pmic_rmb = 1,
|
||||
.reg_scp_srcclkena_mb = 1,
|
||||
.reg_scp_vcore_rmb = 1,
|
||||
.reg_scp_vrf18_rmb = 1,
|
||||
.reg_spu_hwr_apsrc_rmb = 1,
|
||||
.reg_spu_hwr_ddren_rmb = 0,
|
||||
.reg_spu_hwr_emi_rmb = 1,
|
||||
.reg_spu_hwr_infra_rmb = 1,
|
||||
.reg_spu_hwr_pmic_rmb = 1,
|
||||
.reg_spu_hwr_srcclkena_mb = 1,
|
||||
.reg_spu_hwr_vcore_rmb = 1,
|
||||
.reg_spu_hwr_vrf18_rmb = 1,
|
||||
.reg_spu_ise_apsrc_rmb = 1,
|
||||
.reg_spu_ise_ddren_rmb = 0,
|
||||
.reg_spu_ise_emi_rmb = 1,
|
||||
.reg_spu_ise_infra_rmb = 1,
|
||||
.reg_spu_ise_pmic_rmb = 1,
|
||||
.reg_spu_ise_srcclkena_mb = 1,
|
||||
.reg_spu_ise_vcore_rmb = 1,
|
||||
.reg_spu_ise_vrf18_rmb = 1,
|
||||
|
||||
/* SPM_SRC_MASK_14 */
|
||||
.reg_srcclkeni_infra_rmb = 0x3,
|
||||
.reg_srcclkeni_pmic_rmb = 0x3,
|
||||
.reg_srcclkeni_srcclkena_mb = 0x3,
|
||||
.reg_srcclkeni_vcore_rmb = 0x3,
|
||||
.reg_sspm_apsrc_rmb = 1,
|
||||
.reg_sspm_ddren_rmb = 0,
|
||||
.reg_sspm_emi_rmb = 1,
|
||||
.reg_sspm_infra_rmb = 1,
|
||||
.reg_sspm_pmic_rmb = 1,
|
||||
.reg_sspm_srcclkena_mb = 1,
|
||||
.reg_sspm_vrf18_rmb = 1,
|
||||
.reg_ssrsys_apsrc_rmb = 1,
|
||||
.reg_ssrsys_ddren_rmb = 0,
|
||||
.reg_ssrsys_emi_rmb = 1,
|
||||
.reg_ssrsys_infra_rmb = 1,
|
||||
.reg_ssrsys_pmic_rmb = 1,
|
||||
.reg_ssrsys_srcclkena_mb = 1,
|
||||
.reg_ssrsys_vcore_rmb = 1,
|
||||
.reg_ssrsys_vrf18_rmb = 1,
|
||||
.reg_ssusb_apsrc_rmb = 1,
|
||||
.reg_ssusb_ddren_rmb = 0,
|
||||
.reg_ssusb_emi_rmb = 1,
|
||||
.reg_ssusb_infra_rmb = 1,
|
||||
.reg_ssusb_pmic_rmb = 1,
|
||||
.reg_ssusb_srcclkena_mb = 1,
|
||||
.reg_ssusb_vcore_rmb = 1,
|
||||
.reg_ssusb_vrf18_rmb = 1,
|
||||
.reg_uart_hub_infra_rmb = 1,
|
||||
|
||||
/* SPM_SRC_MASK_15 */
|
||||
.reg_uart_hub_pmic_rmb = 1,
|
||||
.reg_uart_hub_srcclkena_mb = 1,
|
||||
.reg_uart_hub_vcore_rmb = 1,
|
||||
.reg_uart_hub_vrf18_rmb = 1,
|
||||
.reg_ufs_apsrc_rmb = 1,
|
||||
.reg_ufs_ddren_rmb = 0,
|
||||
.reg_ufs_emi_rmb = 1,
|
||||
.reg_ufs_infra_rmb = 1,
|
||||
.reg_ufs_pmic_rmb = 1,
|
||||
.reg_ufs_srcclkena_mb = 1,
|
||||
.reg_ufs_vcore_rmb = 1,
|
||||
.reg_ufs_vrf18_rmb = 1,
|
||||
.reg_vdec_apsrc_rmb = 0,
|
||||
.reg_vdec_ddren_rmb = 0,
|
||||
.reg_vdec_emi_rmb = 0,
|
||||
.reg_vdec_infra_rmb = 0,
|
||||
.reg_vdec_pmic_rmb = 0,
|
||||
.reg_vdec_srcclkena_mb = 0,
|
||||
.reg_vdec_vrf18_rmb = 0,
|
||||
.reg_venc_apsrc_rmb = 0,
|
||||
.reg_venc_ddren_rmb = 0,
|
||||
.reg_venc_emi_rmb = 0,
|
||||
.reg_venc_infra_rmb = 0,
|
||||
.reg_venc_pmic_rmb = 0,
|
||||
.reg_venc_srcclkena_mb = 0,
|
||||
.reg_venc_vrf18_rmb = 0,
|
||||
.reg_vlpcfg_apsrc_rmb = 1,
|
||||
.reg_vlpcfg_ddren_rmb = 0,
|
||||
.reg_vlpcfg_emi_rmb = 1,
|
||||
.reg_vlpcfg_infra_rmb = 1,
|
||||
.reg_vlpcfg_pmic_rmb = 1,
|
||||
.reg_vlpcfg_srcclkena_mb = 1,
|
||||
|
||||
/* SPM_SRC_MASK_16 */
|
||||
.reg_vlpcfg_vcore_rmb = 1,
|
||||
.reg_vlpcfg_vrf18_rmb = 1,
|
||||
.reg_vlpcfg1_apsrc_rmb = 1,
|
||||
.reg_vlpcfg1_ddren_rmb = 0,
|
||||
.reg_vlpcfg1_emi_rmb = 1,
|
||||
.reg_vlpcfg1_infra_rmb = 1,
|
||||
.reg_vlpcfg1_pmic_rmb = 1,
|
||||
.reg_vlpcfg1_srcclkena_mb = 1,
|
||||
.reg_vlpcfg1_vcore_rmb = 1,
|
||||
.reg_vlpcfg1_vrf18_rmb = 1,
|
||||
|
||||
/* SPM_EVENT_CON_MISC */
|
||||
.reg_srcclken_fast_resp = 0,
|
||||
.reg_csyspwrup_ack_mask = 1,
|
||||
|
||||
/* SPM_SRC_MASK_17 */
|
||||
/* SPM D7X WA for wakeup source */
|
||||
.reg_spm_sw_vcore_rmb = 0x3,
|
||||
.reg_spm_sw_pmic_rmb = 0,
|
||||
|
||||
/* SPM_SRC_MASK_18 */
|
||||
.reg_spm_sw_srcclkena_mb = 0,
|
||||
|
||||
/* SPM_WAKE_MASK*/
|
||||
#ifdef MT_SPM_COMMON_SODI_SUPPORT
|
||||
#if defined(CFG_MICROTRUST_TEE_SUPPORT)
|
||||
.reg_wake_mask = 0x81302012,
|
||||
#else
|
||||
.reg_wake_mask = 0x89302012,
|
||||
#endif
|
||||
#else
|
||||
.reg_wake_mask = 0xEFFFFFF7,
|
||||
#endif
|
||||
|
||||
.reg_ext_wake_mask = 0xFFFFFFFF,
|
||||
};
|
||||
|
||||
struct spm_lp_scen __spm_vcorefs = {
|
||||
.pwrctrl = &vcorefs_ctrl,
|
||||
};
|
||||
|
||||
static int get_vsram_pmic_voltage(void)
|
||||
{
|
||||
uint8_t vsram_pmic = 0x78;
|
||||
int spmi_ret = 0;
|
||||
#ifdef CONFIG_MTK_SPMI
|
||||
struct spmi_device *spmi_dev;
|
||||
|
||||
spmi_dev = get_spmi_device(SPMI_MASTER_1, SPMI_SLAVE_4);
|
||||
if (spmi_dev == NULL)
|
||||
return vsram_pmic;
|
||||
|
||||
spmi_ret = spmi_ext_register_readl(spmi_dev, 0x250, &vsram_pmic, 1);
|
||||
#endif
|
||||
if (spmi_ret != 0)
|
||||
vsram_pmic = 0x78;
|
||||
|
||||
return vsram_pmic;
|
||||
}
|
||||
|
||||
static int get_vcore_pmic_voltage(void)
|
||||
{
|
||||
uint8_t vcore_pmic = 0x91;
|
||||
int spmi_ret = 0;
|
||||
#ifdef CONFIG_MTK_SPMI
|
||||
struct spmi_device *spmi_dev;
|
||||
uint16_t vcore_addr;
|
||||
|
||||
vcore_addr = (uint16_t)((mmio_read_32(SPM_PWRAP_CMD0) >> 16) & 0xFFFF);
|
||||
spmi_dev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_8);
|
||||
if (spmi_dev == NULL)
|
||||
return vcore_pmic;
|
||||
|
||||
spmi_ret = spmi_ext_register_readl(spmi_dev, vcore_addr, &vcore_pmic, 1);
|
||||
#endif
|
||||
if (spmi_ret != 0)
|
||||
vcore_pmic = 0x91;
|
||||
|
||||
return vcore_pmic;
|
||||
}
|
||||
|
||||
void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue)
|
||||
{
|
||||
uint32_t pmic_val;
|
||||
|
||||
pmic_val = get_vsram_pmic_voltage();
|
||||
pmic_val = VCORE_UV_TO_PMIC(VSRAM_PMIC_TO_UV(pmic_val));
|
||||
mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, CMD_17, pmic_val);
|
||||
pmic_val = get_vcore_pmic_voltage();
|
||||
mmio_write_32(PCM_WDT_LATCH_SPARE_5, pmic_val);
|
||||
|
||||
if (spm_dvfs_init_done)
|
||||
return;
|
||||
|
||||
mmio_clrsetbits_32(SPM_DVFS_CON, SPM_DVFS_FORCE_ENABLE_LSB, SPM_DVFSRC_ENABLE_LSB);
|
||||
|
||||
mmio_write_32(SPM_SW_RSV_3, 0x08000000);
|
||||
mmio_write_32(SPM_DVS_DFS_LEVEL, 0x10080080);
|
||||
mmio_write_32(PCM_WDT_LATCH_SPARE_4, 0x08008002);
|
||||
|
||||
spm_dvfs_init_done = 1;
|
||||
}
|
||||
|
||||
void __spm_sync_vcore_dvfs_pcm_flags(uint32_t *dest_pcm_flags,
|
||||
const uint32_t *src_pcm_flags)
|
||||
{
|
||||
uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS |
|
||||
SPM_FLAG_DISABLE_DDR_DFS |
|
||||
SPM_FLAG_DISABLE_EMI_DFS |
|
||||
SPM_FLAG_DISABLE_BUS_DFS;
|
||||
|
||||
*dest_pcm_flags = (*dest_pcm_flags & (~dvfs_mask)) |
|
||||
(*src_pcm_flags & dvfs_mask);
|
||||
}
|
||||
|
||||
void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
|
||||
const struct pwr_ctrl *src_pwr_ctrl)
|
||||
{
|
||||
|
||||
__spm_sync_vcore_dvfs_pcm_flags(&dest_pwr_ctrl->pcm_flags,
|
||||
&src_pwr_ctrl->pcm_flags);
|
||||
|
||||
if (dest_pwr_ctrl->pcm_flags_cust)
|
||||
__spm_sync_vcore_dvfs_pcm_flags(&dest_pwr_ctrl->pcm_flags_cust,
|
||||
&src_pwr_ctrl->pcm_flags);
|
||||
}
|
||||
|
||||
void spm_go_to_vcorefs(uint64_t spm_flags)
|
||||
{
|
||||
set_pwrctrl_pcm_flags(__spm_vcorefs.pwrctrl, spm_flags);
|
||||
__spm_set_power_control(__spm_vcorefs.pwrctrl, 0);
|
||||
__spm_set_wakeup_event(__spm_vcorefs.pwrctrl);
|
||||
__spm_set_pcm_flags(__spm_vcorefs.pwrctrl);
|
||||
__spm_send_cpu_wakeup_event();
|
||||
}
|
||||
12
plat/mediatek/drivers/spm/mt8196/mt_spm_vcorefs.h
Normal file
12
plat/mediatek/drivers/spm/mt8196/mt_spm_vcorefs.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2025, Mediatek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_VCOREFS_H
|
||||
#define MT_SPM_VCOREFS_H
|
||||
|
||||
void spm_go_to_vcorefs(uint64_t spm_flags);
|
||||
|
||||
#endif /* MT_SPM_VCOREFS_H */
|
||||
14
plat/mediatek/drivers/spm/mt8196/mt_spm_vcorefs_ext.h
Normal file
14
plat/mediatek/drivers/spm/mt8196/mt_spm_vcorefs_ext.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright (c) 2025, Mediatek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_VCORE_DVFSRC_EXT_H
|
||||
|
||||
#define MT_VCORE_DVFSRC_EXT_H
|
||||
#define MTK_VCORE_DVFS_RES_MEM
|
||||
|
||||
int spm_vcorefs_rsc_mem_req(bool request);
|
||||
|
||||
#endif /* MT_VCORE_DVFSRC_EXT_H */
|
||||
598
plat/mediatek/drivers/spm/mt8196/mt_spm_vcorefs_reg.h
Normal file
598
plat/mediatek/drivers/spm/mt8196/mt_spm_vcorefs_reg.h
Normal file
|
|
@ -0,0 +1,598 @@
|
|||
/*
|
||||
* Copyright (c) 2025, Mediatek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_VCOREFS_REG_6991_H
|
||||
#define MT_SPM_VCOREFS_REG_6991_H
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
/*************************************************************************
|
||||
* DVFSRC related constants
|
||||
*************************************************************************/
|
||||
#define DVFSRC_BASE (IO_PHYS + 0x0C013000)
|
||||
#define EFUSEC_BASE (IO_PHYS + 0x03260000)
|
||||
#define EFUSE_SIZE (0x1000)
|
||||
#define DVFSRC_REG_SIZE (0x1000)
|
||||
#define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
|
||||
#define DVFSRC_BASIC_CONTROL_4 (DVFSRC_BASE + 0xC)
|
||||
#define DVFSRC_SW_REQ1 (DVFSRC_BASE + 0x10)
|
||||
#define DVFSRC_SW_REQ2 (DVFSRC_BASE + 0x14)
|
||||
#define DVFSRC_SW_REQ3 (DVFSRC_BASE + 0x18)
|
||||
#define DVFSRC_SW_REQ4 (DVFSRC_BASE + 0x1C)
|
||||
#define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x20)
|
||||
#define DVFSRC_SW_REQ6 (DVFSRC_BASE + 0x24)
|
||||
#define DVFSRC_SW_REQ7 (DVFSRC_BASE + 0x28)
|
||||
#define DVFSRC_SW_REQ8 (DVFSRC_BASE + 0x2C)
|
||||
#define DVFSRC_EMI_REQUEST (DVFSRC_BASE + 0x30)
|
||||
#define DVFSRC_EMI_REQUEST3 (DVFSRC_BASE + 0x38)
|
||||
#define DVFSRC_EMI_REQUEST5 (DVFSRC_BASE + 0x40)
|
||||
#define DVFSRC_EMI_QOS0 (DVFSRC_BASE + 0x4C)
|
||||
#define DVFSRC_EMI_QOS1 (DVFSRC_BASE + 0x50)
|
||||
#define DVFSRC_EMI_QOS2 (DVFSRC_BASE + 0x54)
|
||||
#define DVFSRC_EMI_QOS3 (DVFSRC_BASE + 0x58)
|
||||
#define DVFSRC_EMI_QOS4 (DVFSRC_BASE + 0x5C)
|
||||
#define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0x60)
|
||||
#define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0x64)
|
||||
#define DVFSRC_VCORE_REQUEST (DVFSRC_BASE + 0x80)
|
||||
#define DVFSRC_VCORE_REQUEST3 (DVFSRC_BASE + 0x88)
|
||||
#define DVFSRC_VCORE_QOS0 (DVFSRC_BASE + 0x94)
|
||||
#define DVFSRC_VCORE_QOS1 (DVFSRC_BASE + 0x98)
|
||||
#define DVFSRC_VCORE_QOS2 (DVFSRC_BASE + 0x9C)
|
||||
#define DVFSRC_VCORE_QOS3 (DVFSRC_BASE + 0xA0)
|
||||
#define DVFSRC_VCORE_QOS4 (DVFSRC_BASE + 0xA4)
|
||||
#define DVFSRC_HALT_SW_CONTROL (DVFSRC_BASE + 0xC4)
|
||||
#define DVFSRC_INT (DVFSRC_BASE + 0xC8)
|
||||
#define DVFSRC_INT_EN (DVFSRC_BASE + 0xCC)
|
||||
#define DVFSRC_INT_CLR (DVFSRC_BASE + 0xD0)
|
||||
#define DVFSRC_BW_MON_WINDOW (DVFSRC_BASE + 0xD4)
|
||||
#define DVFSRC_BW_MON_THRES_1 (DVFSRC_BASE + 0xD8)
|
||||
#define DVFSRC_BW_MON_THRES_2 (DVFSRC_BASE + 0xDC)
|
||||
#define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xE0)
|
||||
#define DVFSRC_PCIE_VCORE_REQ (DVFSRC_BASE + 0xE4)
|
||||
#define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE8)
|
||||
#define DVFSRC_BW_USER_REQ (DVFSRC_BASE + 0xEC)
|
||||
#define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8)
|
||||
#define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0xFC)
|
||||
#define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x100)
|
||||
#define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x104)
|
||||
#define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x108)
|
||||
#define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x10C)
|
||||
#define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x110)
|
||||
#define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x114)
|
||||
#define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x118)
|
||||
#define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0x11C)
|
||||
#define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0x120)
|
||||
#define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0x124)
|
||||
#define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0x128)
|
||||
#define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0x12C)
|
||||
#define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0x130)
|
||||
#define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0x134)
|
||||
#define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0x138)
|
||||
#define DVFSRC_LEVEL_LABEL_32_33 (DVFSRC_BASE + 0x13C)
|
||||
#define DVFSRC_LEVEL_LABEL_34_35 (DVFSRC_BASE + 0x140)
|
||||
#define DVFSRC_LEVEL_LABEL_36_37 (DVFSRC_BASE + 0x144)
|
||||
#define DVFSRC_LEVEL_LABEL_38_39 (DVFSRC_BASE + 0x148)
|
||||
#define DVFSRC_LEVEL_LABEL_40_41 (DVFSRC_BASE + 0x14C)
|
||||
#define DVFSRC_LEVEL_LABEL_42_43 (DVFSRC_BASE + 0x150)
|
||||
#define DVFSRC_LEVEL_LABEL_44_45 (DVFSRC_BASE + 0x154)
|
||||
#define DVFSRC_LEVEL_LABEL_46_47 (DVFSRC_BASE + 0x158)
|
||||
#define DVFSRC_LEVEL_LABEL_48_49 (DVFSRC_BASE + 0x15C)
|
||||
#define DVFSRC_LEVEL_LABEL_50_51 (DVFSRC_BASE + 0x160)
|
||||
#define DVFSRC_LEVEL_LABEL_52_53 (DVFSRC_BASE + 0x164)
|
||||
#define DVFSRC_LEVEL_LABEL_54_55 (DVFSRC_BASE + 0x168)
|
||||
#define DVFSRC_LEVEL_LABEL_56_57 (DVFSRC_BASE + 0x16C)
|
||||
#define DVFSRC_LEVEL_LABEL_58_59 (DVFSRC_BASE + 0x170)
|
||||
#define DVFSRC_LEVEL_LABEL_60_61 (DVFSRC_BASE + 0x174)
|
||||
#define DVFSRC_LEVEL_LABEL_62_63 (DVFSRC_BASE + 0x178)
|
||||
#define DVFSRC_SW_BW_0 (DVFSRC_BASE + 0x1DC)
|
||||
#define DVFSRC_SW_BW_1 (DVFSRC_BASE + 0x1E0)
|
||||
#define DVFSRC_SW_BW_2 (DVFSRC_BASE + 0x1E4)
|
||||
#define DVFSRC_SW_BW_3 (DVFSRC_BASE + 0x1E8)
|
||||
#define DVFSRC_SW_BW_4 (DVFSRC_BASE + 0x1EC)
|
||||
#define DVFSRC_SW_BW_5 (DVFSRC_BASE + 0x1F0)
|
||||
#define DVFSRC_SW_BW_6 (DVFSRC_BASE + 0x1F4)
|
||||
#define DVFSRC_SW_BW_7 (DVFSRC_BASE + 0x1F8)
|
||||
#define DVFSRC_SW_BW_8 (DVFSRC_BASE + 0x1FC)
|
||||
#define DVFSRC_SW_BW_9 (DVFSRC_BASE + 0x200)
|
||||
#define DVFSRC_QOS_EN (DVFSRC_BASE + 0x204)
|
||||
#define DVFSRC_ISP_HRT (DVFSRC_BASE + 0x20C)
|
||||
#define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x210)
|
||||
#define DVFSRC_SEC_SW_REQ (DVFSRC_BASE + 0x214)
|
||||
#define DVFSRC_EMI_MON_DEBOUNCE_TIME (DVFSRC_BASE + 0x218)
|
||||
#define DVFSRC_MD_LATENCY_IMPROVE (DVFSRC_BASE + 0x21C)
|
||||
#define DVFSRC_DEBOUNCE_TIME (DVFSRC_BASE + 0x220)
|
||||
#define DVFSRC_LEVEL_MASK_MD_1 (DVFSRC_BASE + 0x224)
|
||||
#define DVFSRC_LEVEL_MASK_MD_2 (DVFSRC_BASE + 0x228)
|
||||
#define DVFSRC_DEFAULT_OPP_1 (DVFSRC_BASE + 0x22C)
|
||||
#define DVFSRC_DEFAULT_OPP_2 (DVFSRC_BASE + 0x230)
|
||||
#define DVFSRC_95MD_SCEN_EMI0 (DVFSRC_BASE + 0x234)
|
||||
#define DVFSRC_95MD_SCEN_EMI1 (DVFSRC_BASE + 0x238)
|
||||
#define DVFSRC_95MD_SCEN_EMI2 (DVFSRC_BASE + 0x23C)
|
||||
#define DVFSRC_95MD_SCEN_EMI3 (DVFSRC_BASE + 0x240)
|
||||
#define DVFSRC_95MD_SCEN_EMI0_T (DVFSRC_BASE + 0x244)
|
||||
#define DVFSRC_95MD_SCEN_EMI1_T (DVFSRC_BASE + 0x248)
|
||||
#define DVFSRC_95MD_SCEN_EMI2_T (DVFSRC_BASE + 0x24C)
|
||||
#define DVFSRC_95MD_SCEN_EMI3_T (DVFSRC_BASE + 0x250)
|
||||
#define DVFSRC_95MD_SCEN_EMIU (DVFSRC_BASE + 0x254)
|
||||
#define DVFSRC_95MD_SCEN_BW0 (DVFSRC_BASE + 0x258)
|
||||
#define DVFSRC_95MD_SCEN_BW1 (DVFSRC_BASE + 0x25C)
|
||||
#define DVFSRC_95MD_SCEN_BW2 (DVFSRC_BASE + 0x260)
|
||||
#define DVFSRC_95MD_SCEN_BW3 (DVFSRC_BASE + 0x264)
|
||||
#define DVFSRC_95MD_SCEN_BW0_T (DVFSRC_BASE + 0x268)
|
||||
#define DVFSRC_95MD_SCEN_BW1_T (DVFSRC_BASE + 0x26C)
|
||||
#define DVFSRC_95MD_SCEN_BW2_T (DVFSRC_BASE + 0x270)
|
||||
#define DVFSRC_95MD_SCEN_BW3_T (DVFSRC_BASE + 0x274)
|
||||
#define DVFSRC_95MD_SCEN_BWU (DVFSRC_BASE + 0x278)
|
||||
#define DVFSRC_MD_LEVEL_SW_REG (DVFSRC_BASE + 0x27C)
|
||||
#define DVFSRC_RSRV_0 (DVFSRC_BASE + 0x280)
|
||||
#define DVFSRC_RSRV_1 (DVFSRC_BASE + 0x284)
|
||||
#define DVFSRC_RSRV_2 (DVFSRC_BASE + 0x288)
|
||||
#define DVFSRC_RSRV_3 (DVFSRC_BASE + 0x28C)
|
||||
#define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x290)
|
||||
#define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x294)
|
||||
#define DVFSRC_SPM_RESEND (DVFSRC_BASE + 0x298)
|
||||
#define DVFSRC_DEBUG_STA_0 (DVFSRC_BASE + 0x29C)
|
||||
#define DVFSRC_DEBUG_STA_1 (DVFSRC_BASE + 0x2A0)
|
||||
#define DVFSRC_DEBUG_STA_2 (DVFSRC_BASE + 0x2A4)
|
||||
#define DVFSRC_DEBUG_STA_3 (DVFSRC_BASE + 0x2A8)
|
||||
#define DVFSRC_DEBUG_STA_4 (DVFSRC_BASE + 0x2AC)
|
||||
#define DVFSRC_DEBUG_STA_5 (DVFSRC_BASE + 0x2B0)
|
||||
#define DVFSRC_DEBUG_STA_6 (DVFSRC_BASE + 0x2B4)
|
||||
#define DVFSRC_DEBUG_STA_8 (DVFSRC_BASE + 0x2BC)
|
||||
#define DVFSRC_DEBUG_STA_9 (DVFSRC_BASE + 0x2C0)
|
||||
#define DVFSRC_DEBUG_STA_10 (DVFSRC_BASE + 0x2C4)
|
||||
#define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0x2C8)
|
||||
#define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0x2D0)
|
||||
#define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0x2D8)
|
||||
#define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0x2E8)
|
||||
#define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0x2EC)
|
||||
#define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0x2F0)
|
||||
#define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0x2F4)
|
||||
#define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0x2F8)
|
||||
#define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0x2FC)
|
||||
#define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0x300)
|
||||
#define DVFSRC_RSRV_6 (DVFSRC_BASE + 0x304)
|
||||
#define DVFSRC_RSRV_7 (DVFSRC_BASE + 0x308)
|
||||
#define DVFSRC_RSRV_8 (DVFSRC_BASE + 0x30C)
|
||||
#define DVFSRC_RSRV_9 (DVFSRC_BASE + 0x310)
|
||||
#define DVFSRC_RSRV_10 (DVFSRC_BASE + 0x314)
|
||||
#define DVFSRC_RSRV_11 (DVFSRC_BASE + 0x318)
|
||||
#define DVFSRC_HRT_REQ_MD_URG (DVFSRC_BASE + 0x320)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_0 (DVFSRC_BASE + 0x324)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_1 (DVFSRC_BASE + 0x328)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_2 (DVFSRC_BASE + 0x32C)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_3 (DVFSRC_BASE + 0x330)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_4 (DVFSRC_BASE + 0x334)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_5 (DVFSRC_BASE + 0x338)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_6 (DVFSRC_BASE + 0x33C)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_7 (DVFSRC_BASE + 0x340)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_8 (DVFSRC_BASE + 0x344)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_9 (DVFSRC_BASE + 0x348)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_10 (DVFSRC_BASE + 0x34C)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_0 (DVFSRC_BASE + 0x350)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_1 (DVFSRC_BASE + 0x354)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_2 (DVFSRC_BASE + 0x358)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_3 (DVFSRC_BASE + 0x35C)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_4 (DVFSRC_BASE + 0x360)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_5 (DVFSRC_BASE + 0x364)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_6 (DVFSRC_BASE + 0x368)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_7 (DVFSRC_BASE + 0x36C)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_8 (DVFSRC_BASE + 0x370)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_9 (DVFSRC_BASE + 0x374)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_10 (DVFSRC_BASE + 0x378)
|
||||
#define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0x380)
|
||||
#define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0x384)
|
||||
#define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0x388)
|
||||
#define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0x38C)
|
||||
#define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0x390)
|
||||
#define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0x394)
|
||||
#define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0x398)
|
||||
#define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0x39C)
|
||||
#define DVFSRC_HRT_LOW (DVFSRC_BASE + 0x3A0)
|
||||
#define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0x3A4)
|
||||
#define DVFSRC_EMI_ADD_REQUEST (DVFSRC_BASE + 0x3A8)
|
||||
#define DVFSRC_LAST (DVFSRC_BASE + 0x3AC)
|
||||
#define DVFSRC_LAST_L (DVFSRC_BASE + 0x3B0)
|
||||
#define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0x3B4)
|
||||
#define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0x3B8)
|
||||
#define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0x3BC)
|
||||
#define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0x3C0)
|
||||
#define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0x3C4)
|
||||
#define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0x3C8)
|
||||
#define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0x3CC)
|
||||
#define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0x3D0)
|
||||
#define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0x3D4)
|
||||
#define DVFSRC_RECORD_1_0 (DVFSRC_BASE + 0x3D8)
|
||||
#define DVFSRC_RECORD_1_1 (DVFSRC_BASE + 0x3DC)
|
||||
#define DVFSRC_RECORD_1_2 (DVFSRC_BASE + 0x3E0)
|
||||
#define DVFSRC_RECORD_1_3 (DVFSRC_BASE + 0x3E4)
|
||||
#define DVFSRC_RECORD_1_4 (DVFSRC_BASE + 0x3E8)
|
||||
#define DVFSRC_RECORD_1_5 (DVFSRC_BASE + 0x3EC)
|
||||
#define DVFSRC_RECORD_1_6 (DVFSRC_BASE + 0x3F0)
|
||||
#define DVFSRC_RECORD_1_7 (DVFSRC_BASE + 0x3F4)
|
||||
#define DVFSRC_RECORD_2_0 (DVFSRC_BASE + 0x3F8)
|
||||
#define DVFSRC_RECORD_2_1 (DVFSRC_BASE + 0x3FC)
|
||||
#define DVFSRC_RECORD_2_2 (DVFSRC_BASE + 0x400)
|
||||
#define DVFSRC_RECORD_2_3 (DVFSRC_BASE + 0x404)
|
||||
#define DVFSRC_RECORD_2_4 (DVFSRC_BASE + 0x408)
|
||||
#define DVFSRC_RECORD_2_5 (DVFSRC_BASE + 0x40C)
|
||||
#define DVFSRC_RECORD_2_6 (DVFSRC_BASE + 0x410)
|
||||
#define DVFSRC_RECORD_2_7 (DVFSRC_BASE + 0x414)
|
||||
#define DVFSRC_RECORD_3_0 (DVFSRC_BASE + 0x418)
|
||||
#define DVFSRC_RECORD_3_1 (DVFSRC_BASE + 0x41C)
|
||||
#define DVFSRC_RECORD_3_2 (DVFSRC_BASE + 0x420)
|
||||
#define DVFSRC_RECORD_3_3 (DVFSRC_BASE + 0x424)
|
||||
#define DVFSRC_RECORD_3_4 (DVFSRC_BASE + 0x428)
|
||||
#define DVFSRC_RECORD_3_5 (DVFSRC_BASE + 0x42C)
|
||||
#define DVFSRC_RECORD_3_6 (DVFSRC_BASE + 0x430)
|
||||
#define DVFSRC_RECORD_3_7 (DVFSRC_BASE + 0x434)
|
||||
#define DVFSRC_RECORD_4_0 (DVFSRC_BASE + 0x438)
|
||||
#define DVFSRC_RECORD_4_1 (DVFSRC_BASE + 0x43C)
|
||||
#define DVFSRC_RECORD_4_2 (DVFSRC_BASE + 0x440)
|
||||
#define DVFSRC_RECORD_4_3 (DVFSRC_BASE + 0x444)
|
||||
#define DVFSRC_RECORD_4_4 (DVFSRC_BASE + 0x448)
|
||||
#define DVFSRC_RECORD_4_5 (DVFSRC_BASE + 0x44C)
|
||||
#define DVFSRC_RECORD_4_6 (DVFSRC_BASE + 0x450)
|
||||
#define DVFSRC_RECORD_4_7 (DVFSRC_BASE + 0x454)
|
||||
#define DVFSRC_RECORD_5_0 (DVFSRC_BASE + 0x458)
|
||||
#define DVFSRC_RECORD_5_1 (DVFSRC_BASE + 0x45C)
|
||||
#define DVFSRC_RECORD_5_2 (DVFSRC_BASE + 0x460)
|
||||
#define DVFSRC_RECORD_5_3 (DVFSRC_BASE + 0x464)
|
||||
#define DVFSRC_RECORD_5_4 (DVFSRC_BASE + 0x468)
|
||||
#define DVFSRC_RECORD_5_5 (DVFSRC_BASE + 0x46C)
|
||||
#define DVFSRC_RECORD_5_6 (DVFSRC_BASE + 0x470)
|
||||
#define DVFSRC_RECORD_5_7 (DVFSRC_BASE + 0x474)
|
||||
#define DVFSRC_RECORD_6_0 (DVFSRC_BASE + 0x478)
|
||||
#define DVFSRC_RECORD_6_1 (DVFSRC_BASE + 0x47C)
|
||||
#define DVFSRC_RECORD_6_2 (DVFSRC_BASE + 0x480)
|
||||
#define DVFSRC_RECORD_6_3 (DVFSRC_BASE + 0x484)
|
||||
#define DVFSRC_RECORD_6_4 (DVFSRC_BASE + 0x488)
|
||||
#define DVFSRC_RECORD_6_5 (DVFSRC_BASE + 0x48C)
|
||||
#define DVFSRC_RECORD_6_6 (DVFSRC_BASE + 0x490)
|
||||
#define DVFSRC_RECORD_6_7 (DVFSRC_BASE + 0x494)
|
||||
#define DVFSRC_RECORD_7_0 (DVFSRC_BASE + 0x498)
|
||||
#define DVFSRC_RECORD_7_1 (DVFSRC_BASE + 0x49C)
|
||||
#define DVFSRC_RECORD_7_2 (DVFSRC_BASE + 0x4A0)
|
||||
#define DVFSRC_RECORD_7_3 (DVFSRC_BASE + 0x4A4)
|
||||
#define DVFSRC_RECORD_7_4 (DVFSRC_BASE + 0x4A8)
|
||||
#define DVFSRC_RECORD_7_5 (DVFSRC_BASE + 0x4AC)
|
||||
#define DVFSRC_RECORD_7_6 (DVFSRC_BASE + 0x4B0)
|
||||
#define DVFSRC_RECORD_7_7 (DVFSRC_BASE + 0x4B4)
|
||||
#define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0x4B8)
|
||||
#define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0x4BC)
|
||||
#define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0x4C0)
|
||||
#define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0x4C4)
|
||||
#define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0x4C8)
|
||||
#define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0x4CC)
|
||||
#define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0x4D0)
|
||||
#define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0x4D4)
|
||||
#define DVFSRC_RECORD_1_L_0 (DVFSRC_BASE + 0x4D8)
|
||||
#define DVFSRC_RECORD_1_L_1 (DVFSRC_BASE + 0x4DC)
|
||||
#define DVFSRC_RECORD_1_L_2 (DVFSRC_BASE + 0x4E0)
|
||||
#define DVFSRC_RECORD_1_L_3 (DVFSRC_BASE + 0x4E4)
|
||||
#define DVFSRC_RECORD_1_L_4 (DVFSRC_BASE + 0x4E8)
|
||||
#define DVFSRC_RECORD_1_L_5 (DVFSRC_BASE + 0x4EC)
|
||||
#define DVFSRC_RECORD_1_L_6 (DVFSRC_BASE + 0x4F0)
|
||||
#define DVFSRC_RECORD_1_L_7 (DVFSRC_BASE + 0x4F4)
|
||||
#define DVFSRC_RECORD_2_L_0 (DVFSRC_BASE + 0x4F8)
|
||||
#define DVFSRC_RECORD_2_L_1 (DVFSRC_BASE + 0x4FC)
|
||||
#define DVFSRC_RECORD_2_L_2 (DVFSRC_BASE + 0x500)
|
||||
#define DVFSRC_RECORD_2_L_3 (DVFSRC_BASE + 0x504)
|
||||
#define DVFSRC_RECORD_2_L_4 (DVFSRC_BASE + 0x508)
|
||||
#define DVFSRC_RECORD_2_L_5 (DVFSRC_BASE + 0x50C)
|
||||
#define DVFSRC_RECORD_2_L_6 (DVFSRC_BASE + 0x510)
|
||||
#define DVFSRC_RECORD_2_L_7 (DVFSRC_BASE + 0x514)
|
||||
#define DVFSRC_RECORD_3_L_0 (DVFSRC_BASE + 0x518)
|
||||
#define DVFSRC_RECORD_3_L_1 (DVFSRC_BASE + 0x51C)
|
||||
#define DVFSRC_RECORD_3_L_2 (DVFSRC_BASE + 0x520)
|
||||
#define DVFSRC_RECORD_3_L_3 (DVFSRC_BASE + 0x524)
|
||||
#define DVFSRC_RECORD_3_L_4 (DVFSRC_BASE + 0x528)
|
||||
#define DVFSRC_RECORD_3_L_5 (DVFSRC_BASE + 0x52C)
|
||||
#define DVFSRC_RECORD_3_L_6 (DVFSRC_BASE + 0x530)
|
||||
#define DVFSRC_RECORD_3_L_7 (DVFSRC_BASE + 0x534)
|
||||
#define DVFSRC_RECORD_4_L_0 (DVFSRC_BASE + 0x538)
|
||||
#define DVFSRC_RECORD_4_L_1 (DVFSRC_BASE + 0x53C)
|
||||
#define DVFSRC_RECORD_4_L_2 (DVFSRC_BASE + 0x540)
|
||||
#define DVFSRC_RECORD_4_L_3 (DVFSRC_BASE + 0x544)
|
||||
#define DVFSRC_RECORD_4_L_4 (DVFSRC_BASE + 0x548)
|
||||
#define DVFSRC_RECORD_4_L_5 (DVFSRC_BASE + 0x54C)
|
||||
#define DVFSRC_RECORD_4_L_6 (DVFSRC_BASE + 0x550)
|
||||
#define DVFSRC_RECORD_4_L_7 (DVFSRC_BASE + 0x554)
|
||||
#define DVFSRC_RECORD_5_L_0 (DVFSRC_BASE + 0x558)
|
||||
#define DVFSRC_RECORD_5_L_1 (DVFSRC_BASE + 0x55C)
|
||||
#define DVFSRC_RECORD_5_L_2 (DVFSRC_BASE + 0x560)
|
||||
#define DVFSRC_RECORD_5_L_3 (DVFSRC_BASE + 0x564)
|
||||
#define DVFSRC_RECORD_5_L_4 (DVFSRC_BASE + 0x568)
|
||||
#define DVFSRC_RECORD_5_L_5 (DVFSRC_BASE + 0x56C)
|
||||
#define DVFSRC_RECORD_5_L_6 (DVFSRC_BASE + 0x570)
|
||||
#define DVFSRC_RECORD_5_L_7 (DVFSRC_BASE + 0x574)
|
||||
#define DVFSRC_RECORD_6_L_0 (DVFSRC_BASE + 0x578)
|
||||
#define DVFSRC_RECORD_6_L_1 (DVFSRC_BASE + 0x57C)
|
||||
#define DVFSRC_RECORD_6_L_2 (DVFSRC_BASE + 0x580)
|
||||
#define DVFSRC_RECORD_6_L_3 (DVFSRC_BASE + 0x584)
|
||||
#define DVFSRC_RECORD_6_L_4 (DVFSRC_BASE + 0x588)
|
||||
#define DVFSRC_RECORD_6_L_5 (DVFSRC_BASE + 0x58C)
|
||||
#define DVFSRC_RECORD_6_L_6 (DVFSRC_BASE + 0x590)
|
||||
#define DVFSRC_RECORD_6_L_7 (DVFSRC_BASE + 0x594)
|
||||
#define DVFSRC_RECORD_7_L_0 (DVFSRC_BASE + 0x598)
|
||||
#define DVFSRC_RECORD_7_L_1 (DVFSRC_BASE + 0x59C)
|
||||
#define DVFSRC_RECORD_7_L_2 (DVFSRC_BASE + 0x5A0)
|
||||
#define DVFSRC_RECORD_7_L_3 (DVFSRC_BASE + 0x5A4)
|
||||
#define DVFSRC_RECORD_7_L_4 (DVFSRC_BASE + 0x5A8)
|
||||
#define DVFSRC_RECORD_7_L_5 (DVFSRC_BASE + 0x5AC)
|
||||
#define DVFSRC_RECORD_7_L_6 (DVFSRC_BASE + 0x5B0)
|
||||
#define DVFSRC_RECORD_7_L_7 (DVFSRC_BASE + 0x5B4)
|
||||
#define DVFSRC_CURRENT_LEVEL_1 (DVFSRC_BASE + 0x5C4)
|
||||
#define DVFSRC_CURRENT_LEVEL_2 (DVFSRC_BASE + 0x5C8)
|
||||
#define DVFSRC_TARGET_LEVEL_1 (DVFSRC_BASE + 0x5CC)
|
||||
#define DVFSRC_TARGET_LEVEL_2 (DVFSRC_BASE + 0x5D0)
|
||||
#define DVFSRC_CURRENT_FORCE_1 (DVFSRC_BASE + 0x5D4)
|
||||
#define DVFSRC_CURRENT_FORCE_2 (DVFSRC_BASE + 0x5D8)
|
||||
#define DVFSRC_TARGET_FORCE_1 (DVFSRC_BASE + 0x5DC)
|
||||
#define DVFSRC_TARGET_FORCE_2 (DVFSRC_BASE + 0x5E0)
|
||||
#define DVFSRC_MD_DDR_FLOOR_REQUEST (DVFSRC_BASE + 0x5E4)
|
||||
#define DVFSRC_QOS_DDR_REQUEST (DVFSRC_BASE + 0x5E8)
|
||||
#define DVFSRC_FORCE_MASK (DVFSRC_BASE + 0x5EC)
|
||||
#define DVFSRC_LEVEL_HEX (DVFSRC_BASE + 0x5F0)
|
||||
#define DVFSRC_AVS_RETRY (DVFSRC_BASE + 0x5F4)
|
||||
#define DVFSRC_SW_REQ9 (DVFSRC_BASE + 0x5F8)
|
||||
#define DVFSRC_SW_REQ10 (DVFSRC_BASE + 0x5FC)
|
||||
#define DVFSRC_SW_REQ11 (DVFSRC_BASE + 0x600)
|
||||
#define DVFSRC_SW_REQ12 (DVFSRC_BASE + 0x604)
|
||||
#define DVFSRC_LEVEL_MASK_SW_1 (DVFSRC_BASE + 0x608)
|
||||
#define DVFSRC_LEVEL_MASK_SW_2 (DVFSRC_BASE + 0x60C)
|
||||
#define DVFSRC_ACCEPT_RETRY (DVFSRC_BASE + 0x610)
|
||||
#define DVFSRC_TARGET_LEVEL_SPM_1 (DVFSRC_BASE + 0x614)
|
||||
#define DVFSRC_TARGET_LEVEL_SPM_2 (DVFSRC_BASE + 0x618)
|
||||
#define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0x620)
|
||||
#define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0x62C)
|
||||
#define DVFSRC_EMI_QOS7 (DVFSRC_BASE + 0x64C)
|
||||
#define DVFSRC_EMI_QOS8 (DVFSRC_BASE + 0x650)
|
||||
#define DVFSRC_EMI_QOS9 (DVFSRC_BASE + 0x654)
|
||||
#define DVFSRC_EMI_QOS10 (DVFSRC_BASE + 0x658)
|
||||
#define DVFSRC_DDR_QOS7 (DVFSRC_BASE + 0x65C)
|
||||
#define DVFSRC_DDR_QOS8 (DVFSRC_BASE + 0x660)
|
||||
#define DVFSRC_DDR_QOS9 (DVFSRC_BASE + 0x664)
|
||||
#define DVFSRC_DDR_QOS10 (DVFSRC_BASE + 0x668)
|
||||
#define DVFSRC_HRT_HIGH_7 (DVFSRC_BASE + 0x66C)
|
||||
#define DVFSRC_HRT_HIGH_6 (DVFSRC_BASE + 0x670)
|
||||
#define DVFSRC_HRT_HIGH_5 (DVFSRC_BASE + 0x674)
|
||||
#define DVFSRC_HRT_HIGH_4 (DVFSRC_BASE + 0x678)
|
||||
#define DVFSRC_HRT_LOW_7 (DVFSRC_BASE + 0x67C)
|
||||
#define DVFSRC_HRT_LOW_6 (DVFSRC_BASE + 0x680)
|
||||
#define DVFSRC_HRT_LOW_5 (DVFSRC_BASE + 0x684)
|
||||
#define DVFSRC_HRT_LOW_4 (DVFSRC_BASE + 0x688)
|
||||
#define DVFSRC_DDR_ADD_REQUEST_1 (DVFSRC_BASE + 0x68C)
|
||||
#define DVFSRC_EMI_ADD_REQUEST_1 (DVFSRC_BASE + 0x690)
|
||||
#define DVFSRC_HRT_REQUEST_1 (DVFSRC_BASE + 0x694)
|
||||
#define DVFSRC_VCORE_QOS5 (DVFSRC_BASE + 0x69C)
|
||||
#define DVFSRC_VCORE_QOS6 (DVFSRC_BASE + 0x6A0)
|
||||
#define DVFSRC_VCORE_QOS7 (DVFSRC_BASE + 0x6A4)
|
||||
#define DVFSRC_CEILING_SET (DVFSRC_BASE + 0x6A8)
|
||||
#define DVFSRC_CUR_TARGET_GEAR (DVFSRC_BASE + 0x6AC)
|
||||
#define DVFSRC_LEVEL_LABEL_64_65 (DVFSRC_BASE + 0x6B0)
|
||||
#define DVFSRC_LEVEL_LABEL_66_67 (DVFSRC_BASE + 0x6B4)
|
||||
#define DVFSRC_LEVEL_LABEL_68_69 (DVFSRC_BASE + 0x6B8)
|
||||
#define DVFSRC_LEVEL_LABEL_70_71 (DVFSRC_BASE + 0x6BC)
|
||||
#define DVFSRC_LEVEL_LABEL_72_73 (DVFSRC_BASE + 0x6C0)
|
||||
#define DVFSRC_LEVEL_LABEL_74_75 (DVFSRC_BASE + 0x6C4)
|
||||
#define DVFSRC_LEVEL_LABEL_76_77 (DVFSRC_BASE + 0x6C8)
|
||||
#define DVFSRC_LEVEL_LABEL_78_79 (DVFSRC_BASE + 0x6CC)
|
||||
#define DVFSRC_LEVEL_LABEL_80_81 (DVFSRC_BASE + 0x6D0)
|
||||
#define DVFSRC_LEVEL_LABEL_82_83 (DVFSRC_BASE + 0x6D4)
|
||||
#define DVFSRC_LEVEL_LABEL_84_85 (DVFSRC_BASE + 0x6D8)
|
||||
#define DVFSRC_LEVEL_LABEL_86_87 (DVFSRC_BASE + 0x6DC)
|
||||
#define DVFSRC_LEVEL_LABEL_88_89 (DVFSRC_BASE + 0x6E0)
|
||||
#define DVFSRC_LEVEL_LABEL_90_91 (DVFSRC_BASE + 0x6E4)
|
||||
#define DVFSRC_LEVEL_LABEL_92_93 (DVFSRC_BASE + 0x6E8)
|
||||
#define DVFSRC_LEVEL_LABEL_94_95 (DVFSRC_BASE + 0x6EC)
|
||||
#define DVFSRC_LEVEL_LABEL_96_97 (DVFSRC_BASE + 0x6F0)
|
||||
#define DVFSRC_LEVEL_LABEL_98_99 (DVFSRC_BASE + 0x6F4)
|
||||
#define DVFSRC_LEVEL_LABEL_100_101 (DVFSRC_BASE + 0x6F8)
|
||||
#define DVFSRC_LEVEL_LABEL_102_103 (DVFSRC_BASE + 0x6FC)
|
||||
#define DVFSRC_LEVEL_LABEL_104_105 (DVFSRC_BASE + 0x700)
|
||||
#define DVFSRC_LEVEL_LABEL_106_107 (DVFSRC_BASE + 0x704)
|
||||
#define DVFSRC_LEVEL_LABEL_108_109 (DVFSRC_BASE + 0x708)
|
||||
#define DVFSRC_LEVEL_LABEL_110_111 (DVFSRC_BASE + 0x70C)
|
||||
#define DVFSRC_LEVEL_LABEL_112_113 (DVFSRC_BASE + 0x710)
|
||||
#define DVFSRC_LEVEL_LABEL_114_115 (DVFSRC_BASE + 0x714)
|
||||
#define DVFSRC_LEVEL_LABEL_116_117 (DVFSRC_BASE + 0x718)
|
||||
#define DVFSRC_LEVEL_LABEL_118_119 (DVFSRC_BASE + 0x71C)
|
||||
#define DVFSRC_LEVEL_LABEL_120_121 (DVFSRC_BASE + 0x720)
|
||||
#define DVFSRC_LEVEL_LABEL_122_123 (DVFSRC_BASE + 0x724)
|
||||
#define DVFSRC_LEVEL_LABEL_124_125 (DVFSRC_BASE + 0x728)
|
||||
#define DVFSRC_LEVEL_LABEL_126_127 (DVFSRC_BASE + 0x72C)
|
||||
#define DVFSRC_LEVEL_MASK_MD_3 (DVFSRC_BASE + 0x738)
|
||||
#define DVFSRC_LEVEL_MASK_MD_4 (DVFSRC_BASE + 0x73C)
|
||||
#define DVFSRC_DEFAULT_OPP_3 (DVFSRC_BASE + 0x740)
|
||||
#define DVFSRC_DEFAULT_OPP_4 (DVFSRC_BASE + 0x744)
|
||||
#define DVFSRC_LEVEL_MASK_SW_3 (DVFSRC_BASE + 0x748)
|
||||
#define DVFSRC_LEVEL_MASK_SW_4 (DVFSRC_BASE + 0x74C)
|
||||
#define DVFSRC_TARGET_LEVEL_SPM_3 (DVFSRC_BASE + 0x750)
|
||||
#define DVFSRC_TARGET_LEVEL_SPM_4 (DVFSRC_BASE + 0x754)
|
||||
#define DVFSRC_CURRENT_LEVEL_3 (DVFSRC_BASE + 0x758)
|
||||
#define DVFSRC_CURRENT_LEVEL_4 (DVFSRC_BASE + 0x75C)
|
||||
#define DVFSRC_TARGET_LEVEL_3 (DVFSRC_BASE + 0x760)
|
||||
#define DVFSRC_TARGET_LEVEL_4 (DVFSRC_BASE + 0x764)
|
||||
#define DVFSRC_CURRENT_FORCE_3 (DVFSRC_BASE + 0x768)
|
||||
#define DVFSRC_CURRENT_FORCE_4 (DVFSRC_BASE + 0x76C)
|
||||
#define DVFSRC_TARGET_FORCE_3 (DVFSRC_BASE + 0x770)
|
||||
#define DVFSRC_TARGET_FORCE_4 (DVFSRC_BASE + 0x774)
|
||||
#define DVFSRC_DDR_REQUEST10 (DVFSRC_BASE + 0x778)
|
||||
#define DVFSRC_EMI_REQUEST10 (DVFSRC_BASE + 0x77C)
|
||||
#define DVFSRC_DDR_REQUEST11 (DVFSRC_BASE + 0x780)
|
||||
#define DVFSRC_EMI_REQUEST11 (DVFSRC_BASE + 0x784)
|
||||
#define DVFSRC_TARGET_FORCE_5 (DVFSRC_BASE + 0x788)
|
||||
#define DVFSRC_TARGET_FORCE_6 (DVFSRC_BASE + 0x78C)
|
||||
#define DVFSRC_TARGET_FORCE_7 (DVFSRC_BASE + 0x790)
|
||||
#define DVFSRC_TARGET_FORCE_8 (DVFSRC_BASE + 0x794)
|
||||
#define DVFSRC_PMQOS_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x798)
|
||||
#define DVFSRC_DISP_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x79C)
|
||||
#define DVFSRC_ISP_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x7A0)
|
||||
#define DVFSRC_MD_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x7A4)
|
||||
#define DVFSRC_HRT_BASE_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x7A8)
|
||||
#define DVFSRC_APU_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x7AC)
|
||||
#define DVFSRC_SMMU_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x7B0)
|
||||
#define DVFSRC_SMAP_CG_SET (DVFSRC_BASE + 0x814)
|
||||
#define DVFSRC_LEVEL_MASK_MD_5 (DVFSRC_BASE + 0x818)
|
||||
#define DVFSRC_LEVEL_MASK_MD_6 (DVFSRC_BASE + 0x81C)
|
||||
#define DVFSRC_LEVEL_MASK_MD_7 (DVFSRC_BASE + 0x820)
|
||||
#define DVFSRC_LEVEL_MASK_MD_8 (DVFSRC_BASE + 0x824)
|
||||
#define DVFSRC_DEFAULT_OPP_5 (DVFSRC_BASE + 0x828)
|
||||
#define DVFSRC_DEFAULT_OPP_6 (DVFSRC_BASE + 0x82C)
|
||||
#define DVFSRC_DEFAULT_OPP_7 (DVFSRC_BASE + 0x830)
|
||||
#define DVFSRC_DEFAULT_OPP_8 (DVFSRC_BASE + 0x834)
|
||||
#define DVFSRC_LEVEL_MASK_SW_5 (DVFSRC_BASE + 0x838)
|
||||
#define DVFSRC_LEVEL_MASK_SW_6 (DVFSRC_BASE + 0x83C)
|
||||
#define DVFSRC_LEVEL_MASK_SW_7 (DVFSRC_BASE + 0x840)
|
||||
#define DVFSRC_LEVEL_MASK_SW_8 (DVFSRC_BASE + 0x844)
|
||||
#define DVFSRC_TARGET_LEVEL_SPM_5 (DVFSRC_BASE + 0x848)
|
||||
#define DVFSRC_TARGET_LEVEL_SPM_6 (DVFSRC_BASE + 0x84C)
|
||||
#define DVFSRC_TARGET_LEVEL_SPM_7 (DVFSRC_BASE + 0x850)
|
||||
#define DVFSRC_TARGET_LEVEL_SPM_8 (DVFSRC_BASE + 0x854)
|
||||
#define DVFSRC_CURRENT_LEVEL_5 (DVFSRC_BASE + 0x858)
|
||||
#define DVFSRC_CURRENT_LEVEL_6 (DVFSRC_BASE + 0x85C)
|
||||
#define DVFSRC_CURRENT_LEVEL_7 (DVFSRC_BASE + 0x860)
|
||||
#define DVFSRC_CURRENT_LEVEL_8 (DVFSRC_BASE + 0x864)
|
||||
#define DVFSRC_TARGET_LEVEL_5 (DVFSRC_BASE + 0x868)
|
||||
#define DVFSRC_TARGET_LEVEL_6 (DVFSRC_BASE + 0x86C)
|
||||
#define DVFSRC_TARGET_LEVEL_7 (DVFSRC_BASE + 0x870)
|
||||
#define DVFSRC_TARGET_LEVEL_8 (DVFSRC_BASE + 0x874)
|
||||
#define DVFSRC_CURRENT_FORCE_5 (DVFSRC_BASE + 0x878)
|
||||
#define DVFSRC_CURRENT_FORCE_6 (DVFSRC_BASE + 0x87C)
|
||||
#define DVFSRC_CURRENT_FORCE_7 (DVFSRC_BASE + 0x880)
|
||||
#define DVFSRC_CURRENT_FORCE_8 (DVFSRC_BASE + 0x884)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_11 (DVFSRC_BASE + 0x88C)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_12 (DVFSRC_BASE + 0x890)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_13 (DVFSRC_BASE + 0x894)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_14 (DVFSRC_BASE + 0x898)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_15 (DVFSRC_BASE + 0x89C)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_16 (DVFSRC_BASE + 0x8A0)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_17 (DVFSRC_BASE + 0x8A4)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_18 (DVFSRC_BASE + 0x8A8)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_19 (DVFSRC_BASE + 0x8AC)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_20 (DVFSRC_BASE + 0x8B0)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_21 (DVFSRC_BASE + 0x8B4)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_11 (DVFSRC_BASE + 0x8B8)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_12 (DVFSRC_BASE + 0x8BC)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_13 (DVFSRC_BASE + 0x8C0)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_14 (DVFSRC_BASE + 0x8C4)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_15 (DVFSRC_BASE + 0x8C8)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_16 (DVFSRC_BASE + 0x8CC)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_17 (DVFSRC_BASE + 0x8D0)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_18 (DVFSRC_BASE + 0x8D4)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_19 (DVFSRC_BASE + 0x8D8)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_20 (DVFSRC_BASE + 0x8DC)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_21 (DVFSRC_BASE + 0x8E0)
|
||||
#define DVFSRC_95MD_SCEN_EMI4 (DVFSRC_BASE + 0x904)
|
||||
#define DVFSRC_95MD_SCEN_EMI5 (DVFSRC_BASE + 0x908)
|
||||
#define DVFSRC_95MD_SCEN_EMI6 (DVFSRC_BASE + 0x90C)
|
||||
#define DVFSRC_95MD_SCEN_EMI7 (DVFSRC_BASE + 0x910)
|
||||
#define DVFSRC_95MD_SCEN_EMI4_T (DVFSRC_BASE + 0x914)
|
||||
#define DVFSRC_95MD_SCEN_EMI5_T (DVFSRC_BASE + 0x918)
|
||||
#define DVFSRC_95MD_SCEN_EMI6_T (DVFSRC_BASE + 0x91C)
|
||||
#define DVFSRC_95MD_SCEN_EMI7_T (DVFSRC_BASE + 0x920)
|
||||
#define DVFSRC_95MD_SCEN_BW4 (DVFSRC_BASE + 0x924)
|
||||
#define DVFSRC_95MD_SCEN_BW5 (DVFSRC_BASE + 0x928)
|
||||
#define DVFSRC_95MD_SCEN_BW6 (DVFSRC_BASE + 0x92C)
|
||||
#define DVFSRC_95MD_SCEN_BW7 (DVFSRC_BASE + 0x930)
|
||||
#define DVFSRC_95MD_SCEN_BW4_T (DVFSRC_BASE + 0x934)
|
||||
#define DVFSRC_95MD_SCEN_BW5_T (DVFSRC_BASE + 0x938)
|
||||
#define DVFSRC_95MD_SCEN_BW6_T (DVFSRC_BASE + 0x93C)
|
||||
#define DVFSRC_95MD_SCEN_BW7_T (DVFSRC_BASE + 0x940)
|
||||
#define DVFSRC_LEVEL_LABEL_128_129 (DVFSRC_BASE + 0x944)
|
||||
#define DVFSRC_LEVEL_LABEL_130_131 (DVFSRC_BASE + 0x948)
|
||||
#define DVFSRC_LEVEL_LABEL_132_133 (DVFSRC_BASE + 0x94C)
|
||||
#define DVFSRC_LEVEL_LABEL_134_135 (DVFSRC_BASE + 0x950)
|
||||
#define DVFSRC_LEVEL_LABEL_136_137 (DVFSRC_BASE + 0x954)
|
||||
#define DVFSRC_LEVEL_LABEL_138_139 (DVFSRC_BASE + 0x958)
|
||||
#define DVFSRC_LEVEL_LABEL_140_141 (DVFSRC_BASE + 0x95C)
|
||||
#define DVFSRC_LEVEL_LABEL_142_143 (DVFSRC_BASE + 0x960)
|
||||
#define DVFSRC_LEVEL_LABEL_144_145 (DVFSRC_BASE + 0x964)
|
||||
#define DVFSRC_LEVEL_LABEL_146_147 (DVFSRC_BASE + 0x968)
|
||||
#define DVFSRC_LEVEL_LABEL_148_149 (DVFSRC_BASE + 0x96C)
|
||||
#define DVFSRC_LEVEL_LABEL_150_151 (DVFSRC_BASE + 0x970)
|
||||
#define DVFSRC_LEVEL_LABEL_152_153 (DVFSRC_BASE + 0x974)
|
||||
#define DVFSRC_LEVEL_LABEL_154_155 (DVFSRC_BASE + 0x978)
|
||||
#define DVFSRC_LEVEL_LABEL_156_157 (DVFSRC_BASE + 0x97C)
|
||||
#define DVFSRC_LEVEL_LABEL_158_159 (DVFSRC_BASE + 0x980)
|
||||
#define DVFSRC_LEVEL_LABEL_160_161 (DVFSRC_BASE + 0x984)
|
||||
#define DVFSRC_LEVEL_LABEL_162_163 (DVFSRC_BASE + 0x988)
|
||||
#define DVFSRC_LEVEL_LABEL_164_165 (DVFSRC_BASE + 0x98C)
|
||||
#define DVFSRC_LEVEL_LABEL_166_167 (DVFSRC_BASE + 0x990)
|
||||
#define DVFSRC_LEVEL_LABEL_168_169 (DVFSRC_BASE + 0x994)
|
||||
#define DVFSRC_LEVEL_LABEL_170_171 (DVFSRC_BASE + 0x998)
|
||||
#define DVFSRC_LEVEL_LABEL_172_173 (DVFSRC_BASE + 0x99C)
|
||||
#define DVFSRC_LEVEL_LABEL_174_175 (DVFSRC_BASE + 0x9A0)
|
||||
#define DVFSRC_LEVEL_LABEL_176_177 (DVFSRC_BASE + 0x9A4)
|
||||
#define DVFSRC_LEVEL_LABEL_178_179 (DVFSRC_BASE + 0x9A8)
|
||||
#define DVFSRC_LEVEL_LABEL_180_181 (DVFSRC_BASE + 0x9AC)
|
||||
#define DVFSRC_LEVEL_LABEL_182_183 (DVFSRC_BASE + 0x9B0)
|
||||
#define DVFSRC_LEVEL_LABEL_184_185 (DVFSRC_BASE + 0x9B4)
|
||||
#define DVFSRC_LEVEL_LABEL_186_187 (DVFSRC_BASE + 0x9B8)
|
||||
#define DVFSRC_LEVEL_LABEL_188_189 (DVFSRC_BASE + 0x9BC)
|
||||
#define DVFSRC_LEVEL_LABEL_190_191 (DVFSRC_BASE + 0x9C0)
|
||||
#define DVFSRC_LEVEL_LABEL_192_193 (DVFSRC_BASE + 0x9C4)
|
||||
#define DVFSRC_LEVEL_LABEL_194_195 (DVFSRC_BASE + 0x9C8)
|
||||
#define DVFSRC_LEVEL_LABEL_196_197 (DVFSRC_BASE + 0x9CC)
|
||||
#define DVFSRC_LEVEL_LABEL_198_199 (DVFSRC_BASE + 0x9D0)
|
||||
#define DVFSRC_LEVEL_LABEL_200_201 (DVFSRC_BASE + 0x9D4)
|
||||
#define DVFSRC_LEVEL_LABEL_202_203 (DVFSRC_BASE + 0x9D8)
|
||||
#define DVFSRC_LEVEL_LABEL_204_205 (DVFSRC_BASE + 0x9DC)
|
||||
#define DVFSRC_LEVEL_LABEL_206_207 (DVFSRC_BASE + 0x9E0)
|
||||
#define DVFSRC_LEVEL_LABEL_208_209 (DVFSRC_BASE + 0x9E4)
|
||||
#define DVFSRC_LEVEL_LABEL_210_211 (DVFSRC_BASE + 0x9E8)
|
||||
#define DVFSRC_LEVEL_LABEL_212_213 (DVFSRC_BASE + 0x9EC)
|
||||
#define DVFSRC_LEVEL_LABEL_214_215 (DVFSRC_BASE + 0x9F0)
|
||||
#define DVFSRC_LEVEL_LABEL_216_217 (DVFSRC_BASE + 0x9F4)
|
||||
#define DVFSRC_LEVEL_LABEL_218_219 (DVFSRC_BASE + 0x9F8)
|
||||
#define DVFSRC_LEVEL_LABEL_220_221 (DVFSRC_BASE + 0x9FC)
|
||||
#define DVFSRC_LEVEL_LABEL_222_223 (DVFSRC_BASE + 0xA00)
|
||||
#define DVFSRC_LEVEL_LABEL_224_225 (DVFSRC_BASE + 0xA04)
|
||||
#define DVFSRC_LEVEL_LABEL_226_227 (DVFSRC_BASE + 0xA08)
|
||||
#define DVFSRC_LEVEL_LABEL_228_229 (DVFSRC_BASE + 0xA0C)
|
||||
#define DVFSRC_LEVEL_LABEL_230_231 (DVFSRC_BASE + 0xA10)
|
||||
#define DVFSRC_LEVEL_LABEL_232_233 (DVFSRC_BASE + 0xA14)
|
||||
#define DVFSRC_LEVEL_LABEL_234_235 (DVFSRC_BASE + 0xA18)
|
||||
#define DVFSRC_LEVEL_LABEL_236_237 (DVFSRC_BASE + 0xA1C)
|
||||
#define DVFSRC_LEVEL_LABEL_238_239 (DVFSRC_BASE + 0xA20)
|
||||
#define DVFSRC_LEVEL_LABEL_240_241 (DVFSRC_BASE + 0xA24)
|
||||
#define DVFSRC_LEVEL_LABEL_242_243 (DVFSRC_BASE + 0xA28)
|
||||
#define DVFSRC_LEVEL_LABEL_244_245 (DVFSRC_BASE + 0xA2C)
|
||||
#define DVFSRC_LEVEL_LABEL_246_247 (DVFSRC_BASE + 0xA30)
|
||||
#define DVFSRC_LEVEL_LABEL_248_249 (DVFSRC_BASE + 0xA34)
|
||||
#define DVFSRC_LEVEL_LABEL_250_251 (DVFSRC_BASE + 0xA38)
|
||||
#define DVFSRC_LEVEL_LABEL_252_253 (DVFSRC_BASE + 0xA3C)
|
||||
#define DVFSRC_LEVEL_LABEL_254_255 (DVFSRC_BASE + 0xA40)
|
||||
#define DVFSRC_HRT_HIGH_15 (DVFSRC_BASE + 0xA44)
|
||||
#define DVFSRC_HRT_HIGH_14 (DVFSRC_BASE + 0xA48)
|
||||
#define DVFSRC_HRT_HIGH_13 (DVFSRC_BASE + 0xA4C)
|
||||
#define DVFSRC_HRT_HIGH_12 (DVFSRC_BASE + 0xA50)
|
||||
#define DVFSRC_HRT_HIGH_11 (DVFSRC_BASE + 0xA54)
|
||||
#define DVFSRC_HRT_HIGH_10 (DVFSRC_BASE + 0xA58)
|
||||
#define DVFSRC_HRT_HIGH_9 (DVFSRC_BASE + 0xA5C)
|
||||
#define DVFSRC_HRT_HIGH_8 (DVFSRC_BASE + 0xA60)
|
||||
#define DVFSRC_HRT_LOW_15 (DVFSRC_BASE + 0xA64)
|
||||
#define DVFSRC_HRT_LOW_14 (DVFSRC_BASE + 0xA68)
|
||||
#define DVFSRC_HRT_LOW_13 (DVFSRC_BASE + 0xA6C)
|
||||
#define DVFSRC_HRT_LOW_12 (DVFSRC_BASE + 0xA70)
|
||||
#define DVFSRC_HRT_LOW_11 (DVFSRC_BASE + 0xA74)
|
||||
#define DVFSRC_HRT_LOW_10 (DVFSRC_BASE + 0xA78)
|
||||
#define DVFSRC_HRT_LOW_9 (DVFSRC_BASE + 0xA7C)
|
||||
#define DVFSRC_HRT_LOW_8 (DVFSRC_BASE + 0xA80)
|
||||
#define DVFSRC_DDR_QOS11 (DVFSRC_BASE + 0xA84)
|
||||
#define DVFSRC_DDR_QOS12 (DVFSRC_BASE + 0xA88)
|
||||
#define DVFSRC_DDR_QOS13 (DVFSRC_BASE + 0xA8C)
|
||||
#define DVFSRC_DDR_QOS14 (DVFSRC_BASE + 0xA90)
|
||||
#define DVFSRC_DDR_QOS15 (DVFSRC_BASE + 0xA94)
|
||||
#define DVFSRC_EMI_QOS11 (DVFSRC_BASE + 0xA98)
|
||||
#define DVFSRC_EMI_QOS12 (DVFSRC_BASE + 0xA9C)
|
||||
#define DVFSRC_EMI_QOS13 (DVFSRC_BASE + 0xAA0)
|
||||
#define DVFSRC_EMI_QOS14 (DVFSRC_BASE + 0xAA4)
|
||||
#define DVFSRC_EMI_QOS15 (DVFSRC_BASE + 0xAA8)
|
||||
#define DVFSRC_TARGET_REQ_MASK BIT(16)
|
||||
#define DVFSRC_EN_MASK 1
|
||||
#endif /* MT_SPM_VCOREFS_REG_6991_H */
|
||||
463
plat/mediatek/drivers/spm/mt8196/mt_vcore_dvfsrc_plat.c
Normal file
463
plat/mediatek/drivers/spm/mt8196/mt_vcore_dvfsrc_plat.c
Normal file
|
|
@ -0,0 +1,463 @@
|
|||
/*
|
||||
* Copyright (c) 2025, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <drivers/dbgtop.h>
|
||||
#include <drivers/dramc.h>
|
||||
#include <drivers/spmi/spmi_common.h>
|
||||
#include <drivers/spmi_api.h>
|
||||
#include <drivers/sramrc.h>
|
||||
#include <lib/mtk_init/mtk_init.h>
|
||||
#include <mt_plat_spm_setting.h>
|
||||
#include <mt_spm.h>
|
||||
#include <mt_spm_reg.h>
|
||||
#include <mt_spm_vcorefs.h>
|
||||
#include <mt_spm_vcorefs_common.h>
|
||||
#include <mt_spm_vcorefs_ext.h>
|
||||
#include <mt_spm_vcorefs_reg.h>
|
||||
#include <mt_vcore_dvfsrc_plat_def.h>
|
||||
#include <mtk_mmap_pool.h>
|
||||
#include <mtk_sip_svc.h>
|
||||
#include <pmic_wrap/inc/mt_spm_pmic_wrap.h>
|
||||
#include <sleep_def.h>
|
||||
|
||||
#define VCORE_SPM_INIT_PCM_FLAG (SPM_FLAG_RUN_COMMON_SCENARIO | \
|
||||
SPM_FLAG_DISABLE_VLP_PDN)
|
||||
|
||||
#define V_VB_EN BIT(5)
|
||||
#define V_DRM_ENABLE BIT(31)
|
||||
#define V_B0_EN_SHIFT BIT(23)
|
||||
|
||||
#define V_VMODE_SHIFT 0
|
||||
#define V_VMODE_MASK 0x3
|
||||
#define V_OPP_TYPE_SHIFT 20
|
||||
#define V_OPP_TYPE_SHIFT_MASK 0x3
|
||||
|
||||
#define DVFSRC_DISABLE_DVS 0x1
|
||||
#define DVFSRC_DISABLE_DFS 0x2
|
||||
|
||||
#define CFG_DVFSRC_BW_ASYM_ENABLE
|
||||
|
||||
#ifdef MT8196_VCORE_SUPPORT
|
||||
#define VCORE_MAX_OPP 6
|
||||
#define DRAM_MAX_OPP 11
|
||||
|
||||
#define VCORE_OPP0_UV 850000
|
||||
#define VCORE_OPP1_UV 750000
|
||||
#define VCORE_OPP2_UV 675000
|
||||
#define VCORE_OPP3_UV 625000
|
||||
#define VCORE_OPP4_UV 600000
|
||||
|
||||
static unsigned int v_opp_uv[VCORE_MAX_OPP] = {
|
||||
VCORE_OPP0_UV,
|
||||
VCORE_OPP0_UV,
|
||||
VCORE_OPP1_UV,
|
||||
VCORE_OPP2_UV,
|
||||
VCORE_OPP3_UV,
|
||||
VCORE_OPP4_UV
|
||||
};
|
||||
|
||||
#else
|
||||
#define VCORE_MAX_OPP 6
|
||||
#define DRAM_MAX_OPP 11
|
||||
|
||||
#define VCORE_OPP0_UV 875000
|
||||
#define VCORE_OPP1_UV 825000
|
||||
#define VCORE_OPP2_UV 725000
|
||||
#define VCORE_OPP3_UV 650000
|
||||
#define VCORE_OPP4_UV 600000
|
||||
#define VCORE_OPP5_UV 575000
|
||||
|
||||
static unsigned int v_opp_uv[VCORE_MAX_OPP] = {
|
||||
VCORE_OPP0_UV,
|
||||
VCORE_OPP1_UV,
|
||||
VCORE_OPP2_UV,
|
||||
VCORE_OPP3_UV,
|
||||
VCORE_OPP4_UV,
|
||||
VCORE_OPP5_UV,
|
||||
};
|
||||
|
||||
static unsigned int v_opp_df_uv[VCORE_MAX_OPP] = {
|
||||
VCORE_OPP0_UV,
|
||||
VCORE_OPP1_UV,
|
||||
VCORE_OPP2_UV,
|
||||
VCORE_OPP3_UV,
|
||||
VCORE_OPP4_UV,
|
||||
VCORE_OPP5_UV,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MTK_VCOREDVFS_SUPPORT
|
||||
static int opp_type;
|
||||
static unsigned int b0_en;
|
||||
|
||||
static unsigned int v_roundup(unsigned int x, unsigned int y)
|
||||
{
|
||||
return round_up(x, y);
|
||||
}
|
||||
|
||||
static unsigned int v_rounddown(unsigned int x, unsigned int y)
|
||||
{
|
||||
return round_down(x, y);
|
||||
}
|
||||
|
||||
static void spm_vcorefs_pwarp_cmd(uint64_t cmd, uint64_t val)
|
||||
{
|
||||
if (cmd < NR_IDX_ALL)
|
||||
mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val);
|
||||
else
|
||||
INFO("cmd out of range!\n");
|
||||
}
|
||||
|
||||
static void dvfsrc_init(void)
|
||||
{
|
||||
int i;
|
||||
static int dvfs_enable_done;
|
||||
|
||||
if (dvfs_enable_done)
|
||||
return;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dvfsrc_init_configs); i++)
|
||||
mmio_write_32(dvfsrc_init_configs[i].offset,
|
||||
dvfsrc_init_configs[i].val);
|
||||
|
||||
#ifdef MT8196_VCORE_SUPPORT
|
||||
for (i = 0; i < ARRAY_SIZE(lp5_8533_init_configs_auto); i++)
|
||||
mmio_write_32(lp5_8533_init_configs_auto[i].offset,
|
||||
lp5_8533_init_configs_auto[i].val);
|
||||
#endif
|
||||
|
||||
if (opp_type == 2) {
|
||||
for (i = 0; i < ARRAY_SIZE(lp5_7500_init_configs); i++)
|
||||
mmio_write_32(lp5_7500_init_configs[i].offset,
|
||||
lp5_7500_init_configs[i].val);
|
||||
} else if (opp_type == 0) {
|
||||
for (i = 0; i < ARRAY_SIZE(lp5_8533_init_configs); i++)
|
||||
mmio_write_32(lp5_8533_init_configs[i].offset,
|
||||
lp5_8533_init_configs[i].val);
|
||||
} else if (opp_type == 3) {
|
||||
for (i = 0; i < ARRAY_SIZE(lp5_10677_init_configs); i++)
|
||||
mmio_write_32(lp5_10677_init_configs[i].offset,
|
||||
lp5_10677_init_configs[i].val);
|
||||
}
|
||||
#ifdef CFG_DVFSRC_BW_ASYM_ENABLE
|
||||
if (b0_en) {
|
||||
mmio_write_32(DVFSRC_LEVEL_LABEL_210_211, 0x20100000);
|
||||
mmio_write_32(DVFSRC_LEVEL_LABEL_212_213, 0x00504030);
|
||||
mmio_write_32(DVFSRC_LEVEL_LABEL_220_221, 0x00400000);
|
||||
mmio_write_32(DVFSRC_LEVEL_LABEL_224_225, 0x00000050);
|
||||
mmio_write_32(DVFSRC_LEVEL_LABEL_226_227, 0x00300000);
|
||||
mmio_write_32(DVFSRC_LEVEL_LABEL_252_253, 0x000040F5);
|
||||
mmio_write_32(DVFSRC_LEVEL_LABEL_248_249, 0x30450000);
|
||||
mmio_write_32(DVFSRC_LEVEL_LABEL_246_247, 0x00002065);
|
||||
mmio_write_32(DVFSRC_LEVEL_LABEL_242_243, 0x10960000);
|
||||
mmio_write_32(DVFSRC_LEVEL_LABEL_202_203, 0x00010040);
|
||||
mmio_write_32(DVFSRC_LEVEL_LABEL_200_201, 0xE0420030);
|
||||
}
|
||||
#endif
|
||||
|
||||
mmio_write_32(DVFSRC_SW_REQ4, 0x00000030);
|
||||
/* ENABLE */
|
||||
mmio_write_32(DVFSRC_CURRENT_FORCE_4, 0x00000001);
|
||||
#ifdef MT8196_VCORE_SUPPORT
|
||||
mmio_write_32(DVFSRC_BASIC_CONTROL, 0xD460213B);
|
||||
mmio_write_32(DVFSRC_BASIC_CONTROL, 0xD46001BB);
|
||||
#else
|
||||
mmio_write_32(DVFSRC_BASIC_CONTROL, 0xD560213B);
|
||||
mmio_write_32(DVFSRC_BASIC_CONTROL, 0xD56001BB);
|
||||
#endif
|
||||
mmio_write_32(DVFSRC_CURRENT_FORCE_4, 0x00000000);
|
||||
|
||||
#ifdef CONFIG_MTK_DBGTOP
|
||||
mtk_dbgtop_cfg_dvfsrc(1);
|
||||
#endif
|
||||
dvfs_enable_done = 1;
|
||||
}
|
||||
|
||||
static void spm_vcorefs_vcore_setting(void)
|
||||
{
|
||||
int i;
|
||||
uint32_t dvfs_v_mode, dvfsrc_rsrv;
|
||||
#ifndef MT8196_VCORE_SUPPORT
|
||||
uint32_t rsrv0, rsrv1;
|
||||
|
||||
rsrv0 = mmio_read_32(DVFSRC_RSRV_0);
|
||||
rsrv1 = mmio_read_32(DVFSRC_RSRV_1);
|
||||
#endif
|
||||
dvfsrc_rsrv = mmio_read_32(DVFSRC_RSRV_4);
|
||||
dvfs_v_mode = (dvfsrc_rsrv >> V_VMODE_SHIFT) & V_VMODE_MASK;
|
||||
|
||||
if (dvfs_v_mode == 3) { /* LV */
|
||||
for (i = 0; i < VCORE_MAX_OPP; i++)
|
||||
v_opp_uv[i] =
|
||||
v_rounddown((v_opp_uv[i] * 95) / 100,
|
||||
VCORE_STEP_UV);
|
||||
} else if (dvfs_v_mode == 1) { /* HV */
|
||||
for (i = 0; i < VCORE_MAX_OPP; i++)
|
||||
v_opp_uv[i] =
|
||||
v_roundup((v_opp_uv[i] * 105) / 100,
|
||||
VCORE_STEP_UV);
|
||||
}
|
||||
#ifndef MT8196_VCORE_SUPPORT
|
||||
else if (dvfsrc_rsrv & V_VB_EN) { /* NV & AVS1.0 */
|
||||
v_opp_uv[5] = VCORE_PMIC_TO_UV(((rsrv1 >> 24) & 0xFF) + 7);
|
||||
v_opp_uv[4] = VCORE_PMIC_TO_UV(((rsrv1 >> 16) & 0xFF) + 5);
|
||||
v_opp_uv[3] = VCORE_PMIC_TO_UV(((rsrv1 >> 8) & 0xFF) + 4);
|
||||
v_opp_uv[2] = VCORE_PMIC_TO_UV(((rsrv0 >> 24) & 0xFF) + 4);
|
||||
v_opp_uv[1] = VCORE_PMIC_TO_UV(((rsrv0 >> 16) & 0xFF) + 3);
|
||||
v_opp_uv[0] = VCORE_PMIC_TO_UV((rsrv0 & 0xFF) + 3);
|
||||
for (i = 0; i < VCORE_MAX_OPP; i++)
|
||||
v_opp_uv[i] = v_min(v_opp_uv[i], v_opp_df_uv[i]);
|
||||
}
|
||||
#endif
|
||||
#ifdef MT8196_VCORE_SUPPORT
|
||||
spm_vcorefs_pwarp_cmd(CMD_0, VCORE_UV_TO_PMIC(v_opp_uv[5]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_1, VCORE_UV_TO_PMIC(v_opp_uv[5]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_2, VCORE_UV_TO_PMIC(v_opp_uv[4]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_3, VCORE_UV_TO_PMIC(v_opp_uv[3]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_4, VCORE_UV_TO_PMIC(v_opp_uv[2]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_5, VCORE_UV_TO_PMIC(v_opp_uv[2]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_6, VCORE_UV_TO_PMIC(v_opp_uv[1]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_7, VCORE_UV_TO_PMIC(v_opp_uv[1]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_8, VCORE_UV_TO_PMIC(v_opp_uv[0]));
|
||||
|
||||
spm_vcorefs_pwarp_cmd(CMD_9, VCORE_UV_TO_PMIC(v_opp_uv[5]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_10, VCORE_UV_TO_PMIC(v_opp_uv[4]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_11, VCORE_UV_TO_PMIC(v_opp_uv[3]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_12, VCORE_UV_TO_PMIC(v_opp_uv[2]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_13, VCORE_UV_TO_PMIC(v_opp_uv[1]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_14, VCORE_UV_TO_PMIC(v_opp_uv[0]));
|
||||
#else
|
||||
spm_vcorefs_pwarp_cmd(CMD_9, VCORE_UV_TO_PMIC(v_opp_uv[5]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_10, VCORE_UV_TO_PMIC(v_opp_uv[4]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_11, VCORE_UV_TO_PMIC(v_opp_uv[3]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_12, VCORE_UV_TO_PMIC(v_opp_uv[2]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_13, VCORE_UV_TO_PMIC(v_opp_uv[1]));
|
||||
spm_vcorefs_pwarp_cmd(CMD_14, VCORE_UV_TO_PMIC(v_opp_uv[0]));
|
||||
#endif
|
||||
}
|
||||
|
||||
int spm_vcorefs_plat_init(uint32_t dvfsrc_flag,
|
||||
uint32_t dvfsrc_vmode, uint32_t *dram_type)
|
||||
{
|
||||
uint64_t spm_flags = VCORE_SPM_INIT_PCM_FLAG;
|
||||
uint32_t dvfsrc_rsrv = 0;
|
||||
|
||||
if (mmio_read_32(MD32PCM_PC) == 0)
|
||||
return MTK_SIP_E_NOT_SUPPORTED;
|
||||
/* set high opp */
|
||||
mmio_write_32(DVFSRC_SW_BW_9, 0x3FF);
|
||||
spm_dvfsfw_init(0, 0);
|
||||
spm_vcorefs_vcore_setting();
|
||||
dvfsrc_rsrv = mmio_read_32(DVFSRC_RSRV_4);
|
||||
opp_type = (dvfsrc_rsrv >> V_OPP_TYPE_SHIFT) & V_OPP_TYPE_SHIFT_MASK;
|
||||
b0_en = dvfsrc_rsrv & V_B0_EN_SHIFT;
|
||||
|
||||
if (dvfsrc_flag & DVFSRC_DISABLE_DVS)
|
||||
spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
|
||||
|
||||
if (dvfsrc_flag & DVFSRC_DISABLE_DFS) {
|
||||
spm_flags |= (SPM_FLAG_DISABLE_DDR_DFS |
|
||||
SPM_FLAG_DISABLE_EMI_DFS |
|
||||
SPM_FLAG_DISABLE_BUS_DFS);
|
||||
mmio_write_32(DVFSRC_SW_BW_8, 0x3FF);
|
||||
}
|
||||
|
||||
if (dvfsrc_rsrv & V_DRM_ENABLE) {
|
||||
spm_flags |= (SPM_FLAG_DISABLE_VCORE_DVS |
|
||||
SPM_FLAG_DISABLE_DDR_DFS |
|
||||
SPM_FLAG_DISABLE_EMI_DFS |
|
||||
SPM_FLAG_DISABLE_BUS_DFS);
|
||||
return MTK_SIP_E_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
spm_go_to_vcorefs(spm_flags);
|
||||
dvfsrc_init();
|
||||
*dram_type = 0;
|
||||
|
||||
return VCOREFS_SUCCESS;
|
||||
}
|
||||
|
||||
int spm_vcorefs_plat_kick(void)
|
||||
{
|
||||
/* release high opp if not in drm mode*/
|
||||
if (!(mmio_read_32(DVFSRC_RSRV_4) & V_DRM_ENABLE))
|
||||
mmio_write_32(DVFSRC_SW_BW_9, 0);
|
||||
|
||||
mmio_write_32(DVFSRC_AVS_RETRY, 1);
|
||||
mmio_write_32(DVFSRC_AVS_RETRY, 0);
|
||||
|
||||
return VCOREFS_SUCCESS;
|
||||
}
|
||||
|
||||
void spm_vcorefs_plat_suspend(void)
|
||||
{
|
||||
mmio_write_32(DVFSRC_MD_TURBO, 0x1FFF0000);
|
||||
}
|
||||
|
||||
void spm_vcorefs_plat_resume(void)
|
||||
{
|
||||
mmio_write_32(DVFSRC_MD_TURBO, 0x00000000);
|
||||
}
|
||||
|
||||
#else
|
||||
int spm_vcorefs_plat_kick(void)
|
||||
{
|
||||
return MTK_SIP_E_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
int spm_vcorefs_plat_init(uint32_t dvfsrc_flag,
|
||||
uint32_t dvfsrc_vmode, uint32_t *dram_type)
|
||||
{
|
||||
return MTK_SIP_E_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
void spm_vcorefs_plat_suspend(void)
|
||||
{
|
||||
}
|
||||
|
||||
void spm_vcorefs_plat_resume(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
int spm_vcorefs_get_vcore_uv(uint32_t gear, uint32_t *val)
|
||||
{
|
||||
if (gear < VCORE_MAX_OPP)
|
||||
*val = v_opp_uv[VCORE_MAX_OPP - gear - 1];
|
||||
else
|
||||
*val = 0;
|
||||
|
||||
return VCOREFS_SUCCESS;
|
||||
}
|
||||
|
||||
int spm_vcorefs_get_dram_freq(uint32_t gear, uint32_t *val)
|
||||
{
|
||||
#ifdef CONFIG_MTK_DRAMC
|
||||
if (gear < DRAM_MAX_OPP)
|
||||
*val = get_dram_step_freq((DRAM_MAX_OPP - gear - 1)) * 1000;
|
||||
else
|
||||
*val = 0;
|
||||
#else
|
||||
*val = 0;
|
||||
#endif
|
||||
return VCOREFS_SUCCESS;
|
||||
}
|
||||
|
||||
int spm_vcorefs_get_vcore_opp_num(uint32_t *val)
|
||||
{
|
||||
*val = VCORE_MAX_OPP;
|
||||
|
||||
return VCOREFS_SUCCESS;
|
||||
}
|
||||
|
||||
int spm_vcorefs_get_dram_opp_num(uint32_t *val)
|
||||
{
|
||||
*val = DRAM_MAX_OPP;
|
||||
|
||||
return VCOREFS_SUCCESS;
|
||||
}
|
||||
|
||||
int spm_vcorefs_get_opp_type(uint32_t *val)
|
||||
{
|
||||
*val = 0;
|
||||
|
||||
return VCOREFS_SUCCESS;
|
||||
}
|
||||
|
||||
int spm_vcorefs_get_fw_type(uint32_t *val)
|
||||
{
|
||||
*val = 0;
|
||||
|
||||
return VCOREFS_SUCCESS;
|
||||
}
|
||||
|
||||
int spm_vcorefs_get_vcore_info(uint32_t idx, uint32_t *data)
|
||||
{
|
||||
if (idx == 0)
|
||||
*data = mmio_read_32(VCORE_VB_INFO0);
|
||||
else if (idx == 1)
|
||||
*data = mmio_read_32(VCORE_VB_INFO1);
|
||||
else if (idx == 2)
|
||||
*data = mmio_read_32(VCORE_VB_INFO2);
|
||||
else
|
||||
*data = 0;
|
||||
|
||||
return VCOREFS_SUCCESS;
|
||||
}
|
||||
|
||||
#define MMPC_FLAG 0x3333
|
||||
int spm_vcorefs_qos_mode(uint32_t data)
|
||||
{
|
||||
#ifdef CFG_DVFSRC_BW_ASYM_ENABLE
|
||||
uint32_t mode, value;
|
||||
bool mm_flag;
|
||||
|
||||
mm_flag = (mmio_read_32(DVFSRC_VCORE_QOS7) == 0xFFFFFE);
|
||||
mode = data >> 16;
|
||||
|
||||
if ((mode == 0x3333) && b0_en && mm_flag) {
|
||||
value = data & 0xFFFF;
|
||||
if (value == 1)
|
||||
mmio_write_32(DVFSRC_QOS_EN, 0x00F3007C);
|
||||
else
|
||||
mmio_write_32(DVFSRC_QOS_EN, 0x20F1007C);
|
||||
return VCOREFS_SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
return MTK_SIP_E_NOT_SUPPORTED;
|
||||
|
||||
}
|
||||
|
||||
int spm_vcorefs_pause_enable(uint32_t enable)
|
||||
{
|
||||
#ifdef CONFIG_MTK_DBGTOP
|
||||
mtk_dbgtop_dfd_pause_dvfsrc(1);
|
||||
#endif
|
||||
|
||||
return VCOREFS_SUCCESS;
|
||||
}
|
||||
|
||||
#ifdef MTK_VCORE_DVFS_RES_MEM
|
||||
static int vcorefs_rsc_ctrl(unsigned int rsc, bool hold)
|
||||
{
|
||||
static struct mt_lp_resource_user vcorefs_res_user;
|
||||
int ret = -1;
|
||||
|
||||
if (!vcorefs_res_user.uid) {
|
||||
ret = mt_lp_resource_user_register("VCOREFS",
|
||||
&vcorefs_res_user);
|
||||
if (ret) {
|
||||
WARN("%s: register lp resource failed", __func__);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if (hold)
|
||||
ret = vcorefs_res_user.request(&vcorefs_res_user, rsc);
|
||||
else
|
||||
ret = vcorefs_res_user.release(&vcorefs_res_user);
|
||||
|
||||
if (ret)
|
||||
WARN("%s: RSC_%d %s failed",
|
||||
__func__, rsc, hold ? "req" : "rel");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int spm_vcorefs_rsc_mem_req(bool request)
|
||||
{
|
||||
vcorefs_rsc_ctrl(MT_LP_RQ_DRAM, request);
|
||||
|
||||
return VCOREFS_SUCCESS;
|
||||
}
|
||||
#endif
|
||||
245
plat/mediatek/drivers/spm/mt8196/mt_vcore_dvfsrc_plat_def.h
Normal file
245
plat/mediatek/drivers/spm/mt8196/mt_vcore_dvfsrc_plat_def.h
Normal file
|
|
@ -0,0 +1,245 @@
|
|||
/*
|
||||
* Copyright (c) 2025, Mediatek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_VCORE_DVFSRC_PLAT_DEF_H
|
||||
#define MT_VCORE_DVFSRC_PLAT_DEF_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#ifdef MT8196_VCORE_SUPPORT
|
||||
#define VCORE_BASE_UV 0
|
||||
#define VCORE_STEP_UV 6250
|
||||
|
||||
/* PMIC */
|
||||
#define VCORE_PMIC_TO_UV(pmic) \
|
||||
(((pmic) * VCORE_STEP_UV) + VCORE_BASE_UV)
|
||||
#define VCORE_UV_TO_PMIC(uv) /* pmic >= uv */ \
|
||||
((((uv) - VCORE_BASE_UV) + (VCORE_STEP_UV - 1)) / VCORE_STEP_UV)
|
||||
#else
|
||||
#define VCORE_BASE_UV 0
|
||||
#define VCORE_STEP_UV 5000
|
||||
|
||||
/* PMIC */
|
||||
#define VCORE_PMIC_TO_UV(pmic) \
|
||||
(((pmic) * VCORE_STEP_UV) + VCORE_BASE_UV)
|
||||
#define VCORE_UV_TO_PMIC(uv) /* pmic >= uv */ \
|
||||
((((uv) - VCORE_BASE_UV) + (VCORE_STEP_UV - 1)) / VCORE_STEP_UV)
|
||||
|
||||
#ifndef v_min
|
||||
#define v_min(a, b) MIN(a, b)
|
||||
#endif
|
||||
|
||||
#ifndef v_max
|
||||
#define v_max(a, b) MAZ(a, b)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define VCORE_VB_INFO0 (EFUSEC_BASE + 0xD24)
|
||||
#define VCORE_VB_INFO1 (EFUSEC_BASE + 0xD28)
|
||||
#define VCORE_VB_INFO2 (EFUSEC_BASE + 0xD84)
|
||||
|
||||
static const struct reg_config dvfsrc_init_configs[] = {
|
||||
{ DVFSRC_TIMEOUT_NEXTREQ, 0x00001AFF },
|
||||
{ DVFSRC_VCORE_USER_REQ, 0x00010F51 },
|
||||
{ DVFSRC_BW_USER_REQ, 0x00010033 },
|
||||
/* EMI MONITOR */
|
||||
{ DVFSRC_DDR_REQUEST3, 0x44444321 },
|
||||
{ DVFSRC_DDR_REQUEST10, 0x44444321 },
|
||||
/* SW QOS */
|
||||
{ DVFSRC_QOS_EN, 0x20F1007C },
|
||||
{ DVFSRC_DDR_QOS0, 0x0000004B },
|
||||
{ DVFSRC_DDR_QOS1, 0x0000009A },
|
||||
{ DVFSRC_DDR_QOS2, 0x000000CE },
|
||||
{ DVFSRC_DDR_QOS3, 0x00000134 },
|
||||
{ DVFSRC_DDR_QOS4, 0x00000185 },
|
||||
{ DVFSRC_DDR_QOS5, 0x000001F9 },
|
||||
{ DVFSRC_DDR_QOS6, 0x0000024C },
|
||||
{ DVFSRC_DDR_QOS7, 0x000002B4 },
|
||||
{ DVFSRC_DDR_QOS8, 0x00000354 },
|
||||
{ DVFSRC_DDR_REQUEST5, 0x87654321 },
|
||||
{ DVFSRC_DDR_REQUEST8, 0x00000009 },
|
||||
/* LEVEL */
|
||||
{ DVFSRC_LEVEL_LABEL_0_1, 0x9055A055 },
|
||||
{ DVFSRC_LEVEL_LABEL_2_3, 0x80458055 },
|
||||
{ DVFSRC_LEVEL_LABEL_4_5, 0x70558044 },
|
||||
{ DVFSRC_LEVEL_LABEL_6_7, 0x70447045 },
|
||||
{ DVFSRC_LEVEL_LABEL_8_9, 0x60456055 },
|
||||
{ DVFSRC_LEVEL_LABEL_10_11, 0x60446035 },
|
||||
{ DVFSRC_LEVEL_LABEL_12_13, 0x60336034 },
|
||||
{ DVFSRC_LEVEL_LABEL_14_15, 0x50455055 },
|
||||
{ DVFSRC_LEVEL_LABEL_16_17, 0x50445035 },
|
||||
{ DVFSRC_LEVEL_LABEL_18_19, 0x50335034 },
|
||||
{ DVFSRC_LEVEL_LABEL_20_21, 0x40454055 },
|
||||
{ DVFSRC_LEVEL_LABEL_22_23, 0x40254035 },
|
||||
{ DVFSRC_LEVEL_LABEL_24_25, 0x40344044 },
|
||||
{ DVFSRC_LEVEL_LABEL_26_27, 0x40334024 },
|
||||
{ DVFSRC_LEVEL_LABEL_28_29, 0x40224023 },
|
||||
{ DVFSRC_LEVEL_LABEL_30_31, 0x30453055 },
|
||||
{ DVFSRC_LEVEL_LABEL_32_33, 0x30253035 },
|
||||
{ DVFSRC_LEVEL_LABEL_34_35, 0x30443015 },
|
||||
{ DVFSRC_LEVEL_LABEL_36_37, 0x30243034 },
|
||||
{ DVFSRC_LEVEL_LABEL_38_39, 0x30333014 },
|
||||
{ DVFSRC_LEVEL_LABEL_40_41, 0x30133023 },
|
||||
{ DVFSRC_LEVEL_LABEL_42_43, 0x30123022 },
|
||||
{ DVFSRC_LEVEL_LABEL_44_45, 0x20553011 },
|
||||
{ DVFSRC_LEVEL_LABEL_46_47, 0x20352045 },
|
||||
{ DVFSRC_LEVEL_LABEL_48_49, 0x20152025 },
|
||||
{ DVFSRC_LEVEL_LABEL_50_51, 0x20442005 },
|
||||
{ DVFSRC_LEVEL_LABEL_52_53, 0x20242034 },
|
||||
{ DVFSRC_LEVEL_LABEL_54_55, 0x20042014 },
|
||||
{ DVFSRC_LEVEL_LABEL_56_57, 0x20232033 },
|
||||
{ DVFSRC_LEVEL_LABEL_58_59, 0x20032013 },
|
||||
{ DVFSRC_LEVEL_LABEL_60_61, 0x20122022 },
|
||||
{ DVFSRC_LEVEL_LABEL_62_63, 0x20112002 },
|
||||
{ DVFSRC_LEVEL_LABEL_64_65, 0x20002001 },
|
||||
{ DVFSRC_LEVEL_LABEL_66_67, 0x10451055 },
|
||||
{ DVFSRC_LEVEL_LABEL_68_69, 0x10251035 },
|
||||
{ DVFSRC_LEVEL_LABEL_70_71, 0x10051015 },
|
||||
{ DVFSRC_LEVEL_LABEL_72_73, 0x10341044 },
|
||||
{ DVFSRC_LEVEL_LABEL_74_75, 0x10141024 },
|
||||
{ DVFSRC_LEVEL_LABEL_76_77, 0x10331004 },
|
||||
{ DVFSRC_LEVEL_LABEL_78_79, 0x10131023 },
|
||||
{ DVFSRC_LEVEL_LABEL_80_81, 0x10221003 },
|
||||
{ DVFSRC_LEVEL_LABEL_82_83, 0x10021012 },
|
||||
{ DVFSRC_LEVEL_LABEL_84_85, 0x10011011 },
|
||||
{ DVFSRC_LEVEL_LABEL_86_87, 0x00001000 },
|
||||
/* HRT */
|
||||
{ DVFSRC_PMQOS_HRT_UNIT_SW_BW, 0x00000120 },
|
||||
{ DVFSRC_ISP_HRT_UNIT_SW_BW, 0x0000010F },
|
||||
{ DVFSRC_MD_HRT_UNIT_SW_BW, 0x0000010F },
|
||||
{ DVFSRC_HRT_BASE_HRT_UNIT_SW_BW, 0x0000010F },
|
||||
{ DVFSRC_HRT_REQUEST, 0x87654321 },
|
||||
{ DVFSRC_HRT_REQUEST_1, 0x00000009 },
|
||||
{ DVFSRC_HRT_HIGH, 0x000006A8 },
|
||||
{ DVFSRC_HRT_HIGH_1, 0x00000DD7 },
|
||||
{ DVFSRC_HRT_HIGH_2, 0x000012A8 },
|
||||
{ DVFSRC_HRT_HIGH_3, 0x00001C0B },
|
||||
{ DVFSRC_HRT_HIGH_4, 0x00002644 },
|
||||
{ DVFSRC_HRT_HIGH_5, 0x000031AC },
|
||||
{ DVFSRC_HRT_HIGH_6, 0x000039FD },
|
||||
{ DVFSRC_HRT_HIGH_7, 0x00004435 },
|
||||
{ DVFSRC_HRT_HIGH_8, 0x000053B6 },
|
||||
{ DVFSRC_HRT_LOW, 0x000006A7 },
|
||||
{ DVFSRC_HRT_LOW_1, 0x00000DD7 },
|
||||
{ DVFSRC_HRT_LOW_2, 0x000012A8 },
|
||||
{ DVFSRC_HRT_LOW_3, 0x00001C0B },
|
||||
{ DVFSRC_HRT_LOW_4, 0x00002643 },
|
||||
{ DVFSRC_HRT_LOW_5, 0x000031AB },
|
||||
{ DVFSRC_HRT_LOW_6, 0x000039FD },
|
||||
{ DVFSRC_HRT_LOW_7, 0x00004435 },
|
||||
{ DVFSRC_HRT_LOW_8, 0x000053B6 },
|
||||
/* MDDDR */
|
||||
{ DVFSRC_HRT_REQ_MD_URG, 0x003FF3FF },
|
||||
{ DVFSRC_95MD_SCEN_BW7, 0x90000000 },
|
||||
{ DVFSRC_95MD_SCEN_BW7_T, 0x90000000 },
|
||||
{ DVFSRC_95MD_SCEN_BWU, 0x00000009 },
|
||||
{ DVFSRC_MD_LATENCY_IMPROVE, 0x00000021 },
|
||||
{ DVFSRC_DEBOUNCE_TIME, 0x0000179E },
|
||||
/* RISING */
|
||||
{ DVFSRC_DDR_ADD_REQUEST, 0x76543210 },
|
||||
{ DVFSRC_DDR_ADD_REQUEST_1, 0x99999998 },
|
||||
{ DVFSRC_EMI_MON_DEBOUNCE_TIME, 0x4C2D0000 },
|
||||
/* MISC */
|
||||
{ DVFSRC_DEFAULT_OPP_1, 0x00000000 },
|
||||
{ DVFSRC_DEFAULT_OPP_2, 0x00000000 },
|
||||
{ DVFSRC_DEFAULT_OPP_3, 0x00000000 },
|
||||
{ DVFSRC_DEFAULT_OPP_4, 0x00000000 },
|
||||
{ DVFSRC_DEFAULT_OPP_5, 0x00000000 },
|
||||
{ DVFSRC_DEFAULT_OPP_6, 0x00000000 },
|
||||
{ DVFSRC_DEFAULT_OPP_7, 0x00000000 },
|
||||
{ DVFSRC_DEFAULT_OPP_8, 0x00000001 },
|
||||
{ DVFSRC_BASIC_CONTROL_4, 0x0000020F },
|
||||
{ DVFSRC_INT_EN, 0x00000002 },
|
||||
};
|
||||
|
||||
static const struct reg_config lp5_7500_init_configs[] = {
|
||||
/* SW QOS */
|
||||
{ DVFSRC_DDR_REQUEST5, 0x77654321 },
|
||||
{ DVFSRC_DDR_REQUEST8, 0x00000007 },
|
||||
/* HRT */
|
||||
{ DVFSRC_HRT_REQUEST, 0x77654321 },
|
||||
{ DVFSRC_HRT_REQUEST_1, 0x00000007 },
|
||||
/* MDDDR */
|
||||
{ DVFSRC_95MD_SCEN_BW7, 0x70000000 },
|
||||
{ DVFSRC_95MD_SCEN_BW7_T, 0x70000000 },
|
||||
{ DVFSRC_95MD_SCEN_BWU, 0x00000007 },
|
||||
};
|
||||
|
||||
static const struct reg_config lp5_8533_init_configs[] = {
|
||||
/* SW QOS */
|
||||
{ DVFSRC_DDR_REQUEST5, 0x87654321 },
|
||||
{ DVFSRC_DDR_REQUEST8, 0x00000008 },
|
||||
/* HRT */
|
||||
{ DVFSRC_HRT_REQUEST, 0x87654321 },
|
||||
{ DVFSRC_HRT_REQUEST_1, 0x00000008 },
|
||||
/* MDDDR */
|
||||
{ DVFSRC_95MD_SCEN_BW7, 0x80000000 },
|
||||
{ DVFSRC_95MD_SCEN_BW7_T, 0x80000000 },
|
||||
{ DVFSRC_95MD_SCEN_BWU, 0x00000008 },
|
||||
};
|
||||
|
||||
static const struct reg_config lp5_10677_init_configs[] = {
|
||||
/* SW QOS */
|
||||
{ DVFSRC_DDR_QOS9, 0x000003C0 },
|
||||
{ DVFSRC_DDR_REQUEST5, 0x87654321 },
|
||||
{ DVFSRC_DDR_REQUEST8, 0x000000A9 },
|
||||
/* HRT */
|
||||
{ DVFSRC_HRT_HIGH_9, 0x00005E80 },
|
||||
{ DVFSRC_HRT_LOW_9, 0x00005E7F },
|
||||
{ DVFSRC_HRT_REQUEST, 0x87654321 },
|
||||
{ DVFSRC_HRT_REQUEST_1, 0x000000A9 },
|
||||
};
|
||||
|
||||
static const struct reg_config lp5_8533_init_configs_auto[] = {
|
||||
|
||||
/* LEVEL */
|
||||
{ DVFSRC_LEVEL_LABEL_0_1, 0x80449045 },
|
||||
{ DVFSRC_LEVEL_LABEL_2_3, 0x70448044 },
|
||||
{ DVFSRC_LEVEL_LABEL_4_5, 0x60346044 },
|
||||
{ DVFSRC_LEVEL_LABEL_6_7, 0x50446033 },
|
||||
{ DVFSRC_LEVEL_LABEL_8_9, 0x50335034 },
|
||||
{ DVFSRC_LEVEL_LABEL_10_11, 0x40344044 },
|
||||
{ DVFSRC_LEVEL_LABEL_12_13, 0x40334024 },
|
||||
{ DVFSRC_LEVEL_LABEL_14_15, 0x40224023 },
|
||||
{ DVFSRC_LEVEL_LABEL_16_17, 0x30343044 },
|
||||
{ DVFSRC_LEVEL_LABEL_18_19, 0x30143024 },
|
||||
{ DVFSRC_LEVEL_LABEL_20_21, 0x30233033 },
|
||||
{ DVFSRC_LEVEL_LABEL_22_23, 0x30223013 },
|
||||
{ DVFSRC_LEVEL_LABEL_24_25, 0x30113012 },
|
||||
{ DVFSRC_LEVEL_LABEL_26_27, 0x20342044 },
|
||||
{ DVFSRC_LEVEL_LABEL_28_29, 0x20142024 },
|
||||
{ DVFSRC_LEVEL_LABEL_30_31, 0x20332004 },
|
||||
{ DVFSRC_LEVEL_LABEL_32_33, 0x20132023 },
|
||||
{ DVFSRC_LEVEL_LABEL_34_35, 0x20222003 },
|
||||
{ DVFSRC_LEVEL_LABEL_36_37, 0x20022012 },
|
||||
{ DVFSRC_LEVEL_LABEL_38_39, 0x20012011 },
|
||||
{ DVFSRC_LEVEL_LABEL_40_41, 0x10442000 },
|
||||
{ DVFSRC_LEVEL_LABEL_42_43, 0x10241034 },
|
||||
{ DVFSRC_LEVEL_LABEL_44_45, 0x10041014 },
|
||||
{ DVFSRC_LEVEL_LABEL_46_47, 0x10231033 },
|
||||
{ DVFSRC_LEVEL_LABEL_48_49, 0x10031013 },
|
||||
{ DVFSRC_LEVEL_LABEL_50_51, 0x10121022 },
|
||||
{ DVFSRC_LEVEL_LABEL_52_53, 0x10111002 },
|
||||
{ DVFSRC_LEVEL_LABEL_54_55, 0x10001001 },
|
||||
{ DVFSRC_LEVEL_LABEL_56_57, 0x10341044 },
|
||||
{ DVFSRC_LEVEL_LABEL_58_59, 0x10141024 },
|
||||
{ DVFSRC_LEVEL_LABEL_60_61, 0x10331004 },
|
||||
{ DVFSRC_LEVEL_LABEL_62_63, 0x10131023 },
|
||||
{ DVFSRC_LEVEL_LABEL_64_65, 0x10221003 },
|
||||
{ DVFSRC_LEVEL_LABEL_66_67, 0x10021012 },
|
||||
{ DVFSRC_LEVEL_LABEL_68_69, 0x10011011 },
|
||||
{ DVFSRC_LEVEL_LABEL_70_71, 0x00001000 },
|
||||
{ DVFSRC_LEVEL_LABEL_72_73, 0x00000000 },
|
||||
{ DVFSRC_LEVEL_LABEL_74_75, 0x00000000 },
|
||||
{ DVFSRC_LEVEL_LABEL_76_77, 0x00000000 },
|
||||
{ DVFSRC_LEVEL_LABEL_78_79, 0x00000000 },
|
||||
{ DVFSRC_LEVEL_LABEL_80_81, 0x00000000 },
|
||||
{ DVFSRC_LEVEL_LABEL_82_83, 0x00000000 },
|
||||
{ DVFSRC_LEVEL_LABEL_84_85, 0x00000000 },
|
||||
{ DVFSRC_LEVEL_LABEL_86_87, 0x00000000 },
|
||||
};
|
||||
|
||||
#endif /* MT_VCORE_DVFSRC_PLAT_DEF_H */
|
||||
57
plat/mediatek/drivers/spm/mt_spm_vcorefs_common.h
Normal file
57
plat/mediatek/drivers/spm/mt_spm_vcorefs_common.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (c) 2025, Mediatek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_VCOREFS_COMMON_H
|
||||
#define MT_SPM_VCOREFS_COMMON_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*******************************************************************
|
||||
*
|
||||
* DVFSRC Function Return Value & Other Macro Definition
|
||||
*
|
||||
*******************************************************************/
|
||||
#define VCOREFS_SUCCESS 0
|
||||
#define VCOREFS_E_NOT_SUPPORTED -1
|
||||
#define VCOREFS_E_SPMFW_NOT_READY 0
|
||||
|
||||
#define TAG "vcorefs: "
|
||||
#define v_min(a, b) MAX(a, b)
|
||||
#define v_max(a, b) MIN(a, b)
|
||||
|
||||
/*******************************************************************
|
||||
*
|
||||
* VCOREFS CMD
|
||||
*
|
||||
********************************************************************/
|
||||
enum vcorefs_smc_cmd {
|
||||
VCOREFS_SMC_VCORE_DVFS_INIT = 0,
|
||||
VCOREFS_SMC_VCORE_DVFS_KICK = 1,
|
||||
VCOREFS_SMC_CMD_OPP_TYPE = 2,
|
||||
VCOREFS_SMC_CMD_FW_TYPE = 3,
|
||||
VCOREFS_SMC_CMD_GET_UV = 4,
|
||||
VCOREFS_SMC_CMD_GET_FREQ = 5,
|
||||
VCOREFS_SMC_CMD_GET_NUM_V = 6,
|
||||
VCOREFS_SMC_CMD_GET_NUM_F = 7,
|
||||
|
||||
/*chip specific setting */
|
||||
VCOREFS_SMC_CMD_GET_VCORE_INFO = 18,
|
||||
|
||||
/*qos specific setting */
|
||||
VCOREFS_SMC_CMD_QOS_MODE = 32,
|
||||
VCOREFS_SMC_CMD_PAUSE_ENABLE = 33,
|
||||
|
||||
/*spm resource request */
|
||||
VCOREFS_SMC_RSC_MEM_REQ = 64,
|
||||
VCOREFS_SMC_RSC_MEM_REL = 65,
|
||||
};
|
||||
|
||||
struct reg_config {
|
||||
uint32_t offset;
|
||||
uint32_t val;
|
||||
};
|
||||
|
||||
#endif /* MT_SPM_VCOREFS_COMMON_H */
|
||||
25
plat/mediatek/drivers/spm/mt_spm_vcorefs_exp.h
Normal file
25
plat/mediatek/drivers/spm/mt_spm_vcorefs_exp.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2025, Mediatek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_VCOREFS_EXP_H
|
||||
#define MT_SPM_VCOREFS_EXP_H
|
||||
|
||||
int spm_vcorefs_plat_init(uint32_t dvfsrc_flag,
|
||||
uint32_t dvfsrc_vmode, uint32_t *dram_type);
|
||||
int spm_vcorefs_plat_kick(void);
|
||||
int spm_vcorefs_get_opp_type(uint32_t *val);
|
||||
int spm_vcorefs_get_fw_type(uint32_t *val);
|
||||
int spm_vcorefs_get_dram_freq(uint32_t gear, uint32_t *freq);
|
||||
int spm_vcorefs_get_vcore_opp_num(uint32_t *val);
|
||||
int spm_vcorefs_get_dram_opp_num(uint32_t *val);
|
||||
int spm_vcorefs_get_vcore_info(uint32_t idx, uint32_t *val);
|
||||
int spm_vcorefs_qos_mode(uint32_t mode);
|
||||
int spm_vcorefs_pause_enable(uint32_t enable);
|
||||
void spm_vcorefs_plat_suspend(void);
|
||||
void spm_vcorefs_plat_resume(void);
|
||||
void dvfsrc_md_ddr_turbo(int is_turbo);
|
||||
|
||||
#endif /* MT_SPM_VCOREFS_EXP_H */
|
||||
115
plat/mediatek/drivers/spm/mt_spm_vcorefs_smc.c
Normal file
115
plat/mediatek/drivers/spm/mt_spm_vcorefs_smc.c
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* Copyright (c) 2025, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
|
||||
#include <drivers/spm/mt_spm_vcorefs_api.h>
|
||||
#include <mt_spm_vcorefs_common.h>
|
||||
#include <mt_spm_vcorefs_exp.h>
|
||||
#include <mt_spm_vcorefs_ext.h>
|
||||
#include <mtk_sip_svc.h>
|
||||
|
||||
static u_register_t mtk_vcorefs_handler(u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3,
|
||||
u_register_t x4,
|
||||
void *handle,
|
||||
struct smccc_res *smccc_ret)
|
||||
{
|
||||
uint64_t ret = VCOREFS_E_NOT_SUPPORTED;
|
||||
uint64_t cmd = x1;
|
||||
uint32_t val = 0;
|
||||
|
||||
switch (cmd) {
|
||||
case VCOREFS_SMC_VCORE_DVFS_INIT:
|
||||
ret = spm_vcorefs_plat_init(x2, x3, &val);
|
||||
smccc_ret->a1 = val;
|
||||
break;
|
||||
case VCOREFS_SMC_VCORE_DVFS_KICK:
|
||||
ret = spm_vcorefs_plat_kick();
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_OPP_TYPE:
|
||||
ret = spm_vcorefs_get_opp_type(&val);
|
||||
smccc_ret->a1 = val;
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_FW_TYPE:
|
||||
ret = spm_vcorefs_get_fw_type(&val);
|
||||
smccc_ret->a1 = val;
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_GET_UV:
|
||||
ret = spm_vcorefs_get_vcore_uv(x2, &val);
|
||||
smccc_ret->a1 = val;
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_GET_FREQ:
|
||||
ret = spm_vcorefs_get_dram_freq(x2, &val);
|
||||
smccc_ret->a1 = val;
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_GET_NUM_V:
|
||||
ret = spm_vcorefs_get_vcore_opp_num(&val);
|
||||
smccc_ret->a1 = val;
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_GET_NUM_F:
|
||||
ret = spm_vcorefs_get_dram_opp_num(&val);
|
||||
smccc_ret->a1 = val;
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_GET_VCORE_INFO:
|
||||
ret = spm_vcorefs_get_vcore_info(x2, &val);
|
||||
smccc_ret->a1 = val;
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_QOS_MODE:
|
||||
ret = spm_vcorefs_qos_mode(x2);
|
||||
break;
|
||||
#ifdef MTK_VCORE_DVFS_PAUSE
|
||||
case VCOREFS_SMC_CMD_PAUSE_ENABLE:
|
||||
ret = spm_vcorefs_pause_enable(x2);
|
||||
break;
|
||||
#endif
|
||||
#ifdef MTK_VCORE_DVFS_RES_MEM
|
||||
case VCOREFS_SMC_RSC_MEM_REQ:
|
||||
ret = spm_vcorefs_rsc_mem_req(true);
|
||||
break;
|
||||
case VCOREFS_SMC_RSC_MEM_REL:
|
||||
ret = spm_vcorefs_rsc_mem_req(false);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
DECLARE_SMC_HANDLER(MTK_SIP_VCORE_CONTROL, mtk_vcorefs_handler);
|
||||
|
||||
#ifdef CONFIG_MTK_VCOREDVFS_LK_SUPPORT
|
||||
static u_register_t mtk_vcorefs_bl_handler(u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3,
|
||||
u_register_t x4,
|
||||
void *handle,
|
||||
struct smccc_res *smccc_ret)
|
||||
{
|
||||
uint64_t = VCOREFS_E_NOT_SUPPORTED;
|
||||
uint32_t val = 0;
|
||||
|
||||
switch (x1) {
|
||||
case VCOREFS_SMC_VCORE_DVFS_INIT:
|
||||
ret = spm_vcorefs_plat_init(x2, x3, &val);
|
||||
smccc_ret->a1 = val;
|
||||
break;
|
||||
case VCOREFS_SMC_VCORE_DVFS_KICK:
|
||||
ret = spm_vcorefs_plat_kick();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
DECLARE_SMC_HANDLER(MTK_SIP_BL_SPM_VCOREFS_CONTROL, mtk_vcorefs_bl_handler);
|
||||
#endif
|
||||
|
|
@ -35,6 +35,8 @@ ifneq ($(CONFIG_MTK_SPM_COMMON_SUPPORT), y)
|
|||
LOCAL_SRCS-${CONFIG_MTK_SPM_SUPPORT} += ${LOCAL_DIR}/mt_spm_early_init.c
|
||||
endif
|
||||
|
||||
LOCAL_SRCS-${CONFIG_MTK_VCOREDVFS_SUPPORT} += ${LOCAL_DIR}/mt_spm_vcorefs_smc.c
|
||||
|
||||
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
|
||||
|
||||
SUB_RULES-${MTK_SPM_COMMON_DRV} += ${LOCAL_DIR}/common
|
||||
|
|
|
|||
16
plat/mediatek/include/drivers/dbgtop.h
Normal file
16
plat/mediatek/include/drivers/dbgtop.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright (c) 2025, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef DBGTOP_H
|
||||
#define DBGTOP_H
|
||||
|
||||
int mtk_dbgtop_dram_reserved(int enable);
|
||||
int mtk_dbgtop_cfg_dvfsrc(int enable);
|
||||
int mtk_dbgtop_dfd_count_en(int enable);
|
||||
int mtk_dbgtop_drm_latch_en(int enable);
|
||||
int mtk_dbgtop_dfd_pause_dvfsrc(int enable);
|
||||
|
||||
#endif /* DBGTOP_H */
|
||||
29
plat/mediatek/include/drivers/dramc.h
Normal file
29
plat/mediatek/include/drivers/dramc.h
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright (c) 2025, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef DRAMC_H
|
||||
#define DRAMC_H
|
||||
|
||||
#define DRAM_MAX_FREQ 16
|
||||
#define DRAM_MAX_MR_CNT 10
|
||||
#define DRAM_MAX_RK 2
|
||||
|
||||
int init_dramc_info(void *tag_entry);
|
||||
int get_dram_step_freq(unsigned int step);
|
||||
unsigned int get_dram_type(void);
|
||||
|
||||
enum dram_type {
|
||||
TYPE_DDR1 = 1,
|
||||
TYPE_LPDDR2,
|
||||
TYPE_LPDDR3,
|
||||
TYPE_PCDDR3,
|
||||
TYPE_LPDDR4,
|
||||
TYPE_LPDDR4X,
|
||||
TYPE_LPDDR4P,
|
||||
TYPE_LPDDR5,
|
||||
TYPE_LPDDR5X,
|
||||
};
|
||||
#endif /* DRAMC_H */
|
||||
18
plat/mediatek/include/drivers/spm/mt_spm_vcorefs_api.h
Normal file
18
plat/mediatek/include/drivers/spm/mt_spm_vcorefs_api.h
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* Copyright (c) 2025, Mediatek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_VCOREFS_API_H
|
||||
#define MT_SPM_VCOREFS_API_H
|
||||
|
||||
/*******************************************************************
|
||||
*
|
||||
* DVFSRC API
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
int spm_vcorefs_get_vcore_uv(uint32_t gear, uint32_t *val);
|
||||
|
||||
#endif /* MT_SPM_VCOREFS_API_H */
|
||||
12
plat/mediatek/include/drivers/sramrc.h
Normal file
12
plat/mediatek/include/drivers/sramrc.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2025, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SRAMRC_H
|
||||
#define SRAMRC_H
|
||||
|
||||
int sramrc_update_dvfsrc_setting(int enable);
|
||||
|
||||
#endif /* SRAMRC_H */
|
||||
Loading…
Add table
Reference in a new issue