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https://github.com/ARM-software/arm-trusted-firmware.git
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fix(versal2): modify function to have single return
This corrects the MISRA violation C2012-15.5: A function should have a single point of exit at the end. Introduced a temporary variable to store the return value to ensure single return for the function. Change-Id: Ib152831e84f5ead5b57fd713ebfedb1f3340a727 Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This commit is contained in:
parent
5003a332b8
commit
fb2fdcd953
5 changed files with 53 additions and 29 deletions
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@ -170,16 +170,19 @@ int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
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{
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static uint32_t index;
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uint32_t i;
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int32_t ret = 0;
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/* Validate 'handler' and 'id' parameters */
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if ((handler == NULL) || (index >= MAX_INTR_EL3)) {
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return -EINVAL;
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ret = -EINVAL;
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goto exit_label;
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}
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/* Check if a handler has already been registered */
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for (i = 0; i < index; i++) {
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if (id == type_el3_interrupt_table[i].id) {
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return -EALREADY;
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ret = -EALREADY;
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goto exit_label;
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}
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}
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@ -188,7 +191,8 @@ int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
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index++;
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return 0;
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exit_label:
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return ret;
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}
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static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
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@ -24,6 +24,9 @@
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER)
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#define E_INVALID_CORE_COUNT -1
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#define E_INVALID_CLUSTER_COUNT -3
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#define PLAT_MAX_PWR_LVL U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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@ -40,12 +40,14 @@ static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr)
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int32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER;
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uintptr_t apu_cluster_base = 0, apu_pcli_base, apu_pcli_cluster = 0;
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uintptr_t rst_apu_cluster = PSX_CRF + RST_APU0_OFFSET + ((uint64_t)cluster * 0x4U);
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int32_t ret = PSCI_E_SUCCESS;
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VERBOSE("%s: mpidr: 0x%lx, cpuid: %x, cpu: %x, cluster: %x\n",
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__func__, mpidr, cpu_id, cpu, cluster);
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if (cpu_id == -1) {
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return PSCI_E_INTERN_FAIL;
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ret = PSCI_E_INTERN_FAIL;
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goto exit_label;
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}
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if (cluster > 3U) {
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@ -84,7 +86,8 @@ static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr)
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mmio_write_32(apu_pcli_base + PCLI_PSTATE_OFFSET, PCLI_PSTATE_VAL_CLEAR);
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mmio_write_32(apu_pcli_base + PCLI_PREQ_OFFSET, PREQ_CHANGE_REQUEST);
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return PSCI_E_SUCCESS;
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exit_label:
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return ret;
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}
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static void zynqmp_nopmu_pwr_domain_off(const psci_power_state_t *target_state)
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@ -101,13 +104,15 @@ static void __dead2 zynqmp_nopmu_system_reset(void)
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static int32_t zynqmp_validate_ns_entrypoint(uint64_t ns_entrypoint)
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{
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int32_t ret = PSCI_E_INVALID_ADDRESS;
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VERBOSE("Validate ns_entry point %lx\n", ns_entrypoint);
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if ((ns_entrypoint) != 0U) {
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return PSCI_E_SUCCESS;
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} else {
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return PSCI_E_INVALID_ADDRESS;
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ret = PSCI_E_SUCCESS;
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}
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return ret;
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}
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static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state)
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@ -41,6 +41,7 @@ const uint8_t *plat_get_power_domain_tree_desc(void)
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int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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uint32_t cluster_id, cpu_id;
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int32_t ret = 0;
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mpidr &= MPIDR_AFFINITY_MASK;
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@ -48,7 +49,8 @@ int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
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cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
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if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
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return -3;
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ret = E_INVALID_CLUSTER_COUNT;
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goto exit_label;
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}
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/*
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@ -56,8 +58,11 @@ int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
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* one of the two clusters present on the platform.
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*/
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if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) {
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return -1;
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ret = E_INVALID_CORE_COUNT;
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} else {
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ret = (cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER));
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}
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return (cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER));
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exit_label:
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return ret;
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}
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@ -288,13 +288,16 @@ int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id,
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uint32_t start_idx)
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{
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const struct scmi_clk *clock = clk_find(agent_id, scmi_id);
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int32_t ret = SCMI_SUCCESS;
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if (clock == NULL) {
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return SCMI_NOT_FOUND;
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ret = SCMI_NOT_FOUND;
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goto exit_label;
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}
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if (start_idx > 0U) {
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return SCMI_OUT_OF_RANGE;
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ret = SCMI_OUT_OF_RANGE;
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goto exit_label;
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}
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if (array == NULL) {
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@ -304,10 +307,11 @@ int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id,
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VERBOSE("SCMI: CLK: id: %d, clk_name: %s, get_rate %lu\n",
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scmi_id, clock->name, *array);
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} else {
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return SCMI_GENERIC_ERROR;
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ret = SCMI_GENERIC_ERROR;
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}
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return SCMI_SUCCESS;
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exit_label:
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return ret;
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}
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unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, unsigned int scmi_id)
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@ -529,12 +533,13 @@ size_t plat_scmi_pd_count(unsigned int agent_id)
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const char *plat_scmi_pd_get_name(unsigned int agent_id, unsigned int pd_id)
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{
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const struct scmi_pd *pd = find_pd(agent_id, pd_id);
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const char *ret = NULL;
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if (pd == NULL) {
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return NULL;
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if (pd != NULL) {
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ret = pd->name;
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}
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return pd->name;
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return ret;
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}
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unsigned int plat_scmi_pd_statistics(unsigned int agent_id, unsigned long *pd_id)
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@ -550,14 +555,15 @@ unsigned int plat_scmi_pd_get_attributes(unsigned int agent_id, unsigned int pd_
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unsigned int plat_scmi_pd_get_state(unsigned int agent_id, unsigned int pd_id)
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{
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const struct scmi_pd *pd = find_pd(agent_id, pd_id);
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uint32_t ret = SCMI_NOT_SUPPORTED;
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if (pd == NULL) {
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return SCMI_NOT_SUPPORTED;
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if (pd != NULL) {
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NOTICE("SCMI: PD: get id: %d, state: %x\n", pd_id, pd->state);
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ret = pd->state;
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}
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NOTICE("SCMI: PD: get id: %d, state: %x\n", pd_id, pd->state);
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return pd->state;
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return ret;
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}
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int32_t plat_scmi_pd_set_state(unsigned int agent_id, unsigned int flags, unsigned int pd_id,
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if (pd == NULL) {
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ret = SCMI_NOT_SUPPORTED;
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} else {
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NOTICE("SCMI: PD: set id: %d, orig state: %x, new state: %x, flags: %x\n",
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pd_id, pd->state, state, flags);
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pd->state = state;
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goto exit_label;
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}
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NOTICE("SCMI: PD: set id: %d, orig state: %x, new state: %x, flags: %x\n",
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pd_id, pd->state, state, flags);
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pd->state = state;
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exit_label:
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return ret;
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}
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