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Merge changes I70b68b06,I7b180c3e,Id4ad925d,Ie31933e0,Ie8fe1f1d, ... into integration

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* changes:
  refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM
  fix(tc): modify ethernet configuration for TC4 FPGA
  fix(tc): modify gpio controller base addr for TC4 FPGA
  fix(tc): modify DPU configuration in dts for TC4 FPGA
  fix(tc): modify mmc configuration for TC4 FPGA
  feat(tc): configure UART for TC4 FPGA
This commit is contained in:
Manish V Badarkhe 2025-01-23 10:41:35 +01:00 • committed by TrustedFirmware Code Review
commit bf6b151390
6 changed files with 33 additions and 15 deletions

4
fdts/tc-fpga.dtsi
View file

@ -25,7 +25,7 @@
stdout-path = "serial0:38400n8";
};
#if TC_FPGA_ANDROID_IMG_IN_RAM
#if TC_FPGA_FS_IMG_IN_RAM
reserved-memory {
phram@0x880000000 {
/*
@ -36,7 +36,7 @@
no-map;
};
};
#endif /* TC_FPGA_ANDROID_IMG_IN_RAM */
#endif /* TC_FPGA_FS_IMG_IN_RAM */
ethernet: ethernet@ETHERNET_ADDR {
compatible = "smsc,lan9115";

4
fdts/tc3-4-base.dtsi
View file

@ -22,10 +22,8 @@
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#elif TARGET_FLAVOUR_FPGA
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif
#include "tc-base.dtsi"
/ {

5
fdts/tc3.dts
View file

@ -40,6 +40,11 @@
#define VIRTIO_BLOCK_ADDR 1c130000
#define VIRTIO_BLOCK_INT 204
#if TARGET_FLAVOUR_FPGA
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"

16
fdts/tc4.dts
View file

@ -20,14 +20,21 @@
#define RSE_MHU_TX_ADDR 49020000 /* hex */
#define RSE_MHU_RX_ADDR 49030000 /* hex */
#if TARGET_FLAVOUR_FVP
#define ETHERNET_ADDR 64000000
#define ETHERNET_INT 799
#define SYS_REGS_ADDR 60080000
#define MMC_ADDR 600b0000
#define MMC_INT_0 778
#define MMC_INT_1 779
#else /* TARGET_FLAVOUR_FPGA */
#define ETHERNET_ADDR 18000000
#define ETHERNET_INT 109
#define SYS_REGS_ADDR 1c010000
#define MMC_ADDR 1c050000
#define MMC_INT_0 107
#define MMC_INT_1 108
#endif /* TARGET_FLAVOUR_FVP */
#define RTC_ADDR 600a0000
#define RTC_INT 777
@ -40,6 +47,11 @@
#define VIRTIO_BLOCK_ADDR 60020000
#define VIRTIO_BLOCK_INT 769
#if TARGET_FLAVOUR_FPGA
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#endif
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"

13
plat/arm/board/tc/include/platform_def.h
View file

@ -259,7 +259,7 @@
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
#elif TARGET_PLATFORM >= 3
#if TC_FPGA_ANDROID_IMG_IN_RAM
#if TC_FPGA_FS_IMG_IN_RAM
/* 10GB reserved for system+userdata+vendor images */
#define SYSTEM_IMAGE_SIZE 0xC0000000 /* 3GB */
#define USERDATA_IMAGE_SIZE 0x140000000 /* 5GB */
@ -273,8 +273,8 @@
#define PLAT_ARM_DRAM2_SIZE ULL(0x380000000) - ANDROID_FS_SIZE
#else
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#define PLAT_ARM_DRAM2_SIZE ULL(0x380000000)
#endif /* TC_FPGA_ANDROID_IMG_IN_RAM */
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
#endif /* TC_FPGA_FS_IMG_IN_RAM */
#endif /* TARGET_VERSION >= 3 */
@ -448,9 +448,12 @@
#if TARGET_PLATFORM <= 2
#define TC_UARTCLK 5000000
#elif TARGET_PLATFORM >= 3
#elif TARGET_PLATFORM == 3
#define TC_UARTCLK 3750000
#endif /* TARGET_PLATFORM >= 3 */
#elif TARGET_PLATFORM == 4
#define TC_UARTCLK 4000000
#endif /* TARGET_PLATFORM <=2 */
#if TARGET_FLAVOUR_FVP
#define PLAT_ARM_BOOT_UART_BASE TC_UART1

6
plat/arm/board/tc/platform.mk
View file

@ -77,8 +77,8 @@ ifeq ($(filter ${TARGET_FLAVOUR}, fvp fpga),)
$(error TARGET_FLAVOUR must be fvp or fpga)
endif
# Support for loading Android Image to DRAM
TC_FPGA_ANDROID_IMG_IN_RAM := 0
# Support for loading FS Image to DRAM
TC_FPGA_FS_IMG_IN_RAM := 0
# Support Loading of FIP image to DRAM
TC_FPGA_FIP_IMG_IN_RAM := 0
@ -92,7 +92,7 @@ $(eval $(call add_defines, \
TC_RESOLUTION_$(call uppercase,${TC_RESOLUTION}) \
TC_DPU_USE_SCMI_CLK \
TC_SCMI_PD_CTRL_EN \
TC_FPGA_ANDROID_IMG_IN_RAM \
TC_FPGA_FS_IMG_IN_RAM \
TC_FPGA_FIP_IMG_IN_RAM \
TC_DPU_USE_SIMPLE_PANEL \
))