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https://github.com/ARM-software/arm-trusted-firmware.git
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feat(mt8196): add mcusys moudles for power management
And mcusys drivers to enhance CPU power state control. Signed-off-by: Kai Liang <kai.liang@mediatek.com> Change-Id: I7d84407cebc16a5ab23359781574e9d02e90c58b
This commit is contained in:
Kai Liang
Wenzhen Yu
parent
75530ee280
commit
95e974fa15
6 changed files with 555 additions and 1 deletions
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2022, MediaTek Inc. All rights reserved.
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# Copyright (c) 2025, MediaTek Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -8,7 +8,15 @@ LOCAL_DIR := $(call GET_LOCAL_DIR)
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MODULE := mcusys
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ifeq ($(MTK_SOC), mt8196)
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PLAT_INCLUDES += -I${MTK_PLAT}/include/drivers/mcusys/$(MCUSYS_VERSION)
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ifneq ($(MCUPM_VERSION),)
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PLAT_INCLUDES += -I${MTK_PLAT}/include/drivers/mcusys/mcupm
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CFLAGS += -DMCUPM_VERSION_${MCUPM_VERSION}
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endif
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else
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PLAT_INCLUDES += -I$(LOCAL_DIR)/$(MCUSYS_VERSION)
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endif
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LOCAL_SRCS-y := $(LOCAL_DIR)/mcusys.c
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21
plat/mediatek/include/drivers/mcusys/mcupm/mcupm_cfg.h
Normal file
21
plat/mediatek/include/drivers/mcusys/mcupm/mcupm_cfg.h
Normal file
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MCUPM_CFG_H
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#define MCUPM_CFG_H
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#if defined(MCUPM_VERSION_v1)
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#define CPU_EB_MBOX3_OFFSET 0xCE0
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#elif defined(MCUPM_VERSION_v2) /* MCUPM_VERSION_v1 */
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#define CPU_EB_MBOX3_OFFSET 0x7E0
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#define CPU_EB_MCUSYS_CNT_OFST 0x944
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#elif defined(MCUPM_VERSION_v3) /* MCUPM_VERSION_v2 */
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#define CPU_EB_MBOX3_OFFSET 0x7E0
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#define CPU_EB_MCUSYS_CNT_OFST 0xE44
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#define CPU_EB_RET_STA_OFFSET 0x350
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#endif /* MCUPM_VERSION_v3 */
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#endif /* MCUPM_CFG_H */
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290
plat/mediatek/include/drivers/mcusys/v1/mcucfg.h
Normal file
290
plat/mediatek/include/drivers/mcusys/v1/mcucfg.h
Normal file
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@ -0,0 +1,290 @@
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/*
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* Copyright (c) 2025, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MCUCFG_V1_H
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#define MCUCFG_V1_H
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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#endif /*__ASSEMBLER__*/
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#include <platform_def.h>
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#define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) \
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(MCUCFG_BASE + 0x2290 + ((cpu) * 8))
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#define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) \
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(MCUCFG_BASE + 0x2294 + ((cpu) * 8))
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#define MP2_CPUCFG (MCUCFG_BASE + 0x2208)
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#define MP2_CPU0_STANDBYWFE BIT(4)
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#define MP2_CPU1_STANDBYWFE BIT(5)
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#define MP0_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x788)
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#define MP1_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x78C)
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#define MP1_CPUTOP_SPMC_SRAM_CTL (MCUCFG_BASE + 0x790)
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#define sw_spark_en BIT(0)
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#define sw_no_wait_for_q_channel BIT(1)
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#define sw_fsm_override BIT(2)
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#define sw_logic_pre1_pdb BIT(3)
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#define sw_logic_pre2_pdb BIT(4)
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#define sw_logic_pdb BIT(5)
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#define sw_iso BIT(6)
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#define sw_sram_sleepb (0x3FU << 7)
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#define sw_sram_isointb BIT(13)
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#define sw_clk_dis BIT(14)
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#define sw_ckiso BIT(15)
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#define sw_pd (0x3FU << 16)
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#define sw_hot_plug_reset BIT(22)
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#define sw_pwr_on_override_en BIT(23)
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#define sw_pwr_on BIT(24)
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#define sw_coq_dis BIT(25)
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#define logic_pdbo_all_off_ack BIT(26)
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#define logic_pdbo_all_on_ack BIT(27)
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#define logic_pre2_pdbo_all_on_ack BIT(28)
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#define logic_pre1_pdbo_all_on_ack BIT(29)
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#define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \
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(MCUCFG_BASE + 0x1C30 + (cluster) * 0x2000 + (cpu) * 4)
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#define CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1C30)
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#define CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1C34)
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#define CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1C38)
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#define CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1C3C)
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#define CPUSYS1_CPU0_SPMC_CTL (MCUCFG_BASE + 0x3C30)
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#define CPUSYS1_CPU1_SPMC_CTL (MCUCFG_BASE + 0x3C34)
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#define CPUSYS1_CPU2_SPMC_CTL (MCUCFG_BASE + 0x3C38)
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#define CPUSYS1_CPU3_SPMC_CTL (MCUCFG_BASE + 0x3C3C)
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#define cpu_sw_spark_en BIT(0)
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#define cpu_sw_no_wait_for_q_channel BIT(1)
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#define cpu_sw_fsm_override BIT(2)
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#define cpu_sw_logic_pre1_pdb BIT(3)
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#define cpu_sw_logic_pre2_pdb BIT(4)
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#define cpu_sw_logic_pdb BIT(5)
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#define cpu_sw_iso BIT(6)
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#define cpu_sw_sram_sleepb BIT(7)
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#define cpu_sw_sram_isointb BIT(8)
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#define cpu_sw_clk_dis BIT(9)
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#define cpu_sw_ckiso BIT(10)
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#define cpu_sw_pd (0x1FU<<11)
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#define cpu_sw_hot_plug_reset BIT(16)
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#define cpu_sw_powr_on_override_en BIT(17)
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#define cpu_sw_pwr_on BIT(18)
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#define cpu_spark2ldo_allswoff BIT(19)
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#define cpu_pdbo_all_on_ack BIT(20)
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#define cpu_pre2_pdbo_allon_ack BIT(21)
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#define cpu_pre1_pdbo_allon_ack BIT(22)
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/* CPC related registers */
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#define CPC_MCUSYS_CPC_OFF_THRES (MCUCFG_BASE + 0xa714)
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#define CPC_MCUSYS_PWR_CTRL (MCUCFG_BASE + 0xa804)
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#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUCFG_BASE + 0xa814)
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#define CPC_MCUSYS_LAST_CORE_REQ (MCUCFG_BASE + 0xa818)
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#define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUCFG_BASE + 0xa81c)
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#define CPC_MCUSYS_LAST_CORE_RESP (MCUCFG_BASE + 0xa824)
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#define CPC_MCUSYS_PWR_ON_MASK (MCUCFG_BASE + 0xa828)
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#define CPC_SPMC_PWR_STATUS (MCUCFG_BASE + 0xa840)
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#define CPC_WAKEUP_REQ (MCUCFG_BASE + 0xa84c)
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#define CPC_MCUSYS_CPU_ON_SW_HINT_SET (MCUCFG_BASE + 0xa8a8)
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#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR (MCUCFG_BASE + 0xa8ac)
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#define CPC_MCUSYS_CPC_DBG_SETTING (MCUCFG_BASE + 0xab00)
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#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE (MCUCFG_BASE + 0xab04)
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#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE (MCUCFG_BASE + 0xab08)
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#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE (MCUCFG_BASE + 0xab0c)
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#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE (MCUCFG_BASE + 0xab10)
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#define CPC_MCUSYS_TRACE_SEL (MCUCFG_BASE + 0xab14)
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#define CPC_MCUSYS_TRACE_DATA (MCUCFG_BASE + 0xab20)
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#define CPC_CPU0_LATENCY (MCUCFG_BASE + 0xab40)
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#define CPC_CLUSTER_OFF_LATENCY (MCUCFG_BASE + 0xab60)
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#define CPC_CLUSTER_ON_LATENCY (MCUCFG_BASE + 0xab64)
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#define CPC_MCUSYS_LATENCY (MCUCFG_BASE + 0xab68)
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#define CPC_MCUSYS_CLUSTER_COUNTER (MCUCFG_BASE + 0xab70)
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#define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUCFG_BASE + 0xab74)
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#define CPC_CPU_LATENCY(cpu) (CPC_CPU0_LATENCY + 4 * (cpu))
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/* CPC_MCUSYS_CPC_FLOW_CTRL_CFG bit control */
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#define CPC_CTRL_ENABLE BIT(16)
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#define SSPM_ALL_PWR_CTRL_EN BIT(17)
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#define GIC_WAKEUP_IGNORE(cpu) BIT(21 + (cpu))
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#define CPC_MCUSYS_CPC_RESET_ON_KEEP_ON BIT(17)
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#define CPC_MCUSYS_CPC_RESET_PWR_ON_EN BIT(20)
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/* SPMC related registers */
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#define SPM_MCUSYS_PWR_CON (MCUCFG_BASE + 0xd200)
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#define SPM_MP0_CPUTOP_PWR_CON (MCUCFG_BASE + 0xd204)
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#define SPM_MP0_CPU0_PWR_CON (MCUCFG_BASE + 0xd208)
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#define SPM_MP0_CPU1_PWR_CON (MCUCFG_BASE + 0xd20c)
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#define SPM_MP0_CPU2_PWR_CON (MCUCFG_BASE + 0xd210)
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#define SPM_MP0_CPU3_PWR_CON (MCUCFG_BASE + 0xd214)
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#define SPM_MP0_CPU4_PWR_CON (MCUCFG_BASE + 0xd218)
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#define SPM_MP0_CPU5_PWR_CON (MCUCFG_BASE + 0xd21c)
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#define SPM_MP0_CPU6_PWR_CON (MCUCFG_BASE + 0xd220)
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#define SPM_MP0_CPU7_PWR_CON (MCUCFG_BASE + 0xd224)
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/* bit fields of SPM_*_PWR_CON */
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#define PWR_ON_ACK BIT(31)
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#define VPROC_EXT_OFF BIT(7)
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#define DORMANT_EN BIT(6)
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#define RESETPWRON_CONFIG BIT(5)
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#define PWR_CLK_DIS BIT(4)
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#define PWR_ON BIT(2)
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#define PWR_RST_B BIT(0)
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#define SPARK2LDO (MCUCFG_BASE + 0x2700)
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/* APB Module mcucfg */
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#define MP0_CA7_CACHE_CONFIG (MCUCFG_BASE + 0x000)
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#define MP0_AXI_CONFIG (MCUCFG_BASE + 0x02C)
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#define MP0_MISC_CONFIG0 (MCUCFG_BASE + 0x030)
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#define MP0_MISC_CONFIG1 (MCUCFG_BASE + 0x034)
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#define MP0_MISC_CONFIG2 (MCUCFG_BASE + 0x038)
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#define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x038 + (cpu) * 8)
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#define MP0_MISC_CONFIG3 (MCUCFG_BASE + 0x03C)
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#define MP0_MISC_CONFIG9 (MCUCFG_BASE + 0x054)
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#define MP0_CA7_MISC_CONFIG (MCUCFG_BASE + 0x064)
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#define MP0_RW_RSVD0 (MCUCFG_BASE + 0x06C)
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#define MP1_CA7_CACHE_CONFIG (MCUCFG_BASE + 0x200)
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#define MP1_AXI_CONFIG (MCUCFG_BASE + 0x22C)
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#define MP1_MISC_CONFIG0 (MCUCFG_BASE + 0x230)
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#define MP1_MISC_CONFIG1 (MCUCFG_BASE + 0x234)
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#define MP1_MISC_CONFIG2 (MCUCFG_BASE + 0x238)
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#define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x238 + ((cpu) * 8))
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#define MP1_MISC_CONFIG3 (MCUCFG_BASE + 0x23C)
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#define MP1_MISC_CONFIG9 (MCUCFG_BASE + 0x254)
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#define MP1_CA7_MISC_CONFIG (MCUCFG_BASE + 0x264)
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#define CCI_ADB400_DCM_CONFIG (MCUCFG_BASE + 0x740)
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#define SYNC_DCM_CONFIG (MCUCFG_BASE + 0x744)
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#define MP0_CLUSTER_CFG0 (MCUCFG_BASE + 0xC8D0)
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#define MP0_SPMC (MCUCFG_BASE + 0x788)
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#define MP1_SPMC (MCUCFG_BASE + 0x78C)
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#define MP2_AXI_CONFIG (MCUCFG_BASE + 0x220C)
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#define MP2_AXI_CONFIG_ACINACTM BIT(0)
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#define MP2_AXI_CONFIG_AINACTS BIT(4)
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#define MPx_AXI_CONFIG_ACINACTM BIT(4)
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#define MPx_AXI_CONFIG_AINACTS BIT(5)
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#define MPx_CA7_MISC_CONFIG_standbywfil2 BIT(28)
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#define MP0_CPU0_STANDBYWFE BIT(20)
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#define MP0_CPU1_STANDBYWFE BIT(21)
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#define MP0_CPU2_STANDBYWFE BIT(22)
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#define MP0_CPU3_STANDBYWFE BIT(23)
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#define MP1_CPU0_STANDBYWFE BIT(20)
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#define MP1_CPU1_STANDBYWFE BIT(21)
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#define MP1_CPU2_STANDBYWFE BIT(22)
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#define MP1_CPU3_STANDBYWFE BIT(23)
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#define CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE + 0x1c00)
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#define CPUSYS0_SPARKEN (MCUCFG_BASE + 0x1c04)
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#define CPUSYS0_AMUXSEL (MCUCFG_BASE + 0x1c08)
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#define CPUSYS1_SPARKVRETCNTRL (MCUCFG_BASE + 0x3c00)
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#define CPUSYS1_SPARKEN (MCUCFG_BASE + 0x3c04)
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#define CPUSYS1_AMUXSEL (MCUCFG_BASE + 0x3c08)
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#define MP2_PWR_RST_CTL (MCUCFG_BASE + 0x2008)
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#define MP2_PTP3_CPUTOP_SPMC0 (MCUCFG_BASE + 0x22A0)
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#define MP2_PTP3_CPUTOP_SPMC1 (MCUCFG_BASE + 0x22A4)
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#define MP2_COQ (MCUCFG_BASE + 0x22BC)
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#define MP2_COQ_SW_DIS BIT(0)
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#define MP2_CA15M_MON_SEL (MCUCFG_BASE + 0x2400)
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#define MP2_CA15M_MON_L (MCUCFG_BASE + 0x2404)
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#define CPUSYS2_CPU0_SPMC_CTL (MCUCFG_BASE + 0x2430)
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#define CPUSYS2_CPU1_SPMC_CTL (MCUCFG_BASE + 0x2438)
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#define CPUSYS2_CPU0_SPMC_STA (MCUCFG_BASE + 0x2434)
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#define CPUSYS2_CPU1_SPMC_STA (MCUCFG_BASE + 0x243C)
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#define MP0_CA7L_DBG_PWR_CTRL (MCUCFG_BASE + 0x068)
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#define MP1_CA7L_DBG_PWR_CTRL (MCUCFG_BASE + 0x268)
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#define BIG_DBG_PWR_CTRL (MCUCFG_BASE + 0x75C)
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#define MP2_SW_RST_B BIT(0)
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#define MP2_TOPAON_APB_MASK BIT(1)
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#define B_SW_HOT_PLUG_RESET BIT(30)
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#define B_SW_PD_OFFSET (18)
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#define B_SW_PD (0x3F << B_SW_PD_OFFSET)
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#define B_SW_SRAM_SLEEPB_OFFSET (12)
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#define B_SW_SRAM_SLEEPB (0x3f << B_SW_SRAM_SLEEPB_OFFSET)
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#define B_SW_SRAM_ISOINTB BIT(9)
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#define B_SW_ISO BIT(8)
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#define B_SW_LOGIC_PDB BIT(7)
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#define B_SW_LOGIC_PRE2_PDB BIT(6)
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#define B_SW_LOGIC_PRE1_PDB BIT(5)
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#define B_SW_FSM_OVERRIDE BIT(4)
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#define B_SW_PWR_ON BIT(3)
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#define B_SW_PWR_ON_OVERRIDE_EN BIT(2)
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#define B_FSM_STATE_OUT_OFFSET (6)
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#define B_FSM_STATE_OUT_MASK (0x1f << B_FSM_STATE_OUT_OFFSET)
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#define B_SW_LOGIC_PDBO_ALL_OFF_ACK BIT(5)
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#define B_SW_LOGIC_PDBO_ALL_ON_ACK BIT(4)
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#define B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK BIT(3)
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#define B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK BIT(2)
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#define B_FSM_OFF (0u << B_FSM_STATE_OUT_OFFSET)
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#define B_FSM_ON (1u << B_FSM_STATE_OUT_OFFSET)
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#define B_FSM_RET (2u << B_FSM_STATE_OUT_OFFSET)
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#ifndef __ASSEMBLER__
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/* cpu boot mode */
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enum mp0_coucfg_64bit_ctrl {
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MP0_CPUCFG_64BIT_SHIFT = 12,
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MP1_CPUCFG_64BIT_SHIFT = 28,
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MP0_CPUCFG_64BIT = 0xFU << MP0_CPUCFG_64BIT_SHIFT,
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MP1_CPUCFG_64BIT = 0xFU << MP1_CPUCFG_64BIT_SHIFT
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};
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enum mp1_dis_rgu0_ctrl {
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16,
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
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};
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enum mp1_ainacts_ctrl {
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MP1_AINACTS_SHIFT = 4,
|
||||
MP1_AINACTS = BIT(MP1_AINACTS_SHIFT)
|
||||
};
|
||||
|
||||
enum mp1_sw_cg_gen {
|
||||
MP1_SW_CG_GEN_SHIFT = 12,
|
||||
MP1_SW_CG_GEN = BIT(MP1_SW_CG_GEN_SHIFT)
|
||||
};
|
||||
|
||||
enum mp1_l2rstdisable {
|
||||
MP1_L2RSTDISABLE_SHIFT = 14,
|
||||
MP1_L2RSTDISABLE = BIT(MP1_L2RSTDISABLE_SHIFT)
|
||||
};
|
||||
#endif /*__ASSEMBLER__*/
|
||||
|
||||
#endif /* __MCUCFG_V1_H__ */
|
||||
65
plat/mediatek/include/drivers/mcusys/v2/mcucfg.h
Normal file
65
plat/mediatek/include/drivers/mcusys/v2/mcucfg.h
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright (c) 2025, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MCUCFG_H
|
||||
#define MCUCFG_H
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
#endif /*__ASSEMBLER__*/
|
||||
#include <platform_def.h>
|
||||
|
||||
#define MCUSYS_CPC_BASE (MCUCFG_BASE + 0x40000)
|
||||
|
||||
/* CPC related registers */
|
||||
#define CPC_FCM_SPMC_SW_CFG2 (MCUSYS_CPC_BASE + 0x004)
|
||||
#define CPC_FCM_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x010)
|
||||
#define CPC_MCUSYS_CPC_OFF_THRES (MCUSYS_CPC_BASE + 0x014)
|
||||
#define CPC_MCUSYS_PWR_CTRL (MCUSYS_CPC_BASE + 0x104)
|
||||
#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUSYS_CPC_BASE + 0x114)
|
||||
#define CPC_MCUSYS_LAST_CORE_REQ (MCUSYS_CPC_BASE + 0x118)
|
||||
#define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x11c)
|
||||
#define CPC_MCUSYS_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x124)
|
||||
#define CPC_MCUSYS_PWR_ON_MASK (MCUSYS_CPC_BASE + 0x128)
|
||||
#define CPC_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x140)
|
||||
#define CPC_CORE_CUR_FSM (MCUSYS_CPC_BASE + 0x144)
|
||||
#define CPC_WAKEUP_REQ (MCUSYS_CPC_BASE + 0x14c)
|
||||
#define CPC_MCUSYS_CPU_ON_SW_HINT_SET (MCUSYS_CPC_BASE + 0x1a8)
|
||||
#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR (MCUSYS_CPC_BASE + 0x1ac)
|
||||
#define CPC_MCUSYS_CPC_DBG_SETTING (MCUSYS_CPC_BASE + 0x200)
|
||||
#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE (MCUSYS_CPC_BASE + 0x204)
|
||||
#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE (MCUSYS_CPC_BASE + 0x208)
|
||||
#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE (MCUSYS_CPC_BASE + 0x20c)
|
||||
#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE (MCUSYS_CPC_BASE + 0x210)
|
||||
#define CPC_MCUSYS_TRACE_SEL (MCUSYS_CPC_BASE + 0x214)
|
||||
#define CPC_MCUSYS_TRACE_DATA (MCUSYS_CPC_BASE + 0x220)
|
||||
#define CPC_CPU0_LATENCY (MCUSYS_CPC_BASE + 0x240)
|
||||
#define CPC_CLUSTER_OFF_LATENCY (MCUSYS_CPC_BASE + 0x260)
|
||||
#define CPC_CLUSTER_ON_LATENCY (MCUSYS_CPC_BASE + 0x264)
|
||||
#define CPC_MCUSYS_LATENCY (MCUSYS_CPC_BASE + 0x268)
|
||||
#define CPC_MCUSYS_CLUSTER_COUNTER (MCUSYS_CPC_BASE + 0x270)
|
||||
#define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUSYS_CPC_BASE + 0x274)
|
||||
#define CPC_CPU_LATENCY(cpu) (CPC_CPU0_LATENCY + 4 * (cpu))
|
||||
|
||||
#define CPC_WDT_LATCH_INFO1 (MCUSYS_CPC_BASE + 0x280)
|
||||
#define CPC_WDT_LATCH_INFO2 (MCUSYS_CPC_BASE + 0x284)
|
||||
#define CPC_WDT_LATCH_INFO3 (MCUSYS_CPC_BASE + 0x288)
|
||||
#define CPC_WDT_LATCH_INFO4 (MCUSYS_CPC_BASE + 0x28c)
|
||||
#define CPC_WDT_LATCH_INFO5 (MCUSYS_CPC_BASE + 0x290)
|
||||
|
||||
/* CPC_MCUSYS_CPC_FLOW_CTRL_CFG bit control */
|
||||
#define CPC_CTRL_ENABLE BIT(16)
|
||||
#define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */
|
||||
#define GIC_WAKEUP_IGNORE(cpu) BIT(21 + (cpu))
|
||||
|
||||
#define CPC_MCUSYS_CPC_RESET_ON_KEEP_ON BIT(17)
|
||||
#define CPC_MCUSYS_CPC_RESET_PWR_ON_EN BIT(20)
|
||||
|
||||
#define CPC_CORE_FSM_ON BIT(3)
|
||||
|
||||
#define CPC_WAKEUP_STAT_NONE 0x0
|
||||
|
||||
#endif /* __MCUCFG_H__ */
|
||||
76
plat/mediatek/include/drivers/mcusys/v3/mcucfg.h
Normal file
76
plat/mediatek/include/drivers/mcusys/v3/mcucfg.h
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Copyright (c) 2025, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MCUCFG_H
|
||||
#define MCUCFG_H
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
#endif /*__ASSEMBLER__*/
|
||||
#include <platform_def.h>
|
||||
|
||||
#define MCUSYS_CPC_BASE (MCUCFG_BASE + 0x40000)
|
||||
|
||||
/* CPC related registers */
|
||||
#define CPC_FCM_SPMC_SW_CFG2 (MCUSYS_CPC_BASE + 0x004)
|
||||
#define CPC_FCM_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x010)
|
||||
#define CPC_MCUSYS_CPC_OFF_THRES (MCUSYS_CPC_BASE + 0x014)
|
||||
#define CPC_MCUSYS_PWR_CTRL (MCUSYS_CPC_BASE + 0x104)
|
||||
#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUSYS_CPC_BASE + 0x114)
|
||||
#define CPC_MCUSYS_LAST_CORE_REQ (MCUSYS_CPC_BASE + 0x118)
|
||||
#define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x11c)
|
||||
#define CPC_MCUSYS_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x124)
|
||||
#define CPC_MCUSYS_PWR_ON_MASK (MCUSYS_CPC_BASE + 0x128)
|
||||
#define CPC_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x140)
|
||||
#define CPC_CORE_CUR_FSM (MCUSYS_CPC_BASE + 0x144)
|
||||
#define CPC_WAKEUP_REQ (MCUSYS_CPC_BASE + 0x14c)
|
||||
#define CPC_MCUSYS_CPU_ON_SW_HINT_SET (MCUSYS_CPC_BASE + 0x1a8)
|
||||
#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR (MCUSYS_CPC_BASE + 0x1ac)
|
||||
#define CPC_MCUSYS_CPC_DBG_SETTING (MCUSYS_CPC_BASE + 0x200)
|
||||
#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE (MCUSYS_CPC_BASE + 0x204)
|
||||
#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE (MCUSYS_CPC_BASE + 0x208)
|
||||
#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE (MCUSYS_CPC_BASE + 0x20c)
|
||||
#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE (MCUSYS_CPC_BASE + 0x210)
|
||||
#define CPC_MCUSYS_TRACE_SEL (MCUSYS_CPC_BASE + 0x214)
|
||||
#define CPC_MCUSYS_TRACE_DATA (MCUSYS_CPC_BASE + 0x220)
|
||||
#define CPC_CPU0_LATENCY (MCUSYS_CPC_BASE + 0x240)
|
||||
#define CPC_CLUSTER_OFF_LATENCY (MCUSYS_CPC_BASE + 0x260)
|
||||
#define CPC_CLUSTER_ON_LATENCY (MCUSYS_CPC_BASE + 0x264)
|
||||
#define CPC_MCUSYS_LATENCY (MCUSYS_CPC_BASE + 0x268)
|
||||
#define CPC_MCUSYS_CLUSTER_COUNTER (MCUSYS_CPC_BASE + 0x270)
|
||||
#define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUSYS_CPC_BASE + 0x274)
|
||||
#define CPC_CPU_LATENCY(cpu) (CPC_CPU0_LATENCY + 4 * (cpu))
|
||||
|
||||
#define CPC_WDT_LATCH_INFO1 (MCUSYS_CPC_BASE + 0x280)
|
||||
#define CPC_WDT_LATCH_INFO2 (MCUSYS_CPC_BASE + 0x284)
|
||||
#define CPC_WDT_LATCH_INFO3 (MCUSYS_CPC_BASE + 0x288)
|
||||
#define CPC_WDT_LATCH_INFO4 (MCUSYS_CPC_BASE + 0x28c)
|
||||
#define CPC_WDT_LATCH_INFO5 (MCUSYS_CPC_BASE + 0x290)
|
||||
|
||||
/* CPC_MCUSYS_CPC_FLOW_CTRL_CFG bit control */
|
||||
#define CPC_CTRL_ENABLE BIT(16)
|
||||
#define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */
|
||||
#define GIC_WAKEUP_IGNORE(cpu) BIT(21 + (cpu))
|
||||
|
||||
#define CPC_MCUSYS_CPC_RESET_ON_KEEP_ON BIT(17)
|
||||
#define CPC_MCUSYS_CPC_RESET_PWR_ON_EN BIT(20)
|
||||
|
||||
#define CPC_CORE_FSM_ON BIT(3)
|
||||
|
||||
#define CPC_WAKEUP_STAT_NONE 0x0
|
||||
|
||||
/* Define SPMC_CONTROL_CONFIG */
|
||||
#define SPMC_CONTROL_CONFIG (MCUCFG_BASE + 0x480)
|
||||
|
||||
/* bit fields of SPMC_CONTROL_CONFIG */
|
||||
#define SPMC_CPU_PWR_ON_REQ BIT(0)
|
||||
#define SPMC_CPUTOP_PWR_ON_REQ BIT(8)
|
||||
#define SPMC_MCUSYS_PWR_ON_REQ BIT(9)
|
||||
#define SPMC_CPU_RESET_PWRON_CONFIG BIT(16)
|
||||
#define SPMC_CPUTOP_RESET_PWRON_CONFIG BIT(24)
|
||||
#define SPMC_MCUSYS_RESET_PWRON_CONFIG BIT(25)
|
||||
|
||||
#endif /* __MCUCFG_H__ */
|
||||
94
plat/mediatek/include/drivers/mcusys/v4/mcucfg.h
Normal file
94
plat/mediatek/include/drivers/mcusys/v4/mcucfg.h
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* Copyright (c) 2025, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MCUCFG_H
|
||||
#define MCUCFG_H
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
#endif /*__ASSEMBLER__*/
|
||||
#include <platform_def.h>
|
||||
|
||||
#define MCUSYS_CPC_BASE (MCUCFG_BASE + 0x40000)
|
||||
|
||||
/* CPC related registers */
|
||||
#define CPC_FCM_SPMC_SW_CFG2 (MCUSYS_CPC_BASE + 0x004)
|
||||
#define CPC_FCM_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x010)
|
||||
#define CPC_MCUSYS_CPC_OFF_THRES (MCUSYS_CPC_BASE + 0x014)
|
||||
#define CPC_MCUSYS_PWR_CTRL (MCUSYS_CPC_BASE + 0x104)
|
||||
#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUSYS_CPC_BASE + 0x114)
|
||||
#define CPC_MCUSYS_LAST_CORE_REQ (MCUSYS_CPC_BASE + 0x118)
|
||||
#define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x11c)
|
||||
#define CPC_MCUSYS_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x124)
|
||||
#define CPC_MCUSYS_PWR_ON_MASK (MCUSYS_CPC_BASE + 0x128)
|
||||
#define CPC_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x140)
|
||||
#define CPC_CORE_CUR_FSM (MCUSYS_CPC_BASE + 0x144)
|
||||
#define CPC_WAKEUP_REQ (MCUSYS_CPC_BASE + 0x14c)
|
||||
#define CPC_MCUSYS_CPU_ON_SW_HINT_SET (MCUSYS_CPC_BASE + 0x1a8)
|
||||
#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR (MCUSYS_CPC_BASE + 0x1ac)
|
||||
#define CPC_MCUSYS_CPC_DBG_SETTING (MCUSYS_CPC_BASE + 0x200)
|
||||
#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE (MCUSYS_CPC_BASE + 0x204)
|
||||
#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE (MCUSYS_CPC_BASE + 0x208)
|
||||
#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE (MCUSYS_CPC_BASE + 0x20c)
|
||||
#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE (MCUSYS_CPC_BASE + 0x210)
|
||||
#define CPC_MCUSYS_TRACE_SEL (MCUSYS_CPC_BASE + 0x214)
|
||||
#define CPC_MCUSYS_TRACE_DATA (MCUSYS_CPC_BASE + 0x220)
|
||||
#define CPC_CPU0_OFF_LATENCY (MCUSYS_CPC_BASE + 0x240)
|
||||
#define CPC_CPU0_ON_LATENCY (MCUSYS_CPC_BASE + 0x244)
|
||||
#define CPC_CLUSTER_OFF_LATENCY (MCUSYS_CPC_BASE + 0x280)
|
||||
#define CPC_CLUSTER_ON_LATENCY (MCUSYS_CPC_BASE + 0x284)
|
||||
#define CPC_MCUSYS_OFF_LATENCY (MCUSYS_CPC_BASE + 0x288)
|
||||
#define CPC_MCUSYS_ON_LATENCY (MCUSYS_CPC_BASE + 0x28C)
|
||||
#define CPC_MCUSYS_CLUSTER_COUNTER (MCUSYS_CPC_BASE + 0x290)
|
||||
#define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUSYS_CPC_BASE + 0x294)
|
||||
#define CPC_CPU_OFF_LATENCY(_cpu) \
|
||||
((CPC_CPU0_OFF_LATENCY) + 8 * (_cpu))
|
||||
#define CPC_CPU_ON_LATENCY(_cpu) \
|
||||
((CPC_CPU0_ON_LATENCY) + 8 * (_cpu))
|
||||
|
||||
#define CPC_WDT_LATCH_INFO1 (MCUSYS_CPC_BASE + 0x2A0)
|
||||
#define CPC_WDT_LATCH_INFO2 (MCUSYS_CPC_BASE + 0x2A4)
|
||||
#define CPC_WDT_LATCH_INFO3 (MCUSYS_CPC_BASE + 0x2A8)
|
||||
#define CPC_WDT_LATCH_INFO4 (MCUSYS_CPC_BASE + 0x2AC)
|
||||
#define CPC_WDT_LATCH_INFO5 (MCUSYS_CPC_BASE + 0x2B0)
|
||||
|
||||
/* bit fileds of CPC_MCUSYS_PWR_CTRL */
|
||||
#define CPC_MCUSYS_OFF_EN BIT(0)
|
||||
#define CPC_MCUSYS_DORMANT_EN BIT(1)
|
||||
#define CPC_MCUSYS_DP_IDLE_EN BIT(2)
|
||||
|
||||
/* CPC_MCUSYS_CPC_FLOW_CTRL_CFG bit control */
|
||||
#define CPC_CTRL_ENABLE BIT(16)
|
||||
#define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */
|
||||
#define GIC_WAKEUP_IGNORE(_cpu) BIT(21 + _cpu)
|
||||
|
||||
#define CPC_MCUSYS_CPC_RESET_ON_KEEP_ON BIT(17)
|
||||
#define CPC_MCUSYS_CPC_RESET_PWR_ON_EN BIT(20)
|
||||
|
||||
#define CPC_CORE_FSM_ON BIT(3)
|
||||
|
||||
#define CPC_WAKEUP_STAT_NONE 0x0
|
||||
|
||||
/* Define SPMC_CONTROL_CONFIG */
|
||||
#define SPMC_CONTROL_CONFIG (MCUCFG_BASE + 0x480)
|
||||
|
||||
/* bit fields of SPMC_CONTROL_CONFIG */
|
||||
#define SPMC_CPU_PWR_ON_REQ BIT(0)
|
||||
#define SPMC_CPUTOP_PWR_ON_REQ BIT(8)
|
||||
#define SPMC_MCUSYS_PWR_ON_REQ BIT(9)
|
||||
#define SPMC_CPU_RESET_PWRON_CONFIG BIT(16)
|
||||
#define SPMC_CPUTOP_RESET_PWRON_CONFIG BIT(24)
|
||||
#define SPMC_MCUSYS_RESET_PWRON_CONFIG BIT(25)
|
||||
|
||||
#ifdef CPU_PM_ACP_FSM
|
||||
/* Define MCUSYS_ACP_UTB_FSM */
|
||||
#define MCUSYS_ACP_UTB_FSM (MCUCFG_ACPBASE + 0x150)
|
||||
|
||||
#define ACP_PWR_CTRL_OP_STATUS 0x1C000
|
||||
#define ACP_PWR_CTRL_OP_ST_IDLE 0x0
|
||||
#endif /* CPU_PM_ACP_FSM */
|
||||
|
||||
#endif /* __MCUCFG_H__ */
|
||||
Loading…
Add table
Reference in a new issue