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https://github.com/ARM-software/arm-trusted-firmware.git
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95e974fa15
And mcusys drivers to enhance CPU power state control. Signed-off-by: Kai Liang <kai.liang@mediatek.com> Change-Id: I7d84407cebc16a5ab23359781574e9d02e90c58b
65 lines
2.6 KiB
C
65 lines
2.6 KiB
C
/*
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* Copyright (c) 2025, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MCUCFG_H
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#define MCUCFG_H
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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#endif /*__ASSEMBLER__*/
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#include <platform_def.h>
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#define MCUSYS_CPC_BASE (MCUCFG_BASE + 0x40000)
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/* CPC related registers */
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#define CPC_FCM_SPMC_SW_CFG2 (MCUSYS_CPC_BASE + 0x004)
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#define CPC_FCM_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x010)
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#define CPC_MCUSYS_CPC_OFF_THRES (MCUSYS_CPC_BASE + 0x014)
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#define CPC_MCUSYS_PWR_CTRL (MCUSYS_CPC_BASE + 0x104)
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#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUSYS_CPC_BASE + 0x114)
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#define CPC_MCUSYS_LAST_CORE_REQ (MCUSYS_CPC_BASE + 0x118)
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#define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x11c)
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#define CPC_MCUSYS_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x124)
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#define CPC_MCUSYS_PWR_ON_MASK (MCUSYS_CPC_BASE + 0x128)
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#define CPC_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x140)
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#define CPC_CORE_CUR_FSM (MCUSYS_CPC_BASE + 0x144)
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#define CPC_WAKEUP_REQ (MCUSYS_CPC_BASE + 0x14c)
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#define CPC_MCUSYS_CPU_ON_SW_HINT_SET (MCUSYS_CPC_BASE + 0x1a8)
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#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR (MCUSYS_CPC_BASE + 0x1ac)
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#define CPC_MCUSYS_CPC_DBG_SETTING (MCUSYS_CPC_BASE + 0x200)
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#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE (MCUSYS_CPC_BASE + 0x204)
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#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE (MCUSYS_CPC_BASE + 0x208)
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#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE (MCUSYS_CPC_BASE + 0x20c)
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#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE (MCUSYS_CPC_BASE + 0x210)
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#define CPC_MCUSYS_TRACE_SEL (MCUSYS_CPC_BASE + 0x214)
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#define CPC_MCUSYS_TRACE_DATA (MCUSYS_CPC_BASE + 0x220)
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#define CPC_CPU0_LATENCY (MCUSYS_CPC_BASE + 0x240)
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#define CPC_CLUSTER_OFF_LATENCY (MCUSYS_CPC_BASE + 0x260)
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#define CPC_CLUSTER_ON_LATENCY (MCUSYS_CPC_BASE + 0x264)
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#define CPC_MCUSYS_LATENCY (MCUSYS_CPC_BASE + 0x268)
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#define CPC_MCUSYS_CLUSTER_COUNTER (MCUSYS_CPC_BASE + 0x270)
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#define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUSYS_CPC_BASE + 0x274)
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#define CPC_CPU_LATENCY(cpu) (CPC_CPU0_LATENCY + 4 * (cpu))
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#define CPC_WDT_LATCH_INFO1 (MCUSYS_CPC_BASE + 0x280)
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#define CPC_WDT_LATCH_INFO2 (MCUSYS_CPC_BASE + 0x284)
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#define CPC_WDT_LATCH_INFO3 (MCUSYS_CPC_BASE + 0x288)
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#define CPC_WDT_LATCH_INFO4 (MCUSYS_CPC_BASE + 0x28c)
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#define CPC_WDT_LATCH_INFO5 (MCUSYS_CPC_BASE + 0x290)
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/* CPC_MCUSYS_CPC_FLOW_CTRL_CFG bit control */
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#define CPC_CTRL_ENABLE BIT(16)
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#define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */
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#define GIC_WAKEUP_IGNORE(cpu) BIT(21 + (cpu))
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#define CPC_MCUSYS_CPC_RESET_ON_KEEP_ON BIT(17)
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#define CPC_MCUSYS_CPC_RESET_PWR_ON_EN BIT(20)
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#define CPC_CORE_FSM_ON BIT(3)
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#define CPC_WAKEUP_STAT_NONE 0x0
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#endif /* __MCUCFG_H__ */
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