Update the revision and variant information in the
cortex_a78_ae.s and errata ABI file for erratum ID - 2376748
based on the latest SDEN.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest
Change-Id: I082aac41adf717b0d5d59046a8933a3f5a3de94f
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Update the revision and variant information in the
errata ABI file, cortex_A710.S file for erratum ID - 2058056
and erratum ID - 2055002 to match the revision and variant
in the latest SDEN.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest
Change-Id: Ie010dae90dabf8670f588a06f9a606cf41e22afa
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
* changes:
refactor(cm): enable S-EL2 globally for all contexts
refactor(cm): remove world differentiation for EL2 context restore
fix(cm): make ICC_SRE_EL2 fixup generic to all worlds
refactor(cm): clean up SCR_EL3 and CPTR_EL3 initialization
Currently, S-EL2 is being enabled specifically while we are in
secure context and gets toggled up when we exit secure world.
This behavior is not ideal and needs correction.
Enabling the S-EL2 via SCR_EL3.EEL2 register setting should be
global and this patch addresses it.
Change-Id: If6c39ca258f2fefa835c4b51e0f6b68165fd2e35
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
The EL2 context save/restore functions have an optimisation to not
bother with the EL2 context when SEL2 is not in use. However, this
decision is made on the current value of SCR_EL3.EEL2, which is not
the value for the selected security state, but rather, for the
security state that came before it. This relies on the EEL2 bit's
value to propagate identically to all worlds.
This has an unintended side effect that for the first entry into
secure world, the restoring of the context is fully skipped, because
SCR_EL3 is only initialized after the call to the restoring routine
which means the EEL2 bit is not initialized (except when FEAT_RME
is present). This is inconsistent with normal and realm worlds which
always get their EL2 registers zeroed.
Remove this optimization to remove all the complexity with managing
the EEL2 bit's value. Instead unconditionally save/restore all
registers. It is worth noting that there is no performance penalty
in the case where SEL2 is empty with this change. This is because
SEL2 will never be entered, and as such no secure save/restore will
happen anyway, while normal world remains unchanged.
Removing the value management of the EEL2 bit causes the
CTX_ICC_SRE_EL2 register to be inaccessible in Secure world for some
configurations.
Make the SCR_EL3.NS workaround in cm_prepare_el3_exit_ns() generic
on every access to the register.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1f56d85814c5897b468e82d4bd4a08e3a90a7f8f
For ICC_SRE_EL2.SRE the Arm ARM specifies that "If software changes this
bit from 1 to 0, the results are UNPREDICTABLE". However, the
indiscriminate zeroing of the EL2 context does just that for Secure and
Realm worlds. Make this fixup generic to avoid the problem.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Iee21ace17faf10eae52a046e6dfafc5141fa7f85
As with MDCR_EL3, setting some bits of these registers is redundant at
reset since they do not matter for EL3 execution and the registers get
context switched so they get overwritten anyway.
The SCR_EL3.{TWE, TWI, SMD, API, APK} bits only affect lower ELs so
their place is in context management. The API and APK bits are a bit
special as they would get implicitly unset for secure world when
CTX_INCLUDE_PAUTH_REGS is unset. This is now explicit with their normal
world values being always set as PAuth defaults to enabled. The same
sequence is also added to realm world too. The reasoning is the same as
for Secure world - PAuth will be enabled for NS, and unless explicitly
handled by firmware, it should not leak to realm.
The CPTR_EL3.{ESM, EZ, TAM} bits are set by the relevant
feat_enable()s in lib/extensions so they can be skipped too.
CPTR_EL3.TFP is special as it's needed for access to generic floating
point registers even when SVE is not present. So keep it but move to
context management.
This leaves CPTR_EL3.TCPAC which affects several extensions. This bit
was set centrally at reset, however the earliest need for it is in BL2.
So set it in cm_setup_context_common(). However, this CPTR_EL3 is only
restored for BL31 which is clearly not the case. So always restore it.
Finally, setting CPTR_EL3 to a fresh RESET_VAL for each security state
prevents any bits from leaking between them.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie7095e967bd4a6d6ca6acf314c7086d89fec8900
Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all
revisions <= r1p2 and is still open.
The workaround is to write the value 4'b1001 to the PF_MODE bits
in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher
in the most conservative mode instead of disabling it.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Add transfer list APIs and firmware handoff build option.
Change-Id: I68a0ace22c7e50fcdacd101eb76b271d7b76d8ff
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
This patch fixes the mitigation for erratum 1941500 for the
Cortex-A78AE CPUs. The right fix is to set the bit 8, whereas
the current code clears it.
Reported-by: matthias.rosenfelder@nio.io
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ib7c3fddd567eeae6204756377e0f77a573c0a911
Neoverse V2 erratum 2743011 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I0e06ca723a1cce51fb027b7160f3dd06a4c93e64
Neoverse V2 erratum 2779510 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set bit[47] of CPUACTLR3_EL1 which might have a small impact on
power and negligible impact on performance.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I6d937747bdcbf2913a64c4037f99918cbc466e80
Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations
to other PE caches. There might be a small performance degradation
to this workaround for certain workloads that share data.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id026edcb7ee1ca93371ce0001d18f5a8282c49ba
Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all
revisions <= r0p2 and is still open. The workaround is to write the
value 4'b1001 to the PF_MODE bits in the IMP_CPUECTLR2_EL1 register
which will place the data prefetcher in the most conservative mode
instead of disabling it.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ic6c76375df465a4ad2e20dd7add7037477d973c1
Cortex-X3 erratum 2742421 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Change-Id: Idadd323e419739fe909b9b68ea2dbe857846666b
Neoverse N2 erratum 2009478 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to clear
the ED bit for all core error records before setting the PWRDN_EN
bit in CPUPWRCTLR_EL1 to request a power down.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ic5ef58c9e795b90026af1d2b09edc0eea3ceee51
Adding basic CPU library code to support Nevis CPU
Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
* changes:
refactor(cpus): convert the Cortex-A57 to use cpu helpers
refactor(cpus): convert the Cortex-A57 to use the errata framework
refactor(cpus): reorder Cortex-A57 errata by ascending order
refactor(cpus): add Cortex-A57 errata framework information
refactor(cpus): convert the Cortex-A53 to use cpu helpers
refactor(cpus): convert the Cortex-A53 to use the errata framework
refactor(cpus): reorder Cortex-A53 errata by ascending order
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.
At this point the binary output of all errata was checked with the
script from commit 19136. All reported discrepancies involve errata
with no workaround in the cpu file or errata that did not previously
have a workaround function and now do. The non temporal hint erratum has
been converted to a numeric erratum.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ib321ab01362c5954fe78e7349229c1437b3da847
Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition
level.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ia98976797fc0811f30c7dbf714e94b36e3c2263e
Also, convert checker functions of errata which are enabled for all cpu
revisions to report correctly in preparation of the errata ABI.
Although the script from commit 250919 was used to check that errata
code did not change, this CPU only loosely adhered to convention and its
output was not particularly useful. Nevertheless, the discrepancies were
manually verified. All errata have been checked that they get invoked.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I988db6e7b6d1732f1d2258dbdf945cb475781894
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround and checking
sequences remain unchanged and preserve their git blame.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I30556f438859d17f054cb6bc96f3069b40474b58
Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition
level.
Also rename the disable_non_temporal_hint to its erratum number to
conform to convention.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Id474872afebf361ab3d21c454ab3624db8354045
The original powerdown function for Gelas included SME disabling
instructions but did not check for the presence of SME before disabling.
This could lead to unexpected beaviors. This patch adds that check so
the feature is disabled only if it is present.
Change-Id: I582db53a6669317620e4f72a3eac87525897d3d0
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
MTE and common system registers are the last remaining EL2 save/restores
in assembly. Convert them to C, like all the others.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: If690f792e70b97fd4b4cd5f43847a71719b128f1
This patch adds the necessary CPU library code to support the Gelas CPU
Change-Id: I13ec4a8bb7055c1ebd0796a4a1378983d930fcb3
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.
Testing was conducted by:
* Manual comparison of disassembly of converted functions with non-
converted functions
aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf
* Build for release with all errata flags enabled and run default tftf
tests
CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp DEBUG=0 \
CTX_INCLUDE_AARCH32_REGS=0 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0 \
BL33=./../tf-a-tests/build/fvp/release/tftf.bin \
WORKAROUND_CVE_2022_23960=1 ERRATA_ABI_SUPPORT=1 all fip
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.
Change-Id: I34e27e468d4f971423a03a95a4a52f4af8bd783a
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Convert Neoverse V2 to use CPU helpers, in this case that's
only two spots.
Change-Id: Icd250f92974e8a50c459038de7644a2e68007589
Signed-off-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
For V2, this involves replacing:
- The reset_func with the standard cpu_reset_func_{start,end}
to apply errata automatically
- The <cpu>_errata_report with the errata_report_shim to
report errata automatically
And for each erratum:
- The prologue with the workaround_<type>_start to do the checks and
framework registration automatically at reset or runtime
- The epilogue with the workaround_<type>_end
- The checker function with the check_erratum_<type> to check whether
the erratum applies on the revision of the CPU.
It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.
Testing was conducted by:
* Manual comparison of disassembly of converted functions with non-
converted functions
aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf
* Build for release with all errata flags enabled and run default tftf
tests
CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp CTX_INCLUDE_AARCH32_REGS=0 \
HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0 \
BL33=./../tf-a-tests/build/fvp/debug/tftf.bin \
ERRATA_V2_2801372 WORKAROUND_CVE_2022_23960=1 ERRATA_ABI_SUPPORT=1 all fip
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.
Change-Id: Ic968844d6aabea3867189d747769ced8faa87e56
Signed-off-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Not including the proper CPU file can halt execution at the
reset_handler since the cpu_ops obtained will be invalid and therefore
the cpu reset function will be invalid too, unless SUPPORT_UNKNOWN_MPID
is enabled.
This patch adds an assert to check for the validity of the obtained
cpu_ops object and will display an error if the object is invalid.
Change-Id: I0e1661745e4a692aab5e910e110c2de0caf64f46
Signed-off-by: Thaddeus Serna <Thaddeus.Gonzalez-Serna@arm.com>
Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an
(optional) integrated L2 cache that might need to be flushed if the
whole cluster is powered down. However, unlike Cortex-A53 there is
currently no L2 cache flush in the cluster_pwr_dwn implementation for
some reason. This causes problems if there is unwritten data left in
the L2 cache during a cluster power off.
Fix this by adding the L2 cache flush similar to cortex_a53.S.
Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Align entire TF-A to use Arm in copyright header.
Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
override_vector_table does adr, followed by an msr ops.
Accidentally was used here for for adr and mrs op.
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
Change-Id: I2d3fda12acd097acabbde9b7dcc376d08419e223
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround and checking
sequences remain unchanged and preserve their git blame. Testing was
conducted by:
* Building for release with all errata flags enabled and running script
in change 19136 to compare output of objdump for each errata.
* Manual comparison of disassembly of converted functions with non-
converted functions
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I417539ab292f13a4f0949625d2fef6b7792fbd35
Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition
level.
Change-Id: I4a6ed55d48e91ec914b7a591c6d30da5ce5d915d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
