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f0c96a2e35
As with MDCR_EL3, setting some bits of these registers is redundant at
reset since they do not matter for EL3 execution and the registers get
context switched so they get overwritten anyway.
The SCR_EL3.{TWE, TWI, SMD, API, APK} bits only affect lower ELs so
their place is in context management. The API and APK bits are a bit
special as they would get implicitly unset for secure world when
CTX_INCLUDE_PAUTH_REGS is unset. This is now explicit with their normal
world values being always set as PAuth defaults to enabled. The same
sequence is also added to realm world too. The reasoning is the same as
for Secure world - PAuth will be enabled for NS, and unless explicitly
handled by firmware, it should not leak to realm.
The CPTR_EL3.{ESM, EZ, TAM} bits are set by the relevant
feat_enable()s in lib/extensions so they can be skipped too.
CPTR_EL3.TFP is special as it's needed for access to generic floating
point registers even when SVE is not present. So keep it but move to
context management.
This leaves CPTR_EL3.TCPAC which affects several extensions. This bit
was set centrally at reset, however the earliest need for it is in BL2.
So set it in cm_setup_context_common(). However, this CPTR_EL3 is only
restored for BL31 which is clearly not the case. So always restore it.
Finally, setting CPTR_EL3 to a fresh RESET_VAL for each security state
prevents any bits from leaking between them.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie7095e967bd4a6d6ca6acf314c7086d89fec8900
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| .. | ||
| aarch32 | ||
| aarch64 | ||
| bl_aux_params | ||
| compiler-rt | ||
| coreboot | ||
| cpus | ||
| debugfs | ||
| el3_runtime | ||
| extensions | ||
| fconf | ||
| gpt_rme | ||
| libc | ||
| libfdt | ||
| locks | ||
| mpmm | ||
| optee | ||
| pmf | ||
| psa | ||
| psci | ||
| romlib | ||
| semihosting | ||
| stack_protector | ||
| transfer_list | ||
| utils | ||
| xlat_mpu | ||
| xlat_tables | ||
| xlat_tables_v2 | ||
| zlib | ||