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Merge changes from topic "errata" into integration

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* changes:
  fix(cpus): workaround for Neoverse V2 erratum 2743011
  fix(cpus): workaround for Neoverse V2 erratum 2779510
  fix(cpus): workaround for Neoverse V2 erratum 2719105
  fix(cpus): workaround for Neoverse V2 erratum 2331132
This commit is contained in:
Lauren Wehrmeister 2023-09-22 20:22:19 +02:00 • committed by TrustedFirmware Code Review
commit fcfa15d41c
5 changed files with 93 additions and 4 deletions
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16
docs/design/cpu-specific-build-macros.rst
View file

@ -523,11 +523,27 @@ For Neoverse V1, the following errata build flags are defined :
For Neoverse V2, the following errata build flags are defined :
- ``ERRATA_V2_2331132``: This applies errata 2331132 workaround to Neoverse-V2
CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still
open.
- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2
CPU, this affects system configurations that do not use and ARM interconnect
IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed
in r0p2.
- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
r0p2.
- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
r0p2.
- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
r0p2.
- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2
CPU, this affects all configurations. This needs to be enabled for revisions
r0p0 and r0p1. It has been fixed in r0p2.

29
include/lib/cpus/aarch64/neoverse_v2.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -23,4 +23,31 @@
#define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
/*******************************************************************************
* CPU Extended Control register 2 specific definitions.
******************************************************************************/
#define NEOVERSE_V2_CPUECTLR2_EL1 S3_0_C15_C1_5
#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11)
#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
/*******************************************************************************
* CPU Auxiliary Control register 2 specific definitions.
******************************************************************************/
#define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1
#define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
/*******************************************************************************
* CPU Auxiliary Control register 3 specific definitions.
******************************************************************************/
#define NEOVERSE_V2_CPUACTLR3_EL1 S3_0_C15_C1_2
#define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
/*******************************************************************************
* CPU Auxiliary Control register 5 specific definitions.
******************************************************************************/
#define NEOVERSE_V2_CPUACTLR5_EL1 S3_0_C15_C8_0
#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
#endif /* NEOVERSE_V2_H */

26
lib/cpus/aarch64/neoverse_v2.S
View file

@ -22,6 +22,32 @@
#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132
sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH
workaround_reset_end neoverse_v2, ERRATUM(2331132)
check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2)
workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105
sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0
workaround_reset_end neoverse_v2, ERRATUM(2719105)
check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1)
workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011
sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55
sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56
workaround_reset_end neoverse_v2, ERRATUM(2743011)
check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1)
workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510
sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47
workaround_reset_end neoverse_v2, ERRATUM(2779510)
check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1)
workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
/* dsb before isb of power down sequence */
dsb sy

16
lib/cpus/cpu-ops.mk
View file

@ -794,10 +794,26 @@ CPU_FLAG_LIST += ERRATA_A510_2666669
# Cortex-A510 cpu and is fixed in r1p3.
CPU_FLAG_LIST += ERRATA_A510_2684597
# Flag to apply erratum 2331132 workaround during reset. This erratum applies
# to revisions r0p0, r0p1 and r0p2. It is still open.
CPU_FLAG_LIST += ERRATA_V2_2331132
# Flag to apply erratum 2719103 workaround for non-arm interconnect ip. This
# erratum applies to revisions r0p0, rop1. Fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2719103
# Flag to apply erratum 2719105 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2719105
# Flag to apply erratum 2743011 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2743011
# Flag to apply erratum 2779510 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2779510
# Flag to apply erratum 2801372 workaround for all configurations.
# This erratum applies to revisions r0p0, r0p1. Fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2801372

10
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -400,10 +400,14 @@ struct em_cpu_list cpu_list[] = {
{
.cpu_partnumber = NEOVERSE_V2_MIDR,
.cpu_errata_list = {
[0] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \
[0] = {2331132, 0x00, 0x02, ERRATA_V2_2331132},
[1] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \
ERRATA_NON_ARM_INTERCONNECT},
[1] = {2801372, 0x00, 0x01, ERRATA_V2_2801372},
[2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
[2] = {2719105, 0x00, 0x01, ERRATA_V2_2719105},
[3] = {2743011, 0x00, 0x01, ERRATA_V2_2743011},
[4] = {2779510, 0x00, 0x01, ERRATA_V2_2779510},
[5] = {2801372, 0x00, 0x01, ERRATA_V2_2801372},
[6 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_V2_H_INC */