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fix(cpus): flush L2 cache for Cortex-A7/12/15/17

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Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an
(optional) integrated L2 cache that might need to be flushed if the
whole cluster is powered down. However, unlike Cortex-A53 there is
currently no L2 cache flush in the cluster_pwr_dwn implementation for
some reason. This causes problems if there is unwritten data left in
the L2 cache during a cluster power off.

Fix this by adding the L2 cache flush similar to cortex_a53.S.

Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
This commit is contained in:
Stephan Gerhold 2023-03-19 20:30:58 +01:00
parent 2360d18bb5
commit c5c160cddd
4 changed files with 16 additions and 0 deletions
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4
lib/cpus/aarch32/cortex_a12.S
View file

@ -64,6 +64,10 @@ func cortex_a12_cluster_pwr_dwn
bl plat_disable_acp
/* Flush L2 caches */
mov r0, #DC_OP_CISW
bl dcsw_op_level2
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a12_disable_smp

4
lib/cpus/aarch32/cortex_a15.S
View file

@ -163,6 +163,10 @@ func cortex_a15_cluster_pwr_dwn
bl plat_disable_acp
/* Flush L2 caches */
mov r0, #DC_OP_CISW
bl dcsw_op_level2
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a15_disable_smp

4
lib/cpus/aarch32/cortex_a17.S
View file

@ -159,6 +159,10 @@ func cortex_a17_cluster_pwr_dwn
bl plat_disable_acp
/* Flush L2 caches */
mov r0, #DC_OP_CISW
bl dcsw_op_level2
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a17_disable_smp

4
lib/cpus/aarch32/cortex_a7.S
View file

@ -64,6 +64,10 @@ func cortex_a7_cluster_pwr_dwn
bl plat_disable_acp
/* Flush L2 caches */
mov r0, #DC_OP_CISW
bl dcsw_op_level2
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a7_disable_smp