mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
refactor(cpus): convert the Cortex-A53 to use the errata framework
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround and checking
sequences remain unchanged and preserve their git blame.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I30556f438859d17f054cb6bc96f3069b40474b58
This commit is contained in:
Boyan Karatotev
Sona Mathew
parent
e37dfd3c57
commit
b2d78e1c41
1 changed files with 46 additions and 185 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -12,11 +12,6 @@
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#include <plat_macros.S>
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#include <lib/cpus/errata.h>
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#if A53_DISABLE_NON_TEMPORAL_HINT
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#undef ERRATA_A53_836870
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#define ERRATA_A53_836870 1
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#endif
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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@ -42,14 +37,8 @@ func cortex_a53_disable_smp
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ret
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endfunc cortex_a53_disable_smp
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #819472.
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* This applies only to revision <= r0p1 of Cortex A53.
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* Due to the nature of the errata it is applied unconditionally
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* when built in, report it as applicable in this case
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* ---------------------------------------------------
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*/
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func check_errata_819472
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/* Due to the nature of the errata it is applied unconditionally when chosen */
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check_erratum_custom_start cortex_a53, ERRATUM(819472)
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#if ERRATA_A53_819472
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mov x0, #ERRATA_APPLIES
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ret
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@ -57,16 +46,13 @@ func check_errata_819472
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mov x1, #0x01
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b cpu_rev_var_ls
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#endif
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endfunc check_errata_819472
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check_erratum_custom_end cortex_a53, ERRATUM(819472)
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #824069.
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* This applies only to revision <= r0p2 of Cortex A53.
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* Due to the nature of the errata it is applied unconditionally
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* when built in, report it as applicable in this case
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* ---------------------------------------------------
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*/
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func check_errata_824069
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/* erratum workaround is interleaved with generic code */
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add_erratum_entry cortex_a53, ERRATUM(819472), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
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/* Due to the nature of the errata it is applied unconditionally when chosen */
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check_erratum_custom_start cortex_a53, ERRATUM(824069)
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#if ERRATA_A53_824069
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mov x0, #ERRATA_APPLIES
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ret
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@ -74,44 +60,22 @@ func check_errata_824069
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mov x1, #0x02
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b cpu_rev_var_ls
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#endif
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endfunc check_errata_824069
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check_erratum_custom_end cortex_a53, ERRATUM(824069)
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/* --------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #826319.
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* This applies only to revision <= r0p2 of Cortex A53.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a53_826319_wa
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/*
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* Compare x0 against revision r0p2
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*/
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mov x17, x30
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bl check_errata_826319
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cbz x0, 1f
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/* erratum workaround is interleaved with generic code */
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add_erratum_entry cortex_a53, ERRATUM(824069), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
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workaround_reset_start cortex_a53, ERRATUM(826319), ERRATA_A53_826319
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mrs x1, CORTEX_A53_L2ACTLR_EL1
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bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN
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orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH
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msr CORTEX_A53_L2ACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a53_826319_wa
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workaround_reset_end cortex_a53, ERRATUM(826319)
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func check_errata_826319
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mov x1, #0x02
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b cpu_rev_var_ls
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endfunc check_errata_826319
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check_erratum_ls cortex_a53, ERRATUM(826319), CPU_REV(0, 2)
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #827319.
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* This applies only to revision <= r0p2 of Cortex A53.
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* Due to the nature of the errata it is applied unconditionally
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* when built in, report it as applicable in this case
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* ---------------------------------------------------
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*/
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func check_errata_827319
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/* Due to the nature of the errata it is applied unconditionally when chosen */
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check_erratum_custom_start cortex_a53, ERRATUM(827319)
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#if ERRATA_A53_827319
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mov x0, #ERRATA_APPLIES
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ret
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@ -119,14 +83,12 @@ func check_errata_827319
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mov x1, #0x02
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b cpu_rev_var_ls
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#endif
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endfunc check_errata_827319
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check_erratum_custom_end cortex_a53, ERRATUM(827319)
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/*
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* Errata workaround for Cortex A53 Errata #835769.
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* This applies to revisions <= r0p4 of Cortex A53.
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* This workaround is statically enabled at build time.
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*/
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func check_errata_835769
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/* erratum workaround is interleaved with generic code */
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add_erratum_entry cortex_a53, ERRATUM(827319), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
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check_erratum_custom_start cortex_a53, ERRATUM(835769)
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cmp x0, #0x04
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b.hi errata_not_applies
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/*
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@ -144,50 +106,28 @@ errata_not_applies:
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mov x0, #ERRATA_NOT_APPLIES
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exit_check_errata_835769:
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ret
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endfunc check_errata_835769
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check_erratum_custom_end cortex_a53, ERRATUM(835769)
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/* ---------------------------------------------------------------------
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/* workaround at build time */
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add_erratum_entry cortex_a53, ERRATUM(835769), ERRATA_A53_835769, NO_APPLY_AT_RESET
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/*
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* Disable the cache non-temporal hint.
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*
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* This ignores the Transient allocation hint in the MAIR and treats
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* allocations the same as non-transient allocation types. As a result,
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* the LDNP and STNP instructions in AArch64 behave the same as the
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* equivalent LDP and STP instructions.
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*
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* This is relevant only for revisions <= r0p3 of Cortex-A53.
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* From r0p4 and onwards, the bit to disable the hint is enabled by
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* default at reset.
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*
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ---------------------------------------------------------------------
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*/
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func errata_a53_836870_wa
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/*
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* Compare x0 against revision r0p3
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*/
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mov x17, x30
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bl check_errata_836870
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cbz x0, 1f
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workaround_reset_start cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT
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mrs x1, CORTEX_A53_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH
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msr CORTEX_A53_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a53_836870_wa
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workaround_reset_end cortex_a53, ERRATUM(836870)
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func check_errata_836870
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mov x1, #0x03
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b cpu_rev_var_ls
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endfunc check_errata_836870
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check_erratum_ls cortex_a53, ERRATUM(836870), CPU_REV(0, 3)
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/*
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* Errata workaround for Cortex A53 Errata #843419.
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* This applies to revisions <= r0p4 of Cortex A53.
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* This workaround is statically enabled at build time.
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*/
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func check_errata_843419
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check_erratum_custom_start cortex_a53, ERRATUM(843419)
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mov x1, #ERRATA_APPLIES
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mov x2, #ERRATA_NOT_APPLIES
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cmp x0, #0x04
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@ -204,81 +144,31 @@ func check_errata_843419
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mov x0, x2
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exit_check_errata_843419:
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ret
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endfunc check_errata_843419
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check_erratum_custom_end cortex_a53, ERRATUM(843419)
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/* --------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #855873.
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*
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* This applies only to revisions >= r0p3 of Cortex A53.
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/* workaround at build time */
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add_erratum_entry cortex_a53, ERRATUM(843419), ERRATA_A53_843419, NO_APPLY_AT_RESET
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/*
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* Earlier revisions of the core are affected as well, but don't
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* have the chicken bit in the CPUACTLR register. It is expected that
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* the rich OS takes care of that, especially as the workaround is
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* shared with other erratas in those revisions of the CPU.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a53_855873_wa
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/*
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* Compare x0 against revision r0p3 and higher
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*/
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mov x17, x30
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bl check_errata_855873
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cbz x0, 1f
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workaround_reset_start cortex_a53, ERRATUM(855873), ERRATA_A53_855873
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mrs x1, CORTEX_A53_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
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msr CORTEX_A53_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a53_855873_wa
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workaround_reset_end cortex_a53, ERRATUM(855873)
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func check_errata_855873
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mov x1, #0x03
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b cpu_rev_var_hs
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endfunc check_errata_855873
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check_erratum_hs cortex_a53, ERRATUM(855873), CPU_REV(0, 3)
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/* --------------------------------------------------
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* Errata workaround for Cortex A53 Errata #1530924.
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* This applies to all revisions of Cortex A53.
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* --------------------------------------------------
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*/
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func check_errata_1530924
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#if ERRATA_A53_1530924
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_1530924
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check_erratum_chosen cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A53.
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* Shall clobber: x0-x19
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* -------------------------------------------------
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*/
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func cortex_a53_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A53_826319
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mov x0, x18
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bl errata_a53_826319_wa
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#endif
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#if ERRATA_A53_836870
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mov x0, x18
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bl errata_a53_836870_wa
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#endif
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#if ERRATA_A53_855873
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mov x0, x18
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bl errata_a53_855873_wa
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#endif
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/* erratum has no workaround in the cpu. Generic code must take care */
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add_erratum_entry cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924, NO_APPLY_AT_RESET
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cpu_reset_func_start cortex_a53
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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@ -286,9 +176,7 @@ func cortex_a53_reset_func
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mrs x0, CORTEX_A53_ECTLR_EL1
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orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT
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msr CORTEX_A53_ECTLR_EL1, x0
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isb
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ret x19
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endfunc cortex_a53_reset_func
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cpu_reset_func_end cortex_a53
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func cortex_a53_core_pwr_dwn
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mov x18, x30
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@ -351,34 +239,7 @@ func cortex_a53_cluster_pwr_dwn
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b cortex_a53_disable_smp
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endfunc cortex_a53_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A53. Must follow AAPCS.
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*/
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func cortex_a53_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A53_819472, cortex_a53, 819472
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report_errata ERRATA_A53_824069, cortex_a53, 824069
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report_errata ERRATA_A53_826319, cortex_a53, 826319
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report_errata ERRATA_A53_827319, cortex_a53, 827319
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report_errata ERRATA_A53_835769, cortex_a53, 835769
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report_errata ERRATA_A53_836870, cortex_a53, 836870
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report_errata ERRATA_A53_843419, cortex_a53, 843419
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report_errata ERRATA_A53_855873, cortex_a53, 855873
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report_errata ERRATA_A53_1530924, cortex_a53, 1530924
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a53_errata_report
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#endif
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errata_report_shim cortex_a53
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/* ---------------------------------------------
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* This function provides cortex_a53 specific
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