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Merge changes from topic "ar/errata_refactor" into integration
* changes: refactor(cpus): convert Neoverse V2 to use CPU helpers refactor(cpus): convert Neoverse V2 to framework
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commit
50d89e3016
1 changed files with 26 additions and 78 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -22,6 +22,25 @@
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#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
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check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1)
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workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Neoverse-V2 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_neoverse_v2
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#endif /* IMAGE_BL31 */
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workaround_reset_end neoverse_v2, CVE(2022,23960)
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check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
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#endif /* WORKAROUND_CVE_2022_23960 */
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@ -35,90 +54,19 @@ func neoverse_v2_core_pwr_dwn
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1
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orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0
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#if ERRATA_V2_2801372
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mov x15, x30
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bl cpu_get_rev_var
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bl errata_neoverse_v2_2801372_wa
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mov x30, x15
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#endif /* ERRATA_V2_2801372 */
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sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
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isb
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ret
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endfunc neoverse_v2_core_pwr_dwn
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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/* ----------------------------------------------------
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* Errata Workaround for Neoverse V2 Errata #2801372
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* This applies to revisions <= r0p1 and is fixed in r0p2.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ----------------------------------------------------
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*/
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func errata_neoverse_v2_2801372_wa
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mov x17, x30
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bl check_errata_2801372
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cbz x0, 1f
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/* dsb before isb of power down sequence */
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dsb sy
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1:
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ret x17
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endfunc errata_neoverse_v2_2801372_wa
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func check_errata_2801372
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/* Applies to all revisions <= r0p1 */
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mov x1, #0x01
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b cpu_rev_var_ls
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endfunc check_errata_2801372
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func neoverse_v2_reset_func
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cpu_reset_func_start neoverse_v2
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end neoverse_v2
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Neoverse V2 vectors are overridden to apply
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* errata mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_neoverse_v2
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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isb
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ret
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endfunc neoverse_v2_reset_func
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#if REPORT_ERRATA
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/*
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* Errata printing function for Neoverse V2. Must follow AAPCS.
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*/
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func neoverse_v2_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata WORKAROUND_CVE_2022_23960, neoverse_v2, cve_2022_23960
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report_errata ERRATA_V2_2801372, neoverse_v2, 2801372
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ldp x8, x30, [sp], #16
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ret
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endfunc neoverse_v2_errata_report
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#endif
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errata_report_shim neoverse_v2
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/* ---------------------------------------------
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* This function provides Neoverse V2-
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* specific register information for crash
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