This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.
The `silent` and `verbose` variables are boolean values determining
whether the build system has been configured to run silently or
verbosely respectively (i.e. with `--silent` or `V=1`).
These two modes cannot be used together - if `silent` is truthy then
`verbose` is always falsy. As such:
make --silent V=1
... results in a silent build.
In addition to these boolean variables, we also introduce two new
variables - `s` and `q` - for use in rule recipes to conditionally
suppress the output of commands.
When building silently, `s` expands to a value which disables the
command that follows, and `q` expands to a value which supppresses
echoing of the command:
$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed but not echoed'
When building verbosely, `s` expands to a value which disables the
command that follows, and `q` expands to nothing:
$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed and echoed'
In all other cases, both `s` and `q` expand to a value which suppresses
echoing of the command that follows:
$(s)echo 'This command is executed but not echoed'
$(q)echo 'This command is executed but not echoed'
The `s` variable is predominantly useful for `echo` commands, where you
always want to suppress echoing of the command itself, whilst `q` is
more useful for all other commands.
Change-Id: I8d8ff6ed714d3cb401946c52955887ed7dca602b
Signed-off-by: Chris Kay <chris.kay@arm.com>
Building the default upstream configuration for the imx8mq-evk is no longer
possible: The linker will complain that the TF-A image will no longer
fit On-Chip SRAM.
In order to make the i.MX8MQ Image buildable again, let's make the DRAM
retention feature optional: It was added in v2.9 and it's possible to
boot the systems without it. Users that make space elsewhere and wish to
enable it can use the newly introduced IMX_DRAM_RETENTION parameter to
configure it. The parameter is added to all i.MX8M variants, but only
for i.MX8MQ, we disable it by default, as that's the one that currently
has binary size problems.
Change-Id: I714f8ea96f18154db02390ba500f4a2dc5329ee7
Fixes: dd108c3c1f ("feat(imx8mq): add the dram retention support for imx8mq")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* changes:
feat(imx8mp): optionally take params from BL2
feat(imx8mn): optionally take params from BL2
feat(imx8mm): optionally take params from BL2
feat(imx93): optionally take params from BL2
feat(imx): add helper to take params from BL2
The imx8mq socs communicate with the HAB rom via the TF-A. But the
imx_hab_handler servicing the call wasn't compiled in as of now -
resulting in failed HAB rom calls.
Change-Id: I4ea6164047d5a927aa90f7b1176d45536876843e
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
Refactor console_flush() and console_switch_state(CONSOLE_FLAG_RUNTIME)
to bl31_main(). This has been done per the recommendation in TF-A
mailing list. These calls need to be the last calls, after any runtime
initialization has been done, before BL31 exits.
All platforms that override the generic implementation of
bl31_plat_runtime_setup() have been refactored. The console_flush()
and console_switch_state() calls have been removed as they become
part of bl31_main() function.
Any platform that don't need to make any change to the generic (weak)
implementation of bl31_plat_runtime_setup() don't need to override it
in their platforms.
Change-Id: I6d04d6daa9353daeaa7e3df9e9adf6f322a917b8
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.
TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.
This patch affects the Freescale/NXP SoCs imx93, imx8qm and imx8qx.
Change-Id: Iece74579e1d15eeeb8279db0c53d74bce45545bd
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
This function causes the build message to be generated and compiled in
two different ways, with one way done inside `build_macros.mk` and the
other done inside `windows.mk`, mostly because it's done by generating
the C file on the command line.
We can instead replace this whole build message generation sequence with
a simple standard C compilation command and a normal C file.
Change-Id: I8bc136380c9585ddeec9a11154ee39ef70526f81
Signed-off-by: Chris Kay <chris.kay@arm.com>
Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if arg0 can safely be accessed as a pointer and actually
contains a bl_params_t structure. If not, the hardcoded parameter
values are used as before.
Change-Id: I44537ba2baa7543e459e5691b69df14b0bd6e942
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if arg0 can safely be accessed as a pointer and actually
contains a bl_params_t structure. If not, the hardcoded parameter
values are used as before.
Change-Id: Ia12d35778f4d550860e517f2a1f5c5d062f3283a
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if arg0 can safely be accessed as a pointer and actually
contains a bl_params_t structure. If not, the hardcoded parameter
values are used as before.
Change-Id: I06b3012c67e43ea1e42946d863226bd93ccd4638
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if arg0 can safely be accessed as a pointer and actually
contains a bl_params_t structure. If not, the hardcoded parameter
values are used as before.
Change-Id: Iec885405efd31a6bf6c0e6c532f8d2f31c023333
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
So far the i.MX BL31 doesn't take any parameters. This means the BL32
image base address and whether or not a BL32 image is used at all has to
be hardcoded in BL31.
This adds a helper function that allows to take params from BL2 safely.
On i.MX BL2 is usually U-Boot SPL which passes random values in arg0,
so make sure arg0 is within the internal SRAM range before accessing it
as a pointer. Also make sure arg0 is sufficiently aligned and the header
type and version is correct.
Change-Id: Idab8013a1d6dabf50a83c75f3e6f831de4a537e9
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On the i.MX8M SoCs, TF-A doesn't itself initialize the UART, but depends
on BL2 to set it up beforehand. To allow using the same TF-A binary on
boards with different UART assignment, TF-A On i.MX8M M/N/P supports
dynamically determining the UART in use. The code is also applicable to
the i.MX8MQ, so enable it there too.
Change-Id: I9ba70f7068e762da979bd103390fa006c3a5d480
Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* changes:
style(imx8m): add parenthesis to CSU_HP_REG
feat(imx8mp): restrict peripheral access to secure world
feat(imx8mp): set and lock almost all peripherals as non-secure
feat(imx8mm): restrict peripheral access to secure world
feat(imx8mm): set and lock almost all peripherals as non-secure
feat(imx8m): add defines for csu_sa access security
feat(imx8m): add imx csu_sa enum type defines for imx8m
fix(imx8m): fix CSU_SA_REG to work with all sa registers
This patch gives i.MX8ULP's HIFI4 DSP R/W access to the
following additional resources (peripherals):
1) LPUART7
2) IOMUXC1
3) PCC4
4) CGC1
Doing this allows the firmware running on the DSP to
set up serial communication, which also requires doing
pinctrl and clock management-related operations.
Access to the aforementioned resources is given by
configuring the XRDC module.
Change-Id: Ie3ca9f22bb625b2463870158875f503c3c1d6452
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
To be inline with CSU_SA_REG and CSU_HPCONTROL_REG.
Change-Id: Ia7332096312df41a8cf994d58fad76a99493dd02
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
This restricts and locks all security relevant peripherals to only be
changeable by the secure world. Otherwise the normal world can simply
change the access settings and defeat all security measures put in
place.
Change-Id: I248ef8dd67f1de7e528c3da456311bb138b77540
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
This sets and locks all peripheral type-1 masters, except CAAM, access
as non-secure, so that they can't access secure world resources from the
normal world.
The CAAM itself is TrustZone aware and handles memory access between the
normal world and the secure world on its own. Pinning it as non-secure
access results in bus aborts if the secure memory region is protected by
the TZASC380.
Change-Id: Iedf3d67481dc35d56aa7b291749b999a56d6e85e
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
This restricts and locks all security relevant peripherals to only be
changeable by the secure world. Otherwise the normal world can simply
change the access settings and defeat all security measures put in
place.
Change-Id: I484a2c8164e58b68256d829470e00d5ec473e266
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
This sets and locks all peripheral type-1 masters, except CAAM, access
as non-secure, so that they can't access secure world resources from the
normal world.
The CAAM itself is TrustZone aware and handles memory access between the
normal world and the secure world on its own. Pinning it as non-secure
access results in bus aborts if the secure memory region is protected by
the TZASC380.
Change-Id: Idba4d8a491ccce0491489c61e73545baab1889c4
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
This enables the usage of speaking defines instead of magic numbers:
CSU_SA(CSU_SA_SDMA1, 1, LOCKED)
becomes:
CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED)
Change-Id: Idcabcda677bf7840084a2ea66d321b50aa0b2b20
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
This ports the missing enum defines for the central security unit found
in NXPs i.MX8M socs. The defines itself where imported from NXP's
downstream version of the trusted-firmware-a version 2.8[1].
[1]: https://github.com/nxp-imx/imx-atf/commit/0c52279fc4
Change-Id: Iad0c5d3733e9d29ead86334ba4bc5ce915018142
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
The csu found in the imx8mp has 3 csu_sa registers, before the fix not
all of them could be addressed.
The defines itself was imported from NXP's downstream version of the
trusted-firmware-a version 2.8[1].
[1]: https://github.com/nxp-imx/imx-atf/commit/0c52279fc4
Change-Id: Ia3653118bba82df9244c819a5c5f37bdc4e89c49
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
the mmap region num is not enough for the mmap regions,
so increase it, increase the xlat_table num too.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2a2515b291e96cc12398a2c2c526351342811fff
below commit mapped 16 MB memory from the start of DRAM(0x80000000),
which may have conflict with the shared memory used by Trusty OS:
LF-8819: plat: imx8ulp: ddrc switch auto low power and software interface
change the mapped memory to 'vdev0buffer' reserved memory (0x8ff00000)
to avoid memory conflict. This commit also bumps the XTLB tables
to avoid mapping failure.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Change-Id: I1a7af958af47e3fc9955d0a80d1649971e843eab
Enable switch between DDRC Auto low power and software/hardware
control modes DDRC Auto low-power mode is used when system is
active, software/hardware control mode is used when going into
suspend. Enable switching between Auto mode and SW/HW mode in
enter/exit retention routines.
Set LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 Max setting to allow
LPDDR_EN_CLKGATE reload LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 to
exit retention mode
Signed-off-by: Pascal Mareau <pascal.mareau@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Hongting Ting <hongting.dong@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3c4b6f7bc6ca02649ff27cd3d9a0c50dab3a3ad0
When resume from APD sleep mode, need to add a small delay
before accessing the CMC1 register.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ic8acdf58a3bf82b1791e7ae7f173f8c94c56b49d
for some user case, the ddr may need to be controlled
by RTD side to save power, when APD resume from low
power mode, it should wait ddr is ready for access.
currently we use a GPR in SIM_RTD_SEC as a flag to
indicate when the DDR is for access, non-zero value
means the DDR can be access from APD.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I6fb0cc17a040d803a597304620202423f646f294
When doing CSI stress test after cpu hotplug, sometimes, system
will hang in CSI test. After some debug, we find that if slow
down the APD NIC frequency before power on the offline CPU,
the issue is gone. For now, just add such SW workaround.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I39a49efc382fbebf46e1ff15c93d506bd5f6bec1
When system level DVFS is enabled, voltage can be changed to
optimize the power consumption.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Idfa0e637402078f3daf6e7c4ea1abb9af7675494
Enable the DDR frequency scaling support on i.MX8ULP.
Normally, the freq_index define is as below:
0: boot frequency;
1: low frequency(PLL bypassed);
2. high frequency(PLL ON).
Currently, DDR DFS only do frequency switching between
Low freq and high freq.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I3acd8bdf75e2dd6dff645b9f597dcfc0a756c428
After resume from APD power down, XRDC is initialized by S400 but
the PAC2 and MSC0-2 are not configured, so only DBD owner can access
the resources.
We have to move GPIO restore after TFA XRDC reinit and configure
PDAC for PCC5 before enabling eDMA2 MP clock
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I82748de080151b0bdf1cace092b7892a1e402a27
In order to isolate application memories, ELE FW introduces
a new policy which mimics the requestor attributes (DID, TZ).
So ELE configures SCM to access to external memory with CA35 DID
when CA35 request something from ELE.
Because ELE accesses DDR through NIC_LPAV, the XRDC MRC6 must be
configured for CA35 DID 7 to authorize the access.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I9e91a1b2798e8d15127d1bfa9aa0ffc612fd8981
set the memory region policy for secure heap(0xA9600000 ~ 0xAF600000),
it can only be RWX by secure master. At the same time, restrict G2D
and DCnano(domain 3) to write non-secure memory when they are set as
secure master.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If53e130eaeb1ac867ee56e4af04e3be29dec9857
Using XRDC MRC4/5/6 to restrict the secure access for TEE DDR
memory to protect TEE.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic161df6a98ded23b9a74d552717fc5dcc1ee2ae8
Support trusty on imx8ulp.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I7ada2557023e271a721d50bfe7fd20b5f01cb128
Add opteed support for imx8ulp.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Iddf6f164b7146332e99de42fcbbf9c892eb1d994
Enable the AFBB by default for active mode when APD side wakeup
from low power mode to align with the first time boot up.
Update the power mode configs to force shutdown all the
necessary power switches to optimize the power consumption.
To reduce the pad power consumption, put all the pad into
OFF mode to save more power. the PTD's compensation should
also be disabled in low power mode to save more power.
when APD enters PD mode, the LDO1(used by DDR) can be shutdown
to save power. when APD enters DPD mode, the BUCK3(supply for
APD/LPAV) can be shutdown to save power.
In single boot mode, When APD enters DPD mode, buck3 will
shutdown, LDO1 should be off to save more power as the DDR
controller has lost power.
In dualboot mode, the LPAV is owned by RTD side. When APD enters
low power mode, APD side should not config those PMIC regulators
that used by the resource owned by RTD side.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ie5e9b428f85345b81744313a8fb93bfc27e0dd71
Clear HRM bit in MU0_B CCR0 register to allow RTD to reset APD.
The action needs at both ATF init and APD resume.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2475e34b13f57818580a478ab567bfb9fc6cf174
Upower will check the LPAV ownership when power off the SRAM or PS.
if the LPAV owner is not APD, then the power off will return failure.
Add similar checking in SCMI PD driver to skip the power off to avoid
failure print causing suspend/resume not work.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I9dc657c2277129ac90a792232f734c08fca5f997
On i.MX8ULP, we need to use the APD deep power down(DPD) mode
to support the system power off function. when APD enter
power off mode, only the RTD can re-kick it and boot from ROM.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ifb42db0a7cf87b932160c59b47eca4d0f08f8cdf
The APD can be put into PD mode when linux suspend(mem). This patch
add the support for it. As the whole AP domain's context will be lost,
so we must save the necessary HW module states before entering PD mode,
and we need to restore those contexts when system wake up. Fot details
about which HW module's state will be lost, please refer to the RM.
When APD enter PD mode, only the wakeup event connected to the WUU
can wakeup APD successfully. The upower wakeup source is used to
wakeup APD by RTD due to the factor that the MU between A core & M
core is not connected into WUU to generate wakeup event.
as the SRAM0 will be power down when APD enters PD mode, so we
need to re-init the scmi channels(resides in the SRAM0). otherwise
the SCMI can NOT work anymore.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I44b0cdc8397e5d6a82081ea6746542e9fa4b9fc1
Add basic support for the cpuidle(cluster retention) and system
suspend support using the HW sleep mode.
When system enter low power mode after doing reboot twice, APD
will be failed to exit from low power mode successfully. it is
because that after secondary reboot, upower will modify the default
power switch config, then DDR will be off wrongly. So config the
low power mode info explicitly before APD entering any low power
mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ib68bfdfd4b925541e343aef4a5296a542451f86b
The L2 cache size config will be reset to default 256KB,
So we need to switch to 512KB after resume to make sure
the L2 cache size is same as before suspend.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ifd9b3e01829fbd7b1ae4ba00611359330f1a4f83
Add the initial xRDC support on i.MX8ULP.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I93ea8e2cebb049e6f20e71cfe50c7583a3228f38
JR1, JR2 and JR3 are available for use by the non secure
world. Setup the A35 core DID for these job rings.
Signed-off-by: Varun Sethi <v.sethi@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If64d4ce11ebff49a2405d8b561b344fcd7b2614f
Add the basic support for i.MX8ULP.
The i.MX 8ULP family of processors features NXP’s advanced
implementation of the dual Arm Cortex-A35 cores alongside
an Arm Cortex-M33. This combined architecture enables the
device to run a rich operating system (such as Linux) on
the Cortex-A35 core and an RTOS (such as FreeRTOS) on the
Cortex-M33 core. It also includes a Cadence Tensilica Fusion
DSP for low-power audio and a HiFi4 DSP for advanced audio
and machine learning applications.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I12df622b95960bcdf7da52e4c66470a700690e36
