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feat(imx8ulp): adjust the dram mapped region

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below commit mapped 16 MB memory from the start of DRAM(0x80000000),
which may have conflict with the shared memory used by Trusty OS:
  LF-8819: plat: imx8ulp: ddrc switch auto low power and software interface

change the mapped memory to 'vdev0buffer' reserved memory (0x8ff00000)
to avoid memory conflict. This commit also bumps the XTLB tables
to avoid mapping failure.

Signed-off-by: Ji Luo <ji.luo@nxp.com>
Change-Id: I1a7af958af47e3fc9955d0a80d1649971e843eab
This commit is contained in:
Ji Luo 2023-07-27 18:00:24 +09:00 • committed by Jacky Bai
parent ee25e6a51b
commit 8d50c91b47
2 changed files with 8 additions and 4 deletions
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3
plat/imx/imx8ulp/dram.c
View file

@ -25,7 +25,6 @@
#define IMX_DDRC_BASE U(0x2E060000)
#define SAVED_DRAM_DATA_BASE U(0x20055000)
#define IMX_DRAM_BASE U(0x80000000)
#define DENALI_CTL_143 U(0x23C)
#define DENALI_CTL_144 U(0x240)
#define DENALI_CTL_146 U(0x248)
@ -233,7 +232,7 @@ void dram_lp_auto_disable(void)
/* 0.b Disable DDRC auto low-power mode interface */
mmio_clrbits_32(IMX_DDRC_BASE + DENALI_CTL_146, LP_AUTO_ENTRY_EN << 24);
/* 0.c Read any location to get DRAM out of Self-refresh */
mmio_read_32(IMX_DRAM_BASE);
mmio_read_32(DEVICE2_BASE);
/* 0.d Confirm DRAM is out of Self-refresh */
while ((mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_146) &
LP_STATE_CS_PD_CG) != LP_STATE_CS_IDLE) {

9
plat/imx/imx8ulp/include/platform_def.h
View file

@ -43,8 +43,13 @@
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
#ifdef SPD_trusty
#define MAX_XLAT_TABLES 11
#define MAX_MMAP_REGIONS 12
#else
#define MAX_XLAT_TABLES 8
#define MAX_MMAP_REGIONS 9
#endif
#define PLAT_GICD_BASE U(0x2d400000)
#define PLAT_GICR_BASE U(0x2d440000)
@ -52,8 +57,8 @@
#define DEVICE0_SIZE U(0x10000000)
#define DEVICE1_BASE U(0x30000000)
#define DEVICE1_SIZE U(0x10000000)
#define DEVICE2_BASE U(0x80000000)
#define DEVICE2_SIZE U(0x01000000)
#define DEVICE2_BASE U(0x8ff00000)
#define DEVICE2_SIZE U(0x00001000)
#define IMX_LPUART4_BASE U(0x29390000)
#define IMX_LPUART5_BASE U(0x293a0000)
#define IMX_LPUART_BASE IMX_LPUART5_BASE