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https://github.com/ARM-software/arm-trusted-firmware.git
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feat(imx8ulp): add the initial XRDC support
Add the initial xRDC support on i.MX8ULP. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I93ea8e2cebb049e6f20e71cfe50c7583a3228f38
This commit is contained in:
Jacky Bai
parent
7c5eedca4c
commit
ac5d69b628
8 changed files with 471 additions and 0 deletions
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@ -332,3 +332,16 @@ int imx_kernel_entry_handler(uint32_t smc_fid,
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return 0;
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}
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#if defined(PLAT_imx8ulp)
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int imx_hifi_xrdc(uint32_t smc_fid)
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{
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mmio_setbits_32(IMX_SIM2_BASE + 0x8, BIT_32(19) | BIT_32(17) | BIT_32(18));
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mmio_clrbits_32(IMX_SIM2_BASE + 0x8, BIT_32(16));
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extern int xrdc_apply_hifi_config(void);
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xrdc_apply_hifi_config();
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return 0;
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}
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#endif
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@ -37,6 +37,9 @@ static uintptr_t imx_sip_handler(unsigned int smc_fid,
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scmi_smt_fastcall_smc_entry(0);
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SMC_RET1(handle, 0);
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break;
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case IMX_SIP_HIFI_XRDC:
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SMC_RET1(handle, imx_hifi_xrdc(smc_fid));
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break;
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#endif
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#if defined(PLAT_imx8mq)
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case IMX_SIP_GET_SOC_INFO:
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@ -55,6 +55,8 @@ int imx_kernel_entry_handler(uint32_t smc_fid, u_register_t x1,
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#define IMX_SIP_SCMI 0xC20000FE
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#define IMX_SIP_HIFI_XRDC 0xC200000E
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#if defined(PLAT_imx8mq)
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int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3);
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@ -100,5 +102,6 @@ uint64_t imx_buildinfo_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3,
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u_register_t x4);
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int scmi_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3);
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int imx_hifi_xrdc(uint32_t smc_fid);
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#endif /* __IMX_SIP_SVC_H__ */
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@ -24,6 +24,7 @@
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#include <imx_plat_common.h>
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#include <plat_imx8.h>
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#include <upower_api.h>
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#include <xrdc.h>
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#define MAP_BL31_TOTAL \
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MAP_REGION_FLAT(BL31_BASE, BL31_LIMIT - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE)
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@ -113,6 +114,11 @@ void bl31_platform_setup(void)
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imx8ulp_init_scmi_server();
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upower_init();
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xrdc_apply_apd_config();
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xrdc_apply_lpav_config();
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xrdc_enable();
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imx8ulp_caam_init();
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}
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47
plat/imx/imx8ulp/include/xrdc.h
Normal file
47
plat/imx/imx8ulp/include/xrdc.h
Normal file
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@ -0,0 +1,47 @@
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/*
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* Copyright 2021-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IMX8ULP_XRDC_H
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#define IMX8ULP_XRDC_H
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#define DID_MAX 8
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#define PAC_SLOT_ALL 128
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#define MSC_SLOT_ALL 8
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enum xrdc_mda_sa {
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MDA_SA_S,
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MDA_SA_NS,
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MDA_SA_PT, /* pass through master's secure/nonsecure attribute */
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};
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struct xrdc_mda_config {
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uint16_t mda_id;
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uint16_t did;
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enum xrdc_mda_sa sa;
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};
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struct xrdc_pac_msc_config {
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uint16_t pac_msc_id;
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uint16_t slot_id;
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uint8_t dsel[DID_MAX];
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};
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struct xrdc_mrc_config {
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uint16_t mrc_id;
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uint16_t region_id;
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uint32_t region_start;
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uint32_t region_size;
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uint8_t dsel[DID_MAX];
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uint16_t accset[2];
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};
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/* APIs to apply and enable XRDC */
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int xrdc_apply_lpav_config(void);
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int xrdc_apply_hifi_config(void);
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int xrdc_apply_apd_config(void);
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void xrdc_enable(void);
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#endif
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@ -31,6 +31,7 @@ BL31_SOURCES += plat/imx/common/lpuart_console.S \
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lib/cpus/aarch64/cortex_a35.S \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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plat/imx/imx8ulp/xrdc/xrdc_core.c \
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plat/imx/imx8ulp/imx8ulp_caam.c \
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drivers/scmi-msg/base.c \
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drivers/scmi-msg/entry.c \
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74
plat/imx/imx8ulp/xrdc/xrdc_config.h
Normal file
74
plat/imx/imx8ulp/xrdc/xrdc_config.h
Normal file
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@ -0,0 +1,74 @@
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/*
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* Copyright 2020-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <xrdc.h>
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#define SP(X) ((X) << 9)
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#define SU(X) ((X) << 6)
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#define NP(X) ((X) << 3)
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#define NU(X) ((X) << 0)
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#define RWX 7
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#define RW 6
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#define R 4
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#define X 1
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struct xrdc_mda_config imx8ulp_mda[] = {
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{ 0, 7, MDA_SA_PT }, /* A core */
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{ 1, 1, MDA_SA_NS }, /* DMA1 */
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{ 2, 1, MDA_SA_NS }, /* USB */
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{ 3, 1, MDA_SA_NS }, /* PXP-> .M10 */
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{ 4, 1, MDA_SA_NS }, /* ENET */
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{ 5, 1, MDA_SA_PT }, /* CAAM */
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{ 6, 1, MDA_SA_NS }, /* USDHC0 */
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{ 7, 1, MDA_SA_NS }, /* USDHC1 */
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{ 8, 1, MDA_SA_NS }, /* USDHC2 */
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{ 9, 2, MDA_SA_NS }, /* HIFI4 */
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{ 10, 3, MDA_SA_NS }, /* GPU3D */
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{ 11, 3, MDA_SA_NS }, /* GPU2D */
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{ 12, 3, MDA_SA_NS }, /* EPDC */
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{ 13, 3, MDA_SA_NS }, /* DCNano */
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{ 14, 3, MDA_SA_NS }, /* ISI */
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{ 15, 3, MDA_SA_NS }, /* PXP->NIC_LPAV.M0 */
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{ 16, 3, MDA_SA_NS }, /* DMA2 */
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};
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struct xrdc_mrc_config imx8ulp_mrc[] = {
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{ 0, 0, 0x0, 0x30000, {0, 0, 0, 0, 0, 0, 0, 1}, {0xfff, 0} }, /* ROM1 */
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{ 1, 0, 0x60000000, 0x10000000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* Flexspi2 */
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{ 2, 0, 0x22020000, 0x40000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM2 */
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{ 3, 0, 0x22010000, 0x10000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM0 */
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{ 4, 0, 0x80000000, 0x80000000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* DRAM */
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{ 5, 0, 0x80000000, 0x80000000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* DRAM */
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{ 6, 0, 0x80000000, 0x80000000, {1, 1, 0, 1, 1, 0, 1, 0}, {0xfff, 0} }, /* DRAM for LPAV and RTD*/
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{ 7, 0, 0x80000000, 0x10000000, {0, 0, 1, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for HIFI4 */
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{ 7, 1, 0x90000000, 0x10000000, {0, 0, 1, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for HIFI4 */
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{ 8, 0, 0x21000000, 0x10000, {1, 1, 1, 1, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM1 */
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{ 9, 0, 0x1ffc0000, 0xc0000, {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0} }, /* SSRAM for HIFI4 */
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{ 10, 0, 0x1ffc0000, 0xc0000, {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0} }, /* SSRAM for LPAV */
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{ 11, 0, 0x21170000, 0x10000, {0, 0, 1, 0, 0, 0, 0, 2}, {0xfff, SP(RW) | SU(RW) | NP(RW)} }, /* HIFI4 TCM */
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{ 11, 1, 0x21180000, 0x10000, {0, 0, 1, 0, 0, 0, 0, 2}, {SP(RW) | SU(RW) | NP(RW) | NU(RW), SP(RW) | SU(RW) | NP(RW)} }, /* HIFI4 TCM */
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{ 12, 0, 0x2d400000, 0x100000, {0, 0, 0, 0, 0, 0, 0, 1}, {SP(RW) | SU(RW) | NP(RW) | NU(RW), 0} }, /* GIC500 */
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};
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struct xrdc_pac_msc_config imx8ulp_pdac[] = {
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{ 0, PAC_SLOT_ALL, {0, 7, 0, 0, 0, 0, 0, 7} }, /* PAC0 */
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{ 0, 36, {0, 0, 0, 0, 0, 0, 7, 7} }, /* PAC0 slot 36 for CMC1 */
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{ 0, 41, {0, 0, 0, 0, 0, 0, 7, 7} }, /* PAC0 slot 41 for SIM_AD */
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{ 1, PAC_SLOT_ALL, {0, 7, 0, 0, 0, 0, 0, 7} }, /* PAC1 */
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{ 1, 0, {0, 7, 0, 0, 0, 0, 7, 7} }, /* PAC1 slot 0 for PCC4 */
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{ 1, 6, {0, 7, 7, 0, 0, 0, 0, 7} }, /* PAC1 slot 6 for LPUART6 */
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{ 1, 9, {0, 7, 7, 7, 0, 0, 0, 7} }, /* SAI5 for HIFI4 and eDMA2 */
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{ 1, 12, {0, 7, 0, 0, 0, 0, 7, 7} }, /* PAC1 slot 12 for IOMUXC1 */
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{ 2, PAC_SLOT_ALL, {7, 7, 7, 7, 0, 0, 7, 7} }, /* PAC2 */
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};
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struct xrdc_pac_msc_config imx8ulp_msc[] = {
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{ 0, 0, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC0 GPIOE */
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{ 0, 1, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC0 GPIOF */
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{ 1, MSC_SLOT_ALL, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC1 GPIOD */
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{ 2, MSC_SLOT_ALL, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC2 GPU3D/2D/DCNANO/DDR registers */
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};
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324
plat/imx/imx8ulp/xrdc/xrdc_core.c
Normal file
324
plat/imx/imx8ulp/xrdc/xrdc_core.c
Normal file
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@ -0,0 +1,324 @@
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/*
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* Copyright 2020-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stdbool.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include "xrdc_config.h"
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#define XRDC_ADDR 0x292f0000
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#define MRC_OFFSET 0x2000
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#define MRC_STEP 0x200
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#define XRDC_MGR_PAC_ID U(0)
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#define XRDC_MGR_PAC_SLOT U(47)
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enum xrdc_comp_type {
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MDA_TYPE = (1 << 16),
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MRC_TYPE = (2 << 16),
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PAC_TYPE = (3 << 16),
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MSC_TYPE = (4 << 16),
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};
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enum xrdc_pd_type {
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XRDC_AD_PD,
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XRDC_HIFI_PD,
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XRDC_AV_PD,
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};
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#define XRDC_TYPE_MASK (0x7 << 16)
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#define XRDC_ID_MASK 0xFFFF
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#define XRDC_ID(id) ((id) & XRDC_ID_MASK)
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typedef bool (*xrdc_check_func)(enum xrdc_comp_type type, uint16_t id);
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/* Access below XRDC needs enable PS 8
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* and HIFI clocks and release HIFI firstly
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*/
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uint32_t hifi_xrdc_list[] = {
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(MDA_TYPE | XRDC_ID(9)),
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(MRC_TYPE | XRDC_ID(7)),
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(MRC_TYPE | XRDC_ID(9)),
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(MRC_TYPE | XRDC_ID(11)),
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};
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/* Access below XRDC needs enable PS 16 firstly */
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uint32_t av_periph_xrdc_list[] = {
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(MDA_TYPE | XRDC_ID(10)),
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(MDA_TYPE | XRDC_ID(11)),
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(MDA_TYPE | XRDC_ID(12)),
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(MDA_TYPE | XRDC_ID(13)),
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(MDA_TYPE | XRDC_ID(14)),
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(MDA_TYPE | XRDC_ID(15)),
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(MDA_TYPE | XRDC_ID(16)),
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(PAC_TYPE | XRDC_ID(2)),
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(MRC_TYPE | XRDC_ID(6)),
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(MRC_TYPE | XRDC_ID(8)),
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(MRC_TYPE | XRDC_ID(10)),
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(MSC_TYPE | XRDC_ID(1)),
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(MSC_TYPE | XRDC_ID(2)),
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};
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uint32_t imx8ulp_pac_slots[] = {
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61, 23, 53
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};
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uint32_t imx8ulp_msc_slots[] = {
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2, 1, 7
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};
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static int xrdc_config_mrc_w0_w1(uint32_t mrc_con, uint32_t region, uint32_t w0, uint32_t size)
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{
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uint32_t w0_addr, w1_addr;
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w0_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20;
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w1_addr = w0_addr + 4;
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if ((size % 32) != 0) {
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return -EINVAL;
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}
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mmio_write_32(w0_addr, w0 & ~0x1f);
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mmio_write_32(w1_addr, w0 + size - 1);
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return 0;
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}
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static int xrdc_config_mrc_w2(uint32_t mrc_con, uint32_t region, uint32_t dxsel_all)
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{
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uint32_t w2_addr;
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w2_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0x8;
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mmio_write_32(w2_addr, dxsel_all);
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return 0;
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}
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static int xrdc_config_mrc_w3_w4(uint32_t mrc_con, uint32_t region, uint32_t w3, uint32_t w4)
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{
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uint32_t w3_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0xC;
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uint32_t w4_addr = w3_addr + 4;
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mmio_write_32(w3_addr, w3);
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mmio_write_32(w4_addr, w4);
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return 0;
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}
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static int xrdc_config_pac(uint32_t pac, uint32_t index, uint32_t dxacp)
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{
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uint32_t w0_addr;
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uint32_t val;
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if (pac > 2U) {
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return -EINVAL;
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}
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/* Skip the PAC slot for XRDC MGR, use Sentinel configuration */
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if (pac == XRDC_MGR_PAC_ID && index == XRDC_MGR_PAC_SLOT) {
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return 0;
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}
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w0_addr = XRDC_ADDR + 0x1000 + 0x400 * pac + 0x8 * index;
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mmio_write_32(w0_addr, dxacp);
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val = mmio_read_32(w0_addr + 4);
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mmio_write_32(w0_addr + 4, val | BIT_32(31));
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return 0;
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}
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static int xrdc_config_msc(uint32_t msc, uint32_t index, uint32_t dxacp)
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{
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uint32_t w0_addr;
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uint32_t val;
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if (msc > 2) {
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return -EINVAL;
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}
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w0_addr = XRDC_ADDR + 0x4000 + 0x400 * msc + 0x8 * index;
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mmio_write_32(w0_addr, dxacp);
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val = mmio_read_32(w0_addr + 4);
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mmio_write_32(w0_addr + 4, val | BIT_32(31));
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return 0;
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}
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static int xrdc_config_mda(uint32_t mda_con, uint32_t dom, enum xrdc_mda_sa sa)
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{
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uint32_t w0_addr;
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uint32_t val;
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w0_addr = XRDC_ADDR + 0x800 + mda_con * 0x20;
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val = mmio_read_32(w0_addr);
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if (val & BIT_32(29)) {
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mmio_write_32(w0_addr, (val & (~0xFF)) | dom |
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BIT_32(31) | 0x20 | ((sa & 0x3) << 6));
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} else {
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||||
mmio_write_32(w0_addr, dom | BIT_32(31));
|
||||
mmio_write_32(w0_addr + 0x4, dom | BIT_32(31));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool xrdc_check_pd(enum xrdc_comp_type type,
|
||||
uint16_t id, enum xrdc_pd_type pd)
|
||||
{
|
||||
unsigned int i, size;
|
||||
uint32_t item = type | XRDC_ID(id);
|
||||
uint32_t *list;
|
||||
|
||||
if (pd == XRDC_HIFI_PD) {
|
||||
size = ARRAY_SIZE(hifi_xrdc_list);
|
||||
list = hifi_xrdc_list;
|
||||
} else if (pd == XRDC_AV_PD) {
|
||||
size = ARRAY_SIZE(av_periph_xrdc_list);
|
||||
list = av_periph_xrdc_list;
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
|
||||
for (i = 0U; i < size; i++) {
|
||||
if (item == list[i]) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool xrdc_check_lpav(enum xrdc_comp_type type, uint16_t id)
|
||||
{
|
||||
return xrdc_check_pd(type, id, XRDC_AV_PD);
|
||||
}
|
||||
|
||||
static bool xrdc_check_hifi(enum xrdc_comp_type type, uint16_t id)
|
||||
{
|
||||
return xrdc_check_pd(type, id, XRDC_HIFI_PD);
|
||||
}
|
||||
|
||||
static bool xrdc_check_ad(enum xrdc_comp_type type, uint16_t id)
|
||||
{
|
||||
return (!xrdc_check_pd(type, id, XRDC_HIFI_PD) &&
|
||||
!xrdc_check_pd(type, id, XRDC_AV_PD));
|
||||
}
|
||||
|
||||
static int xrdc_apply_config(xrdc_check_func check_func)
|
||||
{
|
||||
unsigned int i, j;
|
||||
uint32_t val;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(imx8ulp_mda); i++) {
|
||||
if (check_func(MDA_TYPE, imx8ulp_mda[i].mda_id)) {
|
||||
xrdc_config_mda(imx8ulp_mda[i].mda_id,
|
||||
imx8ulp_mda[i].did, imx8ulp_mda[i].sa);
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(imx8ulp_mrc); i++) {
|
||||
if (check_func(MRC_TYPE, imx8ulp_mrc[i].mrc_id)) {
|
||||
xrdc_config_mrc_w0_w1(imx8ulp_mrc[i].mrc_id,
|
||||
imx8ulp_mrc[i].region_id,
|
||||
imx8ulp_mrc[i].region_start,
|
||||
imx8ulp_mrc[i].region_size);
|
||||
|
||||
val = 0;
|
||||
for (j = 0U; j < DID_MAX; j++) {
|
||||
val |= imx8ulp_mrc[i].dsel[j] << (3 * j);
|
||||
}
|
||||
|
||||
xrdc_config_mrc_w2(imx8ulp_mrc[i].mrc_id, imx8ulp_mrc[i].region_id, val);
|
||||
xrdc_config_mrc_w3_w4(imx8ulp_mrc[i].mrc_id, imx8ulp_mrc[i].region_id,
|
||||
0, imx8ulp_mrc[i].accset[0] | (imx8ulp_mrc[i].accset[1] << 16) | BIT_32(31));
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(imx8ulp_pdac); i++) {
|
||||
if (check_func(PAC_TYPE, imx8ulp_pdac[i].pac_msc_id)) {
|
||||
val = 0;
|
||||
for (j = 0U; j < DID_MAX; j++) {
|
||||
val |= imx8ulp_pdac[i].dsel[j] << (3 * j);
|
||||
}
|
||||
|
||||
if (imx8ulp_pdac[i].slot_id == PAC_SLOT_ALL) {
|
||||
/* Apply to all slots*/
|
||||
for (j = 0U; j < imx8ulp_pac_slots[imx8ulp_pdac[i].pac_msc_id]; j++) {
|
||||
xrdc_config_pac(imx8ulp_pdac[i].pac_msc_id, j, val);
|
||||
}
|
||||
} else {
|
||||
if (imx8ulp_pdac[i].slot_id >= imx8ulp_pac_slots[imx8ulp_pdac[i].pac_msc_id]) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
xrdc_config_pac(imx8ulp_pdac[i].pac_msc_id, imx8ulp_pdac[i].slot_id, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(imx8ulp_msc); i++) {
|
||||
if (check_func(MSC_TYPE, imx8ulp_msc[i].pac_msc_id)) {
|
||||
val = 0;
|
||||
for (j = 0U; j < DID_MAX; j++) {
|
||||
val |= imx8ulp_msc[i].dsel[j] << (3 * j);
|
||||
}
|
||||
|
||||
if (imx8ulp_msc[i].slot_id == MSC_SLOT_ALL) {
|
||||
/* Apply to all slots*/
|
||||
for (j = 0U; j < imx8ulp_msc_slots[imx8ulp_msc[i].pac_msc_id]; j++) {
|
||||
xrdc_config_msc(imx8ulp_msc[i].pac_msc_id, j, val);
|
||||
}
|
||||
} else {
|
||||
if (imx8ulp_msc[i].slot_id >= imx8ulp_msc_slots[imx8ulp_msc[i].pac_msc_id]) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
xrdc_config_msc(imx8ulp_msc[i].pac_msc_id, imx8ulp_msc[i].slot_id, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int xrdc_apply_lpav_config(void)
|
||||
{
|
||||
/* Enable the eDMA2 MP clock for MDA16 access */
|
||||
mmio_write_32(IMX_PCC5_BASE + 0x0, 0xc0000000);
|
||||
return xrdc_apply_config(xrdc_check_lpav);
|
||||
}
|
||||
|
||||
int xrdc_apply_hifi_config(void)
|
||||
{
|
||||
return xrdc_apply_config(xrdc_check_hifi);
|
||||
}
|
||||
|
||||
int xrdc_apply_apd_config(void)
|
||||
{
|
||||
return xrdc_apply_config(xrdc_check_ad);
|
||||
}
|
||||
|
||||
void xrdc_enable(void)
|
||||
{
|
||||
mmio_write_32(XRDC_ADDR, BIT(14) | BIT(15) | BIT(0));
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue