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Merge changes from topic "feature/imx8m-csu" into integration

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* changes:
  style(imx8m): add parenthesis to CSU_HP_REG
  feat(imx8mp): restrict peripheral access to secure world
  feat(imx8mp): set and lock almost all peripherals as non-secure
  feat(imx8mm): restrict peripheral access to secure world
  feat(imx8mm): set and lock almost all peripherals as non-secure
  feat(imx8m): add defines for csu_sa access security
  feat(imx8m): add imx csu_sa enum type defines for imx8m
  fix(imx8m): fix CSU_SA_REG to work with all sa registers
This commit is contained in:
Madhukar Pappireddy 2024-03-26 16:45:33 +01:00 • committed by TrustedFirmware Code Review
commit 5f4acf98dd
6 changed files with 137 additions and 5 deletions
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22
plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
View file

@ -77,11 +77,31 @@ static const struct imx_rdc_cfg rdc[] = {
static const struct imx_csu_cfg csu_cfg[] = {
/* peripherals csl setting */
CSU_CSLx(0x1, CSU_SEC_LEVEL_0, UNLOCKED),
CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_3, LOCKED),
CSU_CSLx(CSU_CSL_TZASC, CSU_SEC_LEVEL_5, LOCKED),
CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_5, LOCKED),
/* master HP0~1 */
/* SA setting */
CSU_SA(CSU_SA_M4, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_VPU, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_GPU, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_APBHDMA, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_ENET, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_LCDIF, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_CSI, NON_SEC_ACCESS, LOCKED),
/* HP control setting */

22
plat/imx/imx8m/imx8mm/include/imx_sec_def.h
View file

@ -213,4 +213,26 @@ enum csu_csl_idx {
CSU_CSL_CAAM = 114,
};
enum csu_sa_idx {
CSU_SA_M4 = 1,
CSU_SA_SDMA1 = 2,
CSU_SA_PCIE_CTRL1 = 3,
CSU_SA_USB1 = 4,
CSU_SA_USB2 = 5,
CSU_SA_VPU = 6,
CSU_SA_GPU = 7,
CSU_SA_APBHDMA = 8,
CSU_SA_ENET = 9,
CSU_SA_USDHC1 = 10,
CSU_SA_USDHC2 = 11,
CSU_SA_USDHC3 = 12,
CSU_SA_HUGO = 13,
CSU_SA_DAP = 14,
CSU_SA_SDMA2 = 15,
CSU_SA_CAAM = 16,
CSU_SA_SDMA3 = 17,
CSU_SA_LCDIF = 18,
CSU_SA_CSI = 19,
};
#endif /* IMX_SEC_DEF_H */

19
plat/imx/imx8m/imx8mn/include/imx_sec_def.h
View file

@ -207,4 +207,23 @@ enum csu_csl_idx {
CSU_CSL_OCRAM_S = 119,
};
enum csu_sa_idx {
CSU_SA_M7 = 1,
CSU_SA_SDMA1 = 2,
CSU_SA_USB1 = 4,
CSU_SA_GPU = 7,
CSU_SA_APBHDMA = 8,
CSU_SA_ENET1 = 9,
CSU_SA_USDHC1 = 10,
CSU_SA_USDHC2 = 11,
CSU_SA_USDHC3 = 12,
CSU_SA_HUGO = 13,
CSU_SA_DAP = 14,
CSU_SA_SDMA2 = 15,
CSU_SA_CAAM = 16,
CSU_SA_SDMA3 = 17,
CSU_SA_LCDIF = 18,
CSU_SA_ISI = 19,
};
#endif /* IMX_SEC_DEF_H */

37
plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
View file

@ -63,12 +63,45 @@ static const struct imx_rdc_cfg rdc[] = {
static const struct imx_csu_cfg csu_cfg[] = {
/* peripherals csl setting */
CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED),
CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED),
CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, LOCKED),
CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, LOCKED),
CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_3, LOCKED),
CSU_CSLx(CSU_CSL_TZASC, CSU_SEC_LEVEL_5, LOCKED),
CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_5, LOCKED),
/* master HP0~1 */
/* SA setting */
CSU_SA(CSU_SA_M7, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_APB_HDMA, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_ENET1, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_LCDIF1, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_ISI, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_NPU, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_LCDIF2, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_HDMI_TX, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_ENET2, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_GPU3D, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_GPU2D, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_VPU_G1, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_VPU_G2, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_VPU_VC8000E, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_AUDIO_EDMA, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_ISP1, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_ISP2, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_DEWARP, NON_SEC_ACCESS, LOCKED),
CSU_SA(CSU_SA_GIC500, NON_SEC_ACCESS, LOCKED),
/* HP control setting */

35
plat/imx/imx8m/imx8mp/include/imx_sec_def.h
View file

@ -269,6 +269,41 @@ enum csu_csl_idx {
CSU_CSL_OCRAM_A = 113,
CSU_CSL_OCRAM = 118,
CSU_CSL_OCRAM_S = 119,
CSU_CSL_VPU = 120,
};
enum csu_sa_idx {
CSU_SA_M7 = 1,
CSU_SA_SDMA1 = 2,
CSU_SA_PCIE_CTRL1 = 3,
CSU_SA_USB1 = 4,
CSU_SA_USB2 = 6,
CSU_SA_APB_HDMA = 8,
CSU_SA_ENET1 = 9,
CSU_SA_USDHC1 = 10,
CSU_SA_USDHC2 = 11,
CSU_SA_USDHC3 = 12,
CSU_SA_HUGO = 13,
CSU_SA_DAP = 14,
CSU_SA_SDMA2 = 15,
CSU_SA_CAAM = 16,
CSU_SA_SDMA3 = 17,
CSU_SA_LCDIF1 = 18,
CSU_SA_ISI = 19,
CSU_SA_NPU = 20,
CSU_SA_LCDIF2 = 21,
CSU_SA_HDMI_TX = 22,
CSU_SA_ENET2 = 23,
CSU_SA_GPU3D = 24,
CSU_SA_GPU2D = 25,
CSU_SA_VPU_G1 = 26,
CSU_SA_VPU_G2 = 27,
CSU_SA_VPU_VC8000E = 28,
CSU_SA_AUDIO_EDMA = 29,
CSU_SA_ISP1 = 30,
CSU_SA_ISP2 = 31,
CSU_SA_DEWARP = 32,
CSU_SA_GIC500 = 33,
};
#endif /* IMX_SEC_DEF_H */

7
plat/imx/imx8m/include/imx8m_csu.h
View file

@ -20,6 +20,9 @@
#define CSU_SEC_LEVEL_6 0x03
#define CSU_SEC_LEVEL_7 0x0
#define SEC_ACCESS 0x0
#define NON_SEC_ACCESS 0x1
#define LOCKED 0x1
#define UNLOCKED 0x0
@ -27,11 +30,11 @@
#define CSLx_LOCK(x) ((0x1 << (((x) % 2) * 16 + 8)))
#define CSLx_CFG(x, n) ((x) << (((n) % 2) * 16))
#define CSU_HP_REG(x) (IMX_CSU_BASE + ((x) / 16) * 4 + 0x200)
#define CSU_HP_REG(x) (IMX_CSU_BASE + (((x) / 16) * 4) + 0x200)
#define CSU_HP_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1)))
#define CSU_HP_CFG(x, n) ((x) << (((n) % 16) * 2))
#define CSU_SA_REG(x) (IMX_CSU_BASE + 0x218)
#define CSU_SA_REG(x) (IMX_CSU_BASE + (((x) / 16) * 4) + 0x218)
#define CSU_SA_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1)))
#define CSU_SA_CFG(x, n) ((x) << (((n) % 16) * 2))