mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 10:04:26 +00:00
0324081af0
This restricts and locks all security relevant peripherals to only be changeable by the secure world. Otherwise the normal world can simply change the access settings and defeat all security measures put in place. Change-Id: I248ef8dd67f1de7e528c3da456311bb138b77540 Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
294 lines
7.7 KiB
C
294 lines
7.7 KiB
C
/*
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* Copyright 2020-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <drivers/arm/tzc380.h>
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#include <drivers/console.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <dram.h>
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#include <gpc.h>
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#include <imx_aipstz.h>
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#include <imx_uart.h>
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#include <imx_rdc.h>
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#include <imx8m_caam.h>
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#include <imx8m_ccm.h>
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#include <imx8m_csu.h>
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#include <imx8m_snvs.h>
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#include <platform_def.h>
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#include <plat_imx8.h>
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#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
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static const mmap_region_t imx_mmap[] = {
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GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP,
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NOC_MAP, CAAM_RAM_MAP, NS_OCRAM_MAP,
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ROM_MAP, DRAM_MAP,
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{0},
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};
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static const struct aipstz_cfg aipstz[] = {
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{IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{0},
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};
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static const struct imx_rdc_cfg rdc[] = {
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/* Master domain assignment */
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RDC_MDAn(RDC_MDA_M7, DID1),
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/* peripherals domain permission */
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RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
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/* memory region */
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/* Sentinel */
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{0},
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};
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static const struct imx_csu_cfg csu_cfg[] = {
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/* peripherals csl setting */
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CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, LOCKED),
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CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, LOCKED),
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CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_3, LOCKED),
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CSU_CSLx(CSU_CSL_TZASC, CSU_SEC_LEVEL_5, LOCKED),
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CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_5, LOCKED),
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/* master HP0~1 */
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/* SA setting */
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CSU_SA(CSU_SA_M7, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_APB_HDMA, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_ENET1, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_LCDIF1, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_ISI, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_NPU, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_LCDIF2, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_HDMI_TX, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_ENET2, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_GPU3D, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_GPU2D, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_VPU_G1, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_VPU_G2, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_VPU_VC8000E, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_AUDIO_EDMA, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_ISP1, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_ISP2, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_DEWARP, NON_SEC_ACCESS, LOCKED),
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CSU_SA(CSU_SA_GIC500, NON_SEC_ACCESS, LOCKED),
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/* HP control setting */
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/* Sentinel */
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{0}
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};
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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/* get SPSR for BL33 entry */
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static uint32_t get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned long mode;
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uint32_t spsr;
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/* figure out what mode we enter the non-secure world */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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static void bl31_tzc380_setup(void)
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{
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unsigned int val;
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val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
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if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
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return;
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tzc380_init(IMX_TZASC_BASE);
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/*
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* Need to substact offset 0x40000000 from CPU address when
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* programming tzasc region for i.mx8mp.
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*/
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/* Enable 1G-5G S/NS RW */
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tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
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TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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unsigned int console_base = IMX_BOOT_UART_BASE;
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static console_t console;
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unsigned int val;
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unsigned int i;
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/* Enable CSU NS access permission */
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for (i = 0; i < 64; i++) {
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mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
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}
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imx_aipstz_init(aipstz);
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imx_rdc_init(rdc);
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imx_csu_init(csu_cfg);
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/* config the ocram memory range for secure access */
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mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4E1);
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val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
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mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
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if (console_base == 0U) {
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console_base = imx8m_uart_get_base();
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}
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console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ,
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IMX_CONSOLE_BAUDRATE, &console);
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/* This console is only used for boot stage */
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console_set_scope(&console, CONSOLE_FLAG_BOOT);
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imx8m_caam_init();
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/*
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* tell BL3-1 where the non-secure software image is located
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* and the entry state information.
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*/
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bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
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bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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#if defined(SPD_opteed) || defined(SPD_trusty)
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/* Populate entry point information for BL32 */
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SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
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SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
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bl32_image_ep_info.pc = BL32_BASE;
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bl32_image_ep_info.spsr = 0;
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/* Pass TEE base and size to bl33 */
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bl33_image_ep_info.args.arg1 = BL32_BASE;
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bl33_image_ep_info.args.arg2 = BL32_SIZE;
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#ifdef SPD_trusty
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bl32_image_ep_info.args.arg0 = BL32_SIZE;
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bl32_image_ep_info.args.arg1 = BL32_BASE;
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#else
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/* Make sure memory is clean */
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mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
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bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
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bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
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#endif
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#endif
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#if !defined(SPD_opteed) && !defined(SPD_trusty)
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enable_snvs_privileged_access();
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#endif
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bl31_tzc380_setup();
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}
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#define MAP_BL31_TOTAL \
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MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_BL31_RO \
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MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE)
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#define MAP_COHERENT_MEM \
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MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_BL32_TOTAL \
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MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW)
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void bl31_plat_arch_setup(void)
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{
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const mmap_region_t bl_regions[] = {
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MAP_BL31_TOTAL,
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MAP_BL31_RO,
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#if USE_COHERENT_MEM
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MAP_COHERENT_MEM,
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#endif
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#if defined(SPD_opteed) || defined(SPD_trusty)
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/* Map TEE memory */
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MAP_BL32_TOTAL,
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#endif
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{0}
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};
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setup_page_tables(bl_regions, imx_mmap);
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enable_mmu_el3(0);
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}
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void bl31_platform_setup(void)
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{
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generic_delay_timer_init();
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/* select the CKIL source to 32K OSC */
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mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
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/* Init the dram info */
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dram_info_init(SAVED_DRAM_TIMING_BASE);
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plat_gic_driver_init();
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plat_gic_init();
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imx_gpc_init();
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
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{
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if (type == NON_SECURE) {
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return &bl33_image_ep_info;
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}
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if (type == SECURE) {
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return &bl32_image_ep_info;
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}
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return NULL;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return COUNTER_FREQUENCY;
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}
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#ifdef SPD_trusty
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void plat_trusty_set_boot_args(aapcs64_params_t *args)
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{
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args->arg0 = BL32_SIZE;
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args->arg1 = BL32_BASE;
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args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
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}
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#endif
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