mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
feat(imx8ulp): enable the DDR frequency scaling support
Enable the DDR frequency scaling support on i.MX8ULP. Normally, the freq_index define is as below: 0: boot frequency; 1: low frequency(PLL bypassed); 2. high frequency(PLL ON). Currently, DDR DFS only do frequency switching between Low freq and high freq. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Change-Id: I3acd8bdf75e2dd6dff645b9f597dcfc0a756c428
This commit is contained in:
Jacky Bai
parent
68f132b88b
commit
caee2733ba
5 changed files with 256 additions and 0 deletions
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@ -40,6 +40,8 @@ static uintptr_t imx_sip_handler(unsigned int smc_fid,
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case IMX_SIP_HIFI_XRDC:
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SMC_RET1(handle, imx_hifi_xrdc(smc_fid));
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break;
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case IMX_SIP_DDR_DVFS:
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return dram_dvfs_handler(smc_fid, handle, x1, x2, x3);
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#endif
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#if defined(PLAT_imx8mq)
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case IMX_SIP_GET_SOC_INFO:
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@ -104,4 +104,9 @@ uint64_t imx_buildinfo_handler(uint32_t smc_fid, u_register_t x1,
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int scmi_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3);
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int imx_hifi_xrdc(uint32_t smc_fid);
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#if defined(PLAT_imx8ulp)
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int dram_dvfs_handler(uint32_t smc_fid, void *handle,
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u_register_t x1, u_register_t x2, u_register_t x3);
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#endif
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#endif /* __IMX_SIP_SVC_H__ */
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@ -7,9 +7,16 @@
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#include <assert.h>
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#include <stdbool.h>
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#include <arch_helpers.h>
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#include <bl31/interrupt_mgmt.h>
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#include <common/runtime_svc.h>
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#include <lib/mmio.h>
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#include <lib/spinlock.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <dram.h>
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#include <upower_api.h>
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#define PHY_FREQ_SEL_INDEX(x) ((x) << 16)
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@ -130,6 +137,12 @@ uint32_t freq_specific_reg_array[PHY_DIFF_NUM] = {
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871, 872, 882, 1063, 1319, 1566, 1624, 1625
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};
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/* lock used for DDR DVFS */
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spinlock_t dfs_lock;
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static volatile uint32_t core_count;
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static volatile bool in_progress;
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static int num_fsp;
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static void ddr_init(void)
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{
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unsigned int i;
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@ -425,3 +438,223 @@ void dram_exit_retention(void)
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}
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}
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}
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#define LPDDR_DONE (0x1<<4)
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#define SOC_FREQ_CHG_ACK (0x1<<6)
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#define SOC_FREQ_CHG_REQ (0x1<<7)
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#define LPI_WAKEUP_EN (0x4<<8)
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#define SOC_FREQ_REQ (0x1<<11)
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#define LPDDR_EN_CLKGATE (0x1<<17)
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static void set_cgc2_ddrclk(uint8_t src, uint8_t div)
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{
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/* Wait until the reg is unlocked for writing */
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while (mmio_read_32(IMX_CGC2_BASE + 0x40) & BIT(31))
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;
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mmio_write_32(IMX_CGC2_BASE + 0x40, (src << 28) | (div << 21));
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/* Wait for the clock switching done */
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while (!(mmio_read_32(IMX_CGC2_BASE + 0x40) & BIT(27)))
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;
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}
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static void set_ddr_clk(uint32_t ddr_freq)
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{
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/* Disable DDR clock */
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mmio_clrbits_32(IMX_PCC5_BASE + 0x108, BIT(30));
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switch (ddr_freq) {
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/* boot frequency ? */
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case 48:
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set_cgc2_ddrclk(2, 0);
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break;
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/* default bypass frequency for fsp 1 */
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case 192:
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set_cgc2_ddrclk(0, 1);
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break;
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case 384:
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set_cgc2_ddrclk(0, 0);
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break;
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case 264:
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set_cgc2_ddrclk(4, 3);
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break;
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case 528:
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set_cgc2_ddrclk(4, 1);
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break;
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default:
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break;
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}
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/* Enable DDR clock */
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mmio_setbits_32(IMX_PCC5_BASE + 0x108, BIT(30));
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/* Wait until the reg is unlocked for writing */
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while (mmio_read_32(IMX_CGC2_BASE + 0x40) & BIT(31)) {
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;
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}
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}
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#define AVD_SIM_LPDDR_CTRL (IMX_LPAV_SIM_BASE + 0x14)
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#define AVD_SIM_LPDDR_CTRL2 (IMX_LPAV_SIM_BASE + 0x18)
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#define MAX_FSP_NUM U(3)
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#define DDR_DFS_GET_FSP_COUNT 0x10
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#define DDR_BYPASS_DRATE U(400)
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/* Normally, we only switch frequency between 1(bypass) and 2(highest) */
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int lpddr4_dfs(uint32_t freq_index)
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{
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uint32_t lpddr_ctrl, lpddr_ctrl2;
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uint32_t ddr_ctl_144;
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/*
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* Valid index: 0 to 2
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* index 0: boot frequency
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* index 1: bypass frequency
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* index 2: highest frequency
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*/
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if (freq_index > 2U) {
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return -1;
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}
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/* Enable LPI_WAKEUP_EN */
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ddr_ctl_144 = mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_144);
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mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_144, LPI_WAKEUP_EN);
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/* put DRAM into long self-refresh & clock gating */
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lpddr_ctrl = mmio_read_32(AVD_SIM_LPDDR_CTRL);
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lpddr_ctrl = (lpddr_ctrl & ~((0x3f << 15) | (0x3 << 9))) | (0x28 << 15) | (freq_index << 9);
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mmio_write_32(AVD_SIM_LPDDR_CTRL, lpddr_ctrl);
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/* Gating the clock */
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lpddr_ctrl2 = mmio_read_32(AVD_SIM_LPDDR_CTRL2);
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mmio_setbits_32(AVD_SIM_LPDDR_CTRL2, LPDDR_EN_CLKGATE);
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/* Request frequency change */
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mmio_setbits_32(AVD_SIM_LPDDR_CTRL, SOC_FREQ_REQ);
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do {
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lpddr_ctrl = mmio_read_32(AVD_SIM_LPDDR_CTRL);
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if (lpddr_ctrl & SOC_FREQ_CHG_REQ) {
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/* Bypass mode */
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if (info->fsp_table[freq_index] < DDR_BYPASS_DRATE) {
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/* Change to PLL bypass mode */
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mmio_write_32(IMX_LPAV_SIM_BASE, 0x1);
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/* change the ddr clock source & frequency */
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set_ddr_clk(info->fsp_table[freq_index]);
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} else {
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/* Change to PLL unbypass mode */
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mmio_write_32(IMX_LPAV_SIM_BASE, 0x0);
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/* change the ddr clock source & frequency */
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set_ddr_clk(info->fsp_table[freq_index] >> 1);
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}
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mmio_clrsetbits_32(AVD_SIM_LPDDR_CTRL, SOC_FREQ_CHG_REQ, SOC_FREQ_CHG_ACK);
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continue;
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}
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} while ((lpddr_ctrl & LPDDR_DONE) != 0); /* several try? */
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/* restore the original setting */
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mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_144, ddr_ctl_144);
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mmio_write_32(AVD_SIM_LPDDR_CTRL2, lpddr_ctrl2);
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/* Check the DFS result */
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lpddr_ctrl = mmio_read_32(AVD_SIM_LPDDR_CTRL) & 0xF;
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if (lpddr_ctrl != 0U) {
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/* Must be something wrong, return failure */
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return -1;
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}
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/* DFS done successfully */
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return 0;
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}
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/* for the non-primary core, waiting for DFS done */
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static uint64_t waiting_dvfs(uint32_t id, uint32_t flags,
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void *handle, void *cookie)
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{
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uint32_t irq;
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irq = plat_ic_acknowledge_interrupt();
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if (irq < 1022U) {
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plat_ic_end_of_interrupt(irq);
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}
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/* set the WFE done status */
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spin_lock(&dfs_lock);
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core_count++;
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dsb();
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spin_unlock(&dfs_lock);
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while (in_progress) {
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wfe();
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}
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return 0;
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}
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int dram_dvfs_handler(uint32_t smc_fid, void *handle,
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u_register_t x1, u_register_t x2, u_register_t x3)
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{
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unsigned int fsp_index = x1;
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uint32_t online_cpus = x2 - 1;
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uint64_t mpidr = read_mpidr_el1();
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unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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/* Get the number of FSPs */
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if (x1 == DDR_DFS_GET_FSP_COUNT) {
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SMC_RET2(handle, num_fsp, info->fsp_table[1]);
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}
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/* start lpddr frequency scaling */
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in_progress = true;
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dsb();
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/* notify other core wait for scaling done */
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for (unsigned int i = 0; i < PLATFORM_CORE_COUNT; i++)
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/* Skip raise SGI for current CPU */
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if (i != cpu_id) {
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plat_ic_raise_el3_sgi(0x8, i);
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}
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/* Make sure all the cpu in WFE */
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while (online_cpus != core_count) {
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;
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}
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/* Flush the L1/L2 cache */
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dcsw_op_all(DCCSW);
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lpddr4_dfs(fsp_index);
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in_progress = false;
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core_count = 0;
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dsb();
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sev();
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isb();
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SMC_RET1(handle, 0);
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}
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void dram_init(void)
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{
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uint32_t flags = 0;
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uint32_t rc;
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unsigned int i;
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/* Register the EL3 handler for DDR DVFS */
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set_interrupt_rm_flag(flags, NON_SECURE);
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rc = register_interrupt_type_handler(INTR_TYPE_EL3, waiting_dvfs, flags);
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if (rc) {
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panic();
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}
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info = (struct dram_timing_info *)SAVED_DRAM_DATA_BASE;
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/* Get the num of the supported Fsp */
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for (i = 0; i < MAX_FSP_NUM; i++) {
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if (!info->fsp_table[i]) {
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break;
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}
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}
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num_fsp = (i > MAX_FSP_NUM) ? MAX_FSP_NUM : i;
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}
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@ -19,6 +19,7 @@
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <dram.h>
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#include <imx8_lpuart.h>
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#include <imx8ulp_caam.h>
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#include <imx_plat_common.h>
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@ -153,6 +154,8 @@ void bl31_platform_setup(void)
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xrdc_enable();
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imx8ulp_caam_init();
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dram_init();
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
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13
plat/imx/imx8ulp/include/dram.h
Normal file
13
plat/imx/imx8ulp/include/dram.h
Normal file
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@ -0,0 +1,13 @@
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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DRAM_H
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#define DRAM_H
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void dram_init(void);
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#endif /* DRAM_H */
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