Similarly to the memory node in the NS device tree, platform_def already
defines all the necessary values to populate the spmc manifest and NS
related entries automatically. Use the macros directly so any changes
can propagate automatically.
The result of this is that TC3 and above get correct secure world
manifests automatically. They were previously broken.
One "breaking" change is that the FWU region moves. This should have
happened previously but it was missed when the secure portion of DRAM
was increased, leaving it in secure memory. This was caught when going
over the definitions and correlating them should prevent this in the
future.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1415e402be8c70f5e22f28eabddcb53298c57a11
With new TC revisions, memory banks move around which requires an update
in platform_def. It also requires an update in the device tree which
doesn't come naturally. To avoid this, add the memory node such that it
uses the macros defined in platform_def.
By doing this we can put u-boot out of its misery in trying to come up
with the correct memory node and tf-a's device tree becomes complete.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ia92cc6931abb12be2856ac3fb1455e4f3005b326
For u-boot to use the device tree itself it needs to know about the
arm_ffa module. This is not relevant to linux but it doesn't hurt as it
won't use it.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I6e75659e4950c62ce7377dc7941225eb5d7a3d8d
If the kernel is post 5.19 and is configured with
CONFIG_RANDOM_TRUST_BOOTLOADER=y then entropy can be passed to
Linux via the device tree. This avoids delaying the Linux boot
waiting for entropy. This is particularly noticeable when
booting android but also speeds up the generation of the ssl
certificates.
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Change-Id: I4c6136c54f0e971802a2a9de9f88cd32b610dce9
Currently there are two configurations for DPU
Config 1: Address - 0x2CC0_0000 IRQ - 101
Config 2: Address - 0x40_0000_0000 IRQ - 547
Config 1 is used by all FPGA and TC0, TC1 and TC2 FVPs
Config 2 is used by TC3 FVP currently
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: If0097441b6ab90f58911df032e45f6bf06fc7909
Compile-time controls have been added for the following:
* SCMI power domain use for DPU and GPU.
* SMMU-700: planned rework required to use IOMMU correctly
for DPU and GPU.
These will allow easier experimentation in the future without
ad-hoc changes needed in the dts file for any sort of analysis
that requires testing different paths.
For TC3 however, the DPU is in an always on power domain so SCMI power
domains are not supported.
Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Change-Id: If6179a3e4784c1b69f0338a8d52b552452c0eac1
In trying to use the same DTS for the FVP and FPGA subvariants we need
to keep track of what is different. Move the FVP RoS, which is different
to the FPGA's, to reduce the number of ifdefs and make FVP-only changes
easier.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ib7999d3e39de55ab4a30e68dd81f95120be15a8c
Even though the FVP and FPGA are meant to be identical their RoS's (rest
of system) are different. Factor these in so the device tree works for
both. The differences are:
* addresses of GIC and UART
* displays (FPGA uses 4k)
* ethernet devices and SD card (it's non removable on the FPGA)
Their frequencies are also different. The FVP simulates certain
frequencies but isn't very sensitive when we disregard them. To keep
code similar, update them with the FPGA values. This keeps working on
FVP even if slightly incorrect.
Also add an option for the DPU to either use fixed clocks or SCMI set
clocks, hidden behind a flag. This is useful during bringup and because
SCMI may not necessarily work on FPGA.
Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Co-developed-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Co-developed-by: Usama Arif <usama.arif@arm.com>
Co-developed-by: Angel Rodriguez Garcia <angel.rodriguezgarcia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic7a4bfc302673a3a6571757e23a9e6184fba2a13
TC is getting an FPGA port alongside the FVP. It is meant to be
identical, but the core configurations on TC2 differ (there are 14 in an
odd arrangement).
Introduce these differences and gate them behind a new TARGET_FLAVOUR
flag which defaults to FVP for compatibility.
While updating CPUs, it's a good time to do TC3 too. It has different
cores in a different configuration again, so it needs different capacity
values. Those have been derived using GeekBench 6.0 ST on the FPGA.
Finally GPU and DPU power domains are 1 above the CPUs so make that
relative.
In the end, the big/mid/little configurations are:
* TC2 FVP: 1/3/4
* TC2 FPGA: 2/3/5/4 (the 3 is a big "min" core)
* TC3 both: 2/4/2 (with new capacities)
Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3c3a10d6727f5010fd9026a404df27e9262dff6b
TC3 is a little different from TC2:
* new address for its second DRAM bank
* new CPUs
* a few interrupts have changed
* new SCP MHU base address.
* utility space address (needed for MPAM) is different
* no CMN (and therefore cmn-pmu)
* the uart clock is different
This requires the dts to be different between revisions for the first
time. Introduce a tc_vers.dtsi that includes only definitions for things
that are different.
Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2940d87a69ea93502b7f5a22a539e4b70a63e827
We have lots of errors in our device tree when running dt-validate.
Remove the majority so that dt-validate-ing is useful now.
Do this by renaming nodes to conform to spec, making addresses lowercase
with no 0x at the front, and removing nodes that shouldn't be there.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1840f0f5de34a56ee240c07eff08d73c856b338e
TC has PMUs with interrupts in all cores and Linux needs to be told
about them.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ice0e6dab396b90c05f4b9668623ba7b3556a53ac
The hdlcd device tree node is not in use for any TC incarnation. The DPU
replaces it. So drop it.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I5393435e36d8307bef909a6519cb40305b77f0cf
Firmware update is a trusted service secure partition that implements
the PSA firmware update specification. It executes in the secure world
in total compute platform. To make it fit with Op-tee we need to reduce
its available memory.
Also, reserve 4 MB for stmm communication used for firmware update.
The firmware update secure partition and u-boot communicates using the
stmm communication layer and it needs a dedicated memory region.
Co-developed-by: Sergio Alves <sergio.dasilvalves@arm.com>
Co-developed-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Tudor Cretu <tudor.cretu@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I0427549845f6c7650b8ef4e450d387fe9702a847
The gic and trbe0 are listed as active high, but the spec says they are
triggered on active low. Correct according to the spec.
While we're at it, convert all interrupts to use the macros so hopefully
no such confusion happens again.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2fc01cf0a34b031b95219b9656b613a19a2e9b2a
The scmi-perf-domain property is a custom property while we
wait for proper support in the kernel for using the scmi_pm_domain
driver and scmi_perf_domain driver at the same time.
GPU operating points are now in the SCP firmware.
Change-Id: Ib6d8f52c8bf69194b1d2da4e065a34c4a341c221
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Remap TF-A console logs from SoC UART2 (S1 terminal) to CSS
secure (UART1_AP terminal) and Linux logs from SoC UART2
(S1 terminal) to CSS non-secure (UART_AP terminal) to align
with the latest FVP TC2 model (version 11.23/17).
Change-Id: I7206e64b65346bfdcc48d6acd3792b436041e45f
Signed-off-by: Annam Sai Manisha <annam.saimanisha@arm.com>
* changes:
feat(stm32mp2-fdts): add board ID OTP in STM32MP257F-EV1
feat(stm32mp2-fdts): add OTP nodes in STM32MP251 SoC DT file
fix(stm32mp2): add missing include
feat(st): do not directly call BSEC functions in common code
feat(st): use stm32_get_otp_value_from_idx() in BL31
refactor(st): update test for closed chip
refactor(st-bsec): improve BSEC driver
refactor(st): use dashes for BSEC node names
Add CCA CoT DTB and rename generic CoT DTB to TBBR CoT DTB
This allows CCA platforms to get their chain of trust description
from a configuration file, rather than hard-coding it into the
firmware itself.
Change-Id: I114788a5d21b9a8d625239cfb71b442d204e3654
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Ad the board ID OTP node for the STM32MP257F-EV1 board.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I394b27f50a8f45c919a1e907e03572b25d958ae4
Add the BSEC node in STM32MP25 device tree file, with the OTP fuses
that will be used by TF-A.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I1ffdbd17829f4adf7b113ae0bec7547a6d1b4bac
This is something commonly asked by Linux kernel DT maintainers [1].
The mentioned doc is not upstreamed, but may be checked with dtbs_check.
While at it align some nodes with Linux or OP-TEE.
[1] https://lore.kernel.org/linux-arm-kernel/20231125184422.12315-1-krzysztof.kozlowski@linaro.org/
Change-Id: I63e983c2a00eda3cd8b81c66c0cd1a97cf8249b7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Add virtio-net and virtio-9p devices to the devicetree without the
status set. This ensures that the MMIO frame is set, and it is not
fatal to start the driver initialisation procedure, which will
typically bail out if it finds zero virtqueues.
Add the virtio-rng device with status disabled. The disabled status
is chosen because the FVP models have only supported this since 2022
and older models would trigger an external abort when trying to access
or probe this MMIO region.
This is included by the fvp-base devicetrees.
Change-Id: Ia0a853533bb5d619a3d415e35b3217ad3a978ada
Signed-off-by: Diego Sueiro <Diego.Sueiro@arm.com>
Signed-off-by: Debbie Martin <Debbie.Martin@arm.com>
Add stdout-path to the fvp-base devicetree to be passed to BL33 (U-Boot)
and then to the Linux kernel to be compliant to Arm SystemReady IR:
https://developer.arm.com/documentation/DUI1101/2-0/
Configure-U-Boot-for-SystemReady/Adapt-the-Devicetree
This has been tested by booting fvp-base to Linux and ensuring the
console is accessible.
Change-Id: Iae98630f18f735ce344c1158f41f358c2a49eeb6
Signed-off-by: Diego Sueiro <Diego.Sueiro@arm.com>
Signed-off-by: Debbie Martin <Debbie.Martin@arm.com>
This is an alignment with Linux DT files that have been merged in
stm32 tree [1], and will be in Linux 6.7.
The /omit-if-no-ref/ in overlay files are now removed, as already in
pinctrl files.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iab94b0ba7a4a0288ca53d1ae57ab590566967415
Three packages exist for stm32mp25 dies. As ball-out is different
between them, this patch covers those differences by introducing
dedicated pinctrl dtsi files. Each dtsi pinctrl package file
describes the package ball-out through gpio-ranges.
Available packages are:
STM32MP25xAI: 18*18/FCBGA 172 ios
STM32MP25xAK: 14*14/FCBGA 144 ios
STM32MP25xAL: 10*10/TFBGA 144 ios
It includes also the common file used for pin groups definition.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8500ccccb7a96748f36ffc80edc91da8595f4da8
STM32MP25 family is composed of 4 SoCs defined as following:
-STM32MP251: common part composed of 1*Cortex-A35, common peripherals
like SDMMC, UART, SPI, I2C, PCIe, USB3, parallel and DSI display,
1*ETH ...
-STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH,
CAN-FD and LVDS display.
-STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
-STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).
A second diversity layer exists for security features/ A35 frequency:
-STM32MP25xY, "Y" gives information:
-Y = A means A35@1.2GHz + no cryp IP and no secure boot.
-Y = C means A35@1.2GHz + cryp IP and secure boot.
-Y = D means A35@1.5GHz + no cryp IP and no secure boot.
-Y = F means A35@1.5GHz + cryp IP and secure boot.
Change-Id: Icd1351e20b862675d257dede55df190a90acbd59
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The build flags to enable the Arm(R) Ethos(TM)-N NPU driver are in arm
platform specific make files i.e. plat/arm/common/arm_common.mk. These
flags are renamed and moved to ethosn_npu.mk. Other source and make
files are changed to reflect the changes in these flags.
Signed-off-by: Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com>
Change-Id: I6fd20225343c574cb5ac1f0f32ff2fc28ef37ea6
Add support for Morello I2S audio subsystem. This includes adding the
audio formatter and I2S transmitter nodes and gluing them together with
the hdmi codec using a simple sound card machine node.
Change-Id: I3de4b06ef965c8e0555d074118b944fe6b4b78bb
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Faiz Abbas <faiz.abbas@arm.com>
Device tree alignment with kernel and latest binding for BSEC node:
the rev2.0 is used on STM32MP13x devices with the new compatible
compatible = "st,stm32mp13-bsec".
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I62c4090ae5d5c1de901e6df1e8ea5d1a3296a272
To keep (as much as possible) alignment with Linux DT, move the
/omit-if-no-ref/ keywords to DT overlay files (fdts/stm32mp1*-bl*.dtsi).
This also ease checks for ST tools.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ib467a6b65f05a84c9678799ad32e1820249b4ed1
Use /omit-if-no-ref/ keyword in DT to remove extra device nodes only
when they are not used / not referenced.
If the board device tree only defines subnodes, dtc does not consider it
as usage, you have to specifically mention device's phandle, e.g.:
\ {
i2c6-phandle = <&i2c6>;
};
or in aliases section
aliases {
i2c6 = &i2c6;
};
Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com>
Change-Id: I431ecd93576f97fd021d82d23b93c659fc8f26b8
Adds additional asset allocators to the device tree include
file as the non-secure world kernel module for the Arm(R)
Ethos(TM)-N NPU now fully supports having and using multiple
asset allocators.
Signed-off-by: Joshua Pimm <joshua.pimm@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I82d53667ef64968ee814f611d0a90abd3b3cf3de
With the /omit-if-no-ref/ keyword in DT, the non-referenced nodes
are just removed. This allows reducing the size of device tree blobs.
Setting it before pins node allows a size reduction of more than 2kB.
The corresponding nodes can also be removed from BL2 and BL32 DT
overlays.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6b4a4d227d5592e1d253a1b35da2dafaac2ddcae
FVP PMUv3 SPIs legacy interrupts are only listed for
cluster #0 and are missing for cluster #1.
This patch changes FVP SPIs to PMUv3 PPI as in
arm_fpga.dtsi, morello.dtsi and n1sdp.dtsi.
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: Ic624cec09ba932666c746ae1a6a4b78b6decde96
Add one device tree to support a family of boards (PRTT1C, PRTT1S,
PRTT1A) based on STM32MP151AAD3, used as sensors and actuators for
industrial, 10BaseT1L based networks.
This change was tested with barebox 2022.12.0 bootloader and kernel
v6.2.0-rc1.
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Change-Id: Ibab9933eadd7aa379ae0a7c7ccbfc2fbb9a44ca8
The L3 cache in the DSU supports the Memory System Resources
Partitioning and Monitoring (MPAM). The MPAM specific registers in the
DSU are accessed through utility bus of DSU that are memory mapped from
0x1_0000_1000.
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I2798181d599228e96dd4c0043a2ccd94668c7e20
