mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-07 21:33:54 +00:00
feat(stm32mp15-fdts): add support for prtt1x board family
Add one device tree to support a family of boards (PRTT1C, PRTT1S, PRTT1A) based on STM32MP151AAD3, used as sensors and actuators for industrial, 10BaseT1L based networks. This change was tested with barebox 2022.12.0 bootloader and kernel v6.2.0-rc1. Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Change-Id: Ibab9933eadd7aa379ae0a7c7ccbfc2fbb9a44ca8
This commit is contained in:
David Jander
Oleksij Rempel
parent
5673160717
commit
3812ceba8f
3 changed files with 361 additions and 0 deletions
119
fdts/stm32mp15-ddr3-1x2Gb-1066-binG.dtsi
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119
fdts/stm32mp15-ddr3-1x2Gb-1066-binG.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
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*/
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/*
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* File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
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* DDR type: DDR3 / DDR3L
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* DDR width: 16bits
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* DDR density: 4Gb
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* System frequency: 533000Khz
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* Relaxed Timing Mode: false
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* Address mapping type: RBC
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*
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* Save Date: 2020.02.20, save Time: 18:45:20
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*/
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#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x10000000
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#define DDR_MSTR 0x00041401
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#define DDR_MRCTRL0 0x00000010
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#define DDR_MRCTRL1 0x00000000
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#define DDR_DERATEEN 0x00000000
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#define DDR_DERATEINT 0x00800000
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#define DDR_PWRCTL 0x00000000
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#define DDR_PWRTMG 0x00400010
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#define DDR_HWLPCTL 0x00000000
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#define DDR_RFSHCTL0 0x00210000
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#define DDR_RFSHCTL3 0x00000000
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#define DDR_RFSHTMG 0x0040008B
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#define DDR_CRCPARCTL0 0x00000000
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#define DDR_DRAMTMG0 0x121B1214
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#define DDR_DRAMTMG1 0x000A041C
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#define DDR_DRAMTMG2 0x0608090F
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#define DDR_DRAMTMG3 0x0050400C
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#define DDR_DRAMTMG4 0x08040608
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#define DDR_DRAMTMG5 0x06060403
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#define DDR_DRAMTMG6 0x02020002
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#define DDR_DRAMTMG7 0x00000202
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#define DDR_DRAMTMG8 0x00001005
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#define DDR_DRAMTMG14 0x000000A0
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#define DDR_ZQCTL0 0xC2000040
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#define DDR_DFITMG0 0x02060105
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#define DDR_DFITMG1 0x00000202
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#define DDR_DFILPCFG0 0x07000000
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#define DDR_DFIUPD0 0xC0400003
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#define DDR_DFIUPD1 0x00000000
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#define DDR_DFIUPD2 0x00000000
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#define DDR_DFIPHYMSTR 0x00000000
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#define DDR_ODTCFG 0x06000600
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00000C01
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#define DDR_SCHED1 0x00000000
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#define DDR_PERFHPR1 0x01000001
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#define DDR_PERFLPR1 0x08000200
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#define DDR_PERFWR1 0x08000400
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#define DDR_DBG0 0x00000000
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#define DDR_DBG1 0x00000000
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#define DDR_DBGCMD 0x00000000
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#define DDR_POISONCFG 0x00000000
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#define DDR_PCCFG 0x00000010
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#define DDR_PCFGR_0 0x00010000
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#define DDR_PCFGW_0 0x00000000
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#define DDR_PCFGQOS0_0 0x02100C03
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#define DDR_PCFGQOS1_0 0x00800100
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#define DDR_PCFGWQOS0_0 0x01100C03
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#define DDR_PCFGWQOS1_0 0x01000200
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#define DDR_PCFGR_1 0x00010000
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#define DDR_PCFGW_1 0x00000000
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#define DDR_PCFGQOS0_1 0x02100C03
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#define DDR_PCFGQOS1_1 0x00800040
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#define DDR_PCFGWQOS0_1 0x01100C03
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#define DDR_PCFGWQOS1_1 0x01000200
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#define DDR_ADDRMAP1 0x00151515
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x1F000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x03030303
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#define DDR_ADDRMAP6 0x0F0F0303
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_PGCR 0x01442E02
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#define DDR_PTR0 0x0022AA5B
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#define DDR_PTR1 0x04841104
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#define DDR_PTR2 0x042DA068
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#define DDR_ACIOCR 0x10400812
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#define DDR_DXCCR 0x00000C40
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#define DDR_DSGCR 0xF200011F
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#define DDR_DCR 0x0000000B
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#define DDR_DTPR0 0x38D488D0
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#define DDR_DTPR1 0x098B00D8
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#define DDR_DTPR2 0x10023600
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#define DDR_MR0 0x00000840
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#define DDR_MR1 0x00000000
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#define DDR_MR2 0x00000248
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#define DDR_MR3 0x00000000
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#define DDR_ODTCR 0x00010000
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0DLLCR 0x40000000
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#define DDR_DX0DQTR 0xFFFFFFFF
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#define DDR_DX0DQSTR 0x3DB02000
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1DLLCR 0x40000000
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#define DDR_DX1DQTR 0xFFFFFFFF
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#define DDR_DX1DQSTR 0x3DB02000
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#define DDR_DX2GCR 0x0000CE80
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#define DDR_DX2DLLCR 0x40000000
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#define DDR_DX2DQTR 0xFFFFFFFF
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#define DDR_DX2DQSTR 0x3DB02000
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#define DDR_DX3GCR 0x0000CE80
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#define DDR_DX3DLLCR 0x40000000
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#define DDR_DX3DQTR 0xFFFFFFFF
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#define DDR_DX3DQSTR 0x3DB02000
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#include "stm32mp15-ddr.dtsi"
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7
fdts/stm32mp151a-prtt1a-fw-config.dts
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7
fdts/stm32mp151a-prtt1a-fw-config.dts
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@ -0,0 +1,7 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (c) 2023, Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
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*/
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#define DDR_SIZE 0x10000000 /* 256 MB */
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#include "stm32mp15-fw-config.dtsi"
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235
fdts/stm32mp151a-prtt1a.dts
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235
fdts/stm32mp151a-prtt1a.dts
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@ -0,0 +1,235 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) 2023, Protonic Holland - All Rights Reserved
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* Author: David Jander <david@protonic.nl>
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*/
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/dts-v1/;
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#include "stm32mp151.dtsi"
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#include "stm32mp15-pinctrl.dtsi"
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#include "stm32mp15xxad-pinctrl.dtsi"
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-ddr3-1x2Gb-1066-binG.dtsi"
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/ {
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model = "Protonic PRTT1A";
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compatible = "prt,prtt1a", "st,stm32mp151";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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mmc0 = &sdmmc1;
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mmc1 = &sdmmc2;
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serial0 = &uart4;
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};
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memory@c0000000 {
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device_type = "memory";
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reg = <0xC0000000 0x10000000>;
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};
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};
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&iwdg2 {
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timeout-sec = <32>;
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status = "okay";
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secure-status = "okay";
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};
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&qspi {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
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reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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flash@0 {
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compatible = "spi-nand";
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reg = <0>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <104000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&qspi_bk1_pins_a {
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pins1 {
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bias-pull-up;
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drive-push-pull;
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slew-rate = <1>;
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};
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};
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&rcc {
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_PLL3P
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_LSI
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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>;
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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0 /*MCU*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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0 /*MCO2*/
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>;
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st,pkcs = <
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CLK_CKPER_HSE
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CLK_FMC_ACLK
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CLK_QSPI_ACLK
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CLK_ETH_DISABLED
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CLK_SDMMC12_PLL4P
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CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_SPI2S1_PLL3Q
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CLK_SPI2S23_PLL3Q
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CLK_SPI45_HSI
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CLK_SPI6_HSI
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CLK_I2C46_HSI
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CLK_SDMMC3_PLL4P
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CLK_USBO_USBPHY
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CLK_ADC_CKPER
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CLK_CEC_LSI
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CLK_I2C12_HSI
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CLK_I2C35_HSI
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CLK_UART1_HSI
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CLK_UART24_HSI
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CLK_UART35_HSI
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4R
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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CLK_SAI4_PLL3Q
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CLK_RNG1_LSI
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CLK_RNG2_LSI
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CLK_LPTIM1_PCLK1
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CLK_LPTIM23_PCLK3
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CLK_LPTIM45_LSI
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>;
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/* VCO = 1300.0 MHz => P = 650 (CPU) */
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pll1: st,pll@0 {
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compatible = "st,stm32mp1-pll";
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reg = <0>;
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cfg = <2 80 0 0 0 PQR(1,0,0)>;
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frac = <0x800>;
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};
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
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pll2: st,pll@1 {
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compatible = "st,stm32mp1-pll";
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reg = <1>;
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cfg = <2 65 1 0 0 PQR(1,1,1)>;
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frac = <0x1400>;
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};
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/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
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pll3: st,pll@2 {
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compatible = "st,stm32mp1-pll";
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reg = <2>;
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cfg = <1 33 1 16 36 PQR(1,1,1)>;
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frac = <0x1a04>;
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};
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/* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
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pll4: st,pll@3 {
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compatible = "st,stm32mp1-pll";
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reg = <3>;
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cfg = <1 39 3 11 4 PQR(1,1,1)>;
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};
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};
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&rng1 {
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status = "okay";
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};
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&rtc {
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status = "okay";
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};
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&sdmmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc1_b4_pins_a>;
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bus-width = <4>;
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status = "okay";
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};
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&sdmmc1_b4_pins_a {
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pins1 {
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bias-pull-up;
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};
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pins2 {
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bias-pull-up;
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};
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};
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/* NOTE: Although the PRTT1A does not have an eMMC, we declare it
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* anyway, in order to be able to use the same binary for the
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* PRTT1C also. All involved pins are N.C. on PRTT1A/S for that
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* reason, so it should do no harm. All inputs configured with
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* pull-ups to avoid floating inputs. */
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&sdmmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
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bus-width = <8>;
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status = "okay";
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};
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&sdmmc2_b4_pins_a {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
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<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
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};
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};
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&sdmmc2_d47_pins_a {
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pins {
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pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
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<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
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<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
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<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
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};
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_pins_a>;
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status = "okay";
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};
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&uart4_pins_a {
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pins1 {
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pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
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bias-pull-up;
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};
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};
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