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refactor(ethos-n): move build flags to ethosn_npu.mk

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The build flags to enable the Arm(R) Ethos(TM)-N NPU driver are in arm
platform specific make files i.e. plat/arm/common/arm_common.mk. These
flags are renamed and moved to ethosn_npu.mk. Other source and make
files are changed to reflect the changes in these flags.

Signed-off-by: Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com>
Change-Id: I6fd20225343c574cb5ac1f0f32ff2fc28ef37ea6
This commit is contained in:
Rajasekaran Kalidoss 2023-05-08 14:55:13 +02:00 • committed by rajasekaran.kalidoss
parent 29ae73e3fb
commit 352366ede4
17 changed files with 166 additions and 160 deletions

49
drivers/arm/ethosn/ethosn_npu.mk Normal file
View file

@ -0,0 +1,49 @@
#
# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Arm(R) Ethos(TM)-N NPU SiP service
ETHOSN_NPU_DRIVER := 0
$(eval $(call assert_boolean,ETHOSN_NPU_DRIVER))
$(eval $(call add_define,ETHOSN_NPU_DRIVER))
#Ethos-N NPU TZMP1
ETHOSN_NPU_TZMP1 := 0
$(eval $(call assert_boolean,ETHOSN_NPU_TZMP1))
$(eval $(call add_define,ETHOSN_NPU_TZMP1))
ifeq (${ETHOSN_NPU_TZMP1},1)
ifeq (${ETHOSN_NPU_DRIVER},0)
$(error "ETHOSN_NPU_TZMP1 is only available if ETHOSN_NPU_DRIVER=1)
endif
ifeq (${PLAT},juno)
$(eval $(call add_define,JUNO_ETHOSN_TZMP1))
else
$(error "ETHOSN_NPU_TZMP1 only supported on Juno platform, not ", ${PLAT})
endif
ifeq (${TRUSTED_BOARD_BOOT},0)
# We rely on TRUSTED_BOARD_BOOT to prevent the firmware code from being
# tampered with, which is required to protect the confidentiality of protected
# inference data.
$(error "ETHOSN_NPU_TZMP1 is only available if TRUSTED_BOARD_BOOT is enabled)
endif
# We need the FW certificate and key certificate
$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_key.crt,--npu-fw-key-cert))
$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_content.crt,--npu-fw-cert))
# We need the firmware to be built into the FIP
$(eval $(call TOOL_ADD_IMG,ETHOSN_NPU_FW,--npu-fw))
# Needed for our OIDs to be available in tbbr_cot_bl2.c
$(eval $(call add_define, PLAT_DEF_OID))
# Needed so that UUIDs from the FIP are available in BL2
$(eval $(call add_define,PLAT_DEF_FIP_UUID))
PLAT_INCLUDES += -I${PLAT_DIR}certificate/include
PLAT_INCLUDES += -Iinclude/drivers/arm/
PLAT_INCLUDES += -I${PLAT_DIR}fip
endif

64
drivers/arm/ethosn/ethosn_smc.c
View file

@ -17,9 +17,9 @@
#include <platform_def.h>
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
#include "ethosn_big_fw.h"
#endif
#endif /* ETHOSN_NPU_TZMP1 */
/*
* Number of Arm(R) Ethos(TM)-N NPU (NPU) devices available
@ -51,11 +51,11 @@
#define SEC_AUXCTLR_STASHING_VAL U(0xA5000000)
#define SEC_DEL_REG U(0x0004)
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
#define SEC_DEL_VAL U(0x808)
#else
#define SEC_DEL_VAL U(0x80C)
#endif
#endif /* ETHOSN_NPU_TZMP1 */
#define SEC_DEL_EXCC_MASK U(0x20)
#define SEC_SECCTLR_REG U(0x0010)
@ -104,8 +104,8 @@
#define TO_EXTEND_ADDR(addr) \
((addr >> SEC_ADDR_EXT_SHIFT) & SEC_ADDR_EXT_MASK)
#if ARM_ETHOSN_NPU_TZMP1
CASSERT(ARM_ETHOSN_NPU_FW_IMAGE_BASE > 0U, assert_ethosn_invalid_fw_image_base);
#if ETHOSN_NPU_TZMP1
CASSERT(ETHOSN_NPU_FW_IMAGE_BASE > 0U, assert_ethosn_invalid_fw_image_base);
static const struct ethosn_big_fw *big_fw;
#define FW_INITVTOR_ADDR(big_fw) \
@ -115,7 +115,7 @@ static const struct ethosn_big_fw *big_fw;
#define SYSCTRL0_INITVTOR_ADDR(value) \
(value & SEC_SYSCTRL0_INITVTOR_MASK)
#endif
#endif /* ETHOSN_NPU_TZMP1 */
static bool ethosn_get_device_and_core(uintptr_t core_addr,
const struct ethosn_device_t **dev_match,
@ -142,7 +142,7 @@ static bool ethosn_get_device_and_core(uintptr_t core_addr,
return false;
}
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
static uint32_t ethosn_core_read_arch_version(uintptr_t core_addr)
{
uint32_t npu_id = mmio_read_32(ETHOSN_CORE_SEC_REG(core_addr,
@ -155,23 +155,23 @@ static void ethosn_configure_stream_nsaid(const struct ethosn_core_t *core,
bool is_protected)
{
size_t i;
uint32_t streams[9] = {[0 ... 8] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID};
uint32_t streams[9] = {[0 ... 8] = ETHOSN_NPU_NS_RO_DATA_NSAID};
streams[FIRMWARE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID;
streams[PLE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID;
streams[FIRMWARE_STREAM_INDEX] = ETHOSN_NPU_PROT_FW_NSAID;
streams[PLE_STREAM_INDEX] = ETHOSN_NPU_PROT_FW_NSAID;
streams[WORKING_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
streams[WORKING_STREAM_INDEX] = ETHOSN_NPU_NS_RW_DATA_NSAID;
if (is_protected) {
streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RO_DATA_NSAID;
streams[INPUT_STREAM_INDEX] = ETHOSN_NPU_PROT_RO_DATA_NSAID;
streams[INTERMEDIATE_STREAM_INDEX] =
ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID;
streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID;
ETHOSN_NPU_PROT_RW_DATA_NSAID;
streams[OUTPUT_STREAM_INDEX] = ETHOSN_NPU_PROT_RW_DATA_NSAID;
} else {
streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID;
streams[INPUT_STREAM_INDEX] = ETHOSN_NPU_NS_RO_DATA_NSAID;
streams[INTERMEDIATE_STREAM_INDEX] =
ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
ETHOSN_NPU_NS_RW_DATA_NSAID;
streams[OUTPUT_STREAM_INDEX] = ETHOSN_NPU_NS_RW_DATA_NSAID;
}
for (i = 0U; i < ARRAY_SIZE(streams); ++i) {
@ -188,7 +188,7 @@ static void ethosn_configure_vector_table(uintptr_t core_addr)
FW_INITVTOR_ADDR(big_fw));
}
#endif
#endif /* ETHOSN_NPU_TZMP1 */
static void ethosn_configure_events(uintptr_t core_addr)
{
@ -343,7 +343,7 @@ static bool ethosn_core_reset(uintptr_t core_addr, bool hard_reset)
static int ethosn_core_boot_fw(uintptr_t core_addr)
{
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
const uintptr_t sysctrl0_reg = ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG);
const uint32_t sysctrl0_val = mmio_read_32(sysctrl0_reg);
const bool waiting = (sysctrl0_val & SEC_SYSCTRL0_CPU_WAIT);
@ -363,7 +363,7 @@ static int ethosn_core_boot_fw(uintptr_t core_addr)
return ETHOSN_SUCCESS;
#else
return ETHOSN_NOT_SUPPORTED;
#endif
#endif /* ETHOSN_NPU_TZMP1 */
}
static int ethosn_core_full_reset(const struct ethosn_device_t *device,
@ -392,17 +392,17 @@ static int ethosn_core_full_reset(const struct ethosn_device_t *device,
if (!device->has_reserved_memory) {
ethosn_configure_smmu_streams(device, core, asset_alloc_idx);
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
ethosn_configure_stream_nsaid(core, is_protected);
#endif
#endif /* ETHOSN_NPU_TZMP1 */
}
ethosn_configure_stream_addr_extends(device, core->addr);
ethosn_configure_stream_attr_ctlr(core->addr);
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
ethosn_configure_vector_table(core->addr);
#endif
#endif /* ETHOSN_NPU_TZMP1 */
ethosn_delegate_to_ns(core->addr);
@ -481,7 +481,7 @@ static uintptr_t ethosn_smc_core_handler(uint32_t fid,
static uintptr_t ethosn_smc_fw_prop_handler(u_register_t fw_property,
void *handle)
{
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
switch (fw_property) {
case ETHOSN_FW_PROP_VERSION:
SMC_RET4(handle, ETHOSN_SUCCESS,
@ -507,7 +507,7 @@ static uintptr_t ethosn_smc_fw_prop_handler(u_register_t fw_property,
}
#else
SMC_RET1(handle, ETHOSN_NOT_SUPPORTED);
#endif
#endif /* ETHOSN_NPU_TZMP1 */
}
uintptr_t ethosn_smc_handler(uint32_t smc_fid,
@ -554,17 +554,17 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid,
int ethosn_smc_setup(void)
{
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
struct ethosn_device_t *dev;
uint32_t arch_ver;
#endif
#endif /* ETHOSN_NPU_TZMP1 */
if (ETHOSN_NUM_DEVICES == 0U) {
ERROR("ETHOSN: No NPU found\n");
return ETHOSN_FAILURE;
}
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
/* Only one NPU core is supported in the TZMP1 setup */
if ((ETHOSN_NUM_DEVICES != 1U) ||
@ -580,7 +580,7 @@ int ethosn_smc_setup(void)
}
arch_ver = ethosn_core_read_arch_version(dev->cores[0U].addr);
big_fw = (struct ethosn_big_fw *)ARM_ETHOSN_NPU_FW_IMAGE_BASE;
big_fw = (struct ethosn_big_fw *)ETHOSN_NPU_FW_IMAGE_BASE;
if (!ethosn_big_fw_verify_header(big_fw, arch_ver)) {
return ETHOSN_FAILURE;
@ -591,7 +591,7 @@ int ethosn_smc_setup(void)
big_fw->fw_ver_patch);
#else
NOTICE("ETHOSN: Setup succeeded\n");
#endif
#endif /* ETHOSN_NPU_TZMP1 */
return 0;
}

4
fdts/juno.dts
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Arm Limited. All rights reserved.
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,6 +10,6 @@
};
#if ARM_ETHOSN_NPU_DRIVER
#if ETHOSN_NPU_DRIVER
#include "juno-ethosn.dtsi"
#endif

2
include/plat/arm/common/fconf_ethosn_getter.h
View file

@ -57,8 +57,6 @@ struct ethosn_config_t {
struct ethosn_device_t devices[ETHOSN_DEV_NUM_MAX];
};
int fconf_populate_arm_ethosn(uintptr_t config);
extern struct ethosn_config_t ethosn_config;
#endif /* FCONF_ETHOSN_GETTER_H */

2
plat/arm/board/juno/cert_create_tbbr.mk
View file

@ -7,7 +7,7 @@
PLAT_DEF_OID := 1
ifeq (${PLAT_DEF_OID},1)
ifeq (${ARM_ETHOSN_NPU_DRIVER},1)
ifeq (${ETHOSN_NPU_DRIVER},1)
$(eval $(call add_define, PLAT_DEF_OID))
$(eval $(call add_define, PDEF_CERTS))
$(eval $(call add_define, PDEF_EXTS))

8
plat/arm/board/juno/fdts/juno_tb_fw_config.dts
View file

@ -51,10 +51,10 @@
tos_fw_content_cert_uuid = "a49f4411-5e63-e411-8728-3f05722af33d";
nt_fw_content_cert_uuid = "8ec4c1f3-5d63-e411-a7a9-87ee40b23fa7";
plat_sp_content_cert_uuid = "776dfd44-8697-4c3b-91eb-c13e025a2a6f";
#if ARM_ETHOSN_NPU_TZMP1
arm_ethosn_npu_fw_uuid = "cfd499b5-a3bc-4a7e-98cb-48a41cb8dae1";
arm_ethosn_npu_fw_key_cert_uuid = "5666d004-ab98-40aa-8988-b72a03a256e2";
arm_ethosn_npu_fw_content_cert_uuid = "a5c418da-430f-48b1-88cd-93f67889d9ed";
#if ETHOSN_NPU_TZMP1
ethosn_npu_fw_uuid = "cfd499b5-a3bc-4a7e-98cb-48a41cb8dae1";
ethosn_npu_fw_key_cert_uuid = "5666d004-ab98-40aa-8988-b72a03a256e2";
ethosn_npu_fw_content_cert_uuid = "a5c418da-430f-48b1-88cd-93f67889d9ed";
#endif
};
};

4
plat/arm/board/juno/fip/plat_def_fip_uuid.h
View file

@ -7,8 +7,8 @@
#ifndef PLAT_DEF_FIP_UUID_H
#define PLAT_DEF_FIP_UUID_H
#ifdef ARM_ETHOSN_NPU_TZMP1
#ifdef ETHOSN_NPU_TZMP1
#include <drivers/arm/ethosn_fip.h>
#endif
#endif /* ETHOSN_NPU_TZMP1 */
#endif /* PLAT_DEF_FIP_UUID_H */

4
plat/arm/board/juno/fip/plat_def_uuid_config.c
View file

@ -12,11 +12,11 @@
#include "plat_def_fip_uuid.h"
toc_entry_t plat_def_toc_entries[] = {
#ifdef ARM_ETHOSN_NPU_TZMP1
#ifdef ETHOSN_NPU_TZMP1
ETHOSN_FW_KEY_CERTIFICATE_DEF,
ETHOSN_FW_CONTENT_CERTIFICATE_DEF,
ETHOSN_FW_DEF,
#endif
#endif /* ETHOSN_NPU_TZMP1 */
{
.name = NULL,
.uuid = { { 0 } },

10
plat/arm/board/juno/include/plat_tbbr_img_def.h
View file

@ -7,12 +7,12 @@
#ifndef JUNO_IMG_DEF_H
#define JUNO_IMG_DEF_H
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
/* Arm(R) Ethos(TM)-N NPU images */
#define ARM_ETHOSN_NPU_FW_KEY_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 1)
#define ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 2)
#define ARM_ETHOSN_NPU_FW_IMAGE_ID U(MAX_IMG_IDS_WITH_SPMDS + 3)
#define ETHOSN_NPU_FW_KEY_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 1)
#define ETHOSN_NPU_FW_CONTENT_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 2)
#define ETHOSN_NPU_FW_IMAGE_ID U(MAX_IMG_IDS_WITH_SPMDS + 3)
#define MAX_NUMBER_IDS U(MAX_IMG_IDS_WITH_SPMDS + 4)
#endif
#endif /* ETHOSN_NPU_TZMP1 */
#endif /* JUNO_IMG_DEF_H */

14
plat/arm/board/juno/include/platform_def.h
View file

@ -327,15 +327,15 @@
/* Protected NSAIDs and memory regions for the Arm(R) Ethos(TM)-N NPU driver */
#ifdef JUNO_ETHOSN_TZMP1
#define ARM_ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT
#define ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT
#define ARM_ETHOSN_NPU_PROT_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT
#define ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT
#define ETHOSN_NPU_PROT_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT
#define ETHOSN_NPU_PROT_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT
#define ARM_ETHOSN_NPU_NS_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS
#define ARM_ETHOSN_NPU_NS_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS
#define ETHOSN_NPU_NS_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS
#define ETHOSN_NPU_NS_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS
#define ARM_ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE
#define ARM_ETHOSN_NPU_FW_IMAGE_LIMIT \
#define ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE
#define ETHOSN_NPU_FW_IMAGE_LIMIT \
(JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE + JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE)
#endif

28
plat/arm/board/juno/juno_tbbr_cot_bl2.c
View file

@ -32,9 +32,9 @@ static unsigned char nt_fw_config_hash_buf[HASH_DER_LEN];
#if defined(SPD_spmd)
static unsigned char sp_pkg_hash_buf[MAX_SP_IDS][HASH_DER_LEN];
#endif /* SPD_spmd */
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
static unsigned char npu_fw_image_hash_buf[HASH_DER_LEN];
#endif /* ARM_ETHOSN_NPU_TZMP1 */
#endif /* ETHOSN_NPU_TZMP1 */
static auth_param_type_desc_t non_trusted_nv_ctr = AUTH_PARAM_TYPE_DESC(
@ -87,12 +87,12 @@ static auth_param_type_desc_t sp_pkg7_hash = AUTH_PARAM_TYPE_DESC(
static auth_param_type_desc_t sp_pkg8_hash = AUTH_PARAM_TYPE_DESC(
AUTH_PARAM_HASH, SP_PKG8_HASH_OID);
#endif /* SPD_spmd */
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
static auth_param_type_desc_t npu_fw_cert_pk = AUTH_PARAM_TYPE_DESC(
AUTH_PARAM_PUB_KEY, ETHOSN_NPU_FW_CONTENT_CERT_PK_OID);
static auth_param_type_desc_t npu_fw_image_hash = AUTH_PARAM_TYPE_DESC(
AUTH_PARAM_HASH, ETHOSN_NPU_FW_BINARY_OID);
#endif /* ARM_ETHOSN_NPU_TZMP1 */
#endif /* ETHOSN_NPU_TZMP1 */
/*
* Trusted key certificate
@ -662,9 +662,9 @@ DEFINE_SIP_SP_PKG(7);
DEFINE_SIP_SP_PKG(8);
#endif /* SPD_spmd */
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
static const auth_img_desc_t npu_fw_key_cert = {
.img_id = ARM_ETHOSN_NPU_FW_KEY_CERT_ID,
.img_id = ETHOSN_NPU_FW_KEY_CERT_ID,
.img_type = IMG_CERT,
.parent = &trusted_key_cert,
.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
@ -697,7 +697,7 @@ static const auth_img_desc_t npu_fw_key_cert = {
};
static const auth_img_desc_t npu_fw_content_cert = {
.img_id = ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID,
.img_id = ETHOSN_NPU_FW_CONTENT_CERT_ID,
.img_type = IMG_CERT,
.parent = &npu_fw_key_cert,
.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
@ -730,7 +730,7 @@ static const auth_img_desc_t npu_fw_content_cert = {
};
static const auth_img_desc_t npu_fw_image = {
.img_id = ARM_ETHOSN_NPU_FW_IMAGE_ID,
.img_id = ETHOSN_NPU_FW_IMAGE_ID,
.img_type = IMG_RAW,
.parent = &npu_fw_content_cert,
.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
@ -743,7 +743,7 @@ static const auth_img_desc_t npu_fw_image = {
}
}
};
#endif /* ARM_ETHOSN_NPU_TZMP1 */
#endif /* ETHOSN_NPU_TZMP1 */
static const auth_img_desc_t * const cot_desc[] = {
@ -778,11 +778,11 @@ static const auth_img_desc_t * const cot_desc[] = {
[SP_PKG7_ID] = &sp_pkg7,
[SP_PKG8_ID] = &sp_pkg8,
#endif
#if ARM_ETHOSN_NPU_TZMP1
[ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = &npu_fw_key_cert,
[ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = &npu_fw_content_cert,
[ARM_ETHOSN_NPU_FW_IMAGE_ID] = &npu_fw_image,
#endif /* ARM_ETHOSN_NPU_TZMP1 */
#if ETHOSN_NPU_TZMP1
[ETHOSN_NPU_FW_KEY_CERT_ID] = &npu_fw_key_cert,
[ETHOSN_NPU_FW_CONTENT_CERT_ID] = &npu_fw_content_cert,
[ETHOSN_NPU_FW_IMAGE_ID] = &npu_fw_image,
#endif /* ETHOSN_NPU_TZMP1 */
};
/* Register the CoT in the authentication module */

5
plat/arm/board/juno/platform.mk
View file

@ -43,8 +43,8 @@ $(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME))
JUNO_TZMP1 := 0
$(eval $(call assert_boolean,JUNO_TZMP1))
ifeq (${JUNO_TZMP1}, 1)
ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
$(error JUNO_TZMP1 cannot be used together with ARM_ETHOSN_NPU_TZMP1)
ifeq (${ETHOSN_NPU_TZMP1},1)
$(error JUNO_TZMP1 cannot be used together with ETHOSN_NPU_TZMP1)
else
$(eval $(call add_define,JUNO_TZMP1))
endif
@ -207,6 +207,7 @@ $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
# Add the HW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
include drivers/arm/ethosn/ethosn_npu.mk
include plat/arm/board/common/board_common.mk
include plat/arm/common/arm_common.mk
include plat/arm/soc/common/soc_css.mk

12
plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
View file

@ -223,17 +223,17 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
},
#endif /* EL3_PAYLOAD_BASE */
# if ARM_ETHOSN_NPU_TZMP1
# if ETHOSN_NPU_TZMP1
{
.image_id = ARM_ETHOSN_NPU_FW_IMAGE_ID,
.image_id = ETHOSN_NPU_FW_IMAGE_ID,
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_2, image_info_t, 0),
.image_info.image_base = ARM_ETHOSN_NPU_FW_IMAGE_BASE,
.image_info.image_max_size = ARM_ETHOSN_NPU_FW_IMAGE_LIMIT -
ARM_ETHOSN_NPU_FW_IMAGE_BASE,
.image_info.image_base = ETHOSN_NPU_FW_IMAGE_BASE,
.image_info.image_max_size = ETHOSN_NPU_FW_IMAGE_LIMIT -
ETHOSN_NPU_FW_IMAGE_BASE,
.next_handoff_image_id = INVALID_IMAGE_ID,
},
# endif
#endif /* ETHOSN_NPU_TZMP1 */
};
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)

48
plat/arm/common/arm_common.mk
View file

@ -114,48 +114,6 @@ ifeq (${ARM_LINUX_KERNEL_AS_BL33},1)
endif
endif
# Arm(R) Ethos(TM)-N NPU SiP service
ARM_ETHOSN_NPU_DRIVER := 0
$(eval $(call assert_boolean,ARM_ETHOSN_NPU_DRIVER))
$(eval $(call add_define,ARM_ETHOSN_NPU_DRIVER))
# Arm(R) Ethos(TM)-N NPU TZMP1
ARM_ETHOSN_NPU_TZMP1 := 0
$(eval $(call assert_boolean,ARM_ETHOSN_NPU_TZMP1))
$(eval $(call add_define,ARM_ETHOSN_NPU_TZMP1))
ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
ifeq (${ARM_ETHOSN_NPU_DRIVER},0)
$(error ARM_ETHOSN_NPU_TZMP1 is only available if ARM_ETHOSN_NPU_DRIVER=1)
endif
ifeq (${PLAT},juno)
$(eval $(call add_define,JUNO_ETHOSN_TZMP1))
else
$(error ARM_ETHOSN_NPU_TZMP1 only supported on Juno platform, not ${PLAT})
endif
ifeq (${TRUSTED_BOARD_BOOT},0)
# We rely on TRUSTED_BOARD_BOOT to prevent the firmware code from being
# tampered with, which is required to protect the confidentiality of protected
# inference data.
$(error ARM_ETHOSN_NPU_TZMP1 is only available if TRUSTED_BOARD_BOOT is enabled)
endif
# We need the FW certificate and key certificate
$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_key.crt,--npu-fw-key-cert))
$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_content.crt,--npu-fw-cert))
# Needed for our OIDs to be available in tbbr_cot_bl2.c
$(eval $(call add_define, PLAT_DEF_OID))
PLAT_INCLUDES += -I${PLAT_DIR}certificate/include
PLAT_INCLUDES += -Iinclude/drivers/arm/
# We need the firmware to be built into the FIP
$(eval $(call TOOL_ADD_IMG,ARM_ETHOSN_NPU_FW,--npu-fw))
# Needed so that UUIDs from the FIP are available in BL2
$(eval $(call add_define,PLAT_DEF_FIP_UUID))
PLAT_INCLUDES += -I${PLAT_DIR}fip
endif # ARM_ETHOSN_NPU_TZMP1
# Use an implementation of SHA-256 with a smaller memory footprint but reduced
# speed.
$(eval $(call add_define,MBEDTLS_SHA256_SMALLER))
@ -348,18 +306,18 @@ BL31_SOURCES += plat/arm/common/arm_bl31_setup.c \
plat/arm/common/arm_topology.c \
plat/common/plat_psci_common.c
ifneq ($(filter 1,${ENABLE_PMF} ${ARM_ETHOSN_NPU_DRIVER}),)
ifneq ($(filter 1,${ENABLE_PMF} ${ETHOSN_NPU_DRIVER}),)
ARM_SVC_HANDLER_SRCS :=
ifeq (${ENABLE_PMF},1)
ARM_SVC_HANDLER_SRCS += lib/pmf/pmf_smc.c
endif
ifeq (${ARM_ETHOSN_NPU_DRIVER},1)
ifeq (${ETHOSN_NPU_DRIVER},1)
ARM_SVC_HANDLER_SRCS += plat/arm/common/fconf/fconf_ethosn_getter.c \
drivers/delay_timer/delay_timer.c \
drivers/arm/ethosn/ethosn_smc.c
ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
ifeq (${ETHOSN_NPU_TZMP1},1)
ARM_SVC_HANDLER_SRCS += drivers/arm/ethosn/ethosn_big_fw.c
endif
endif

12
plat/arm/common/arm_sip_svc.c
View file

@ -34,13 +34,13 @@ static int arm_sip_setup(void)
#endif /* USE_DEBUGFS */
#if ARM_ETHOSN_NPU_DRIVER
#if ETHOSN_NPU_DRIVER
if (ethosn_smc_setup() != 0) {
return 1;
}
#endif /* ARM_ETHOSN_NPU_DRIVER */
#endif /* ETHOSN_NPU_DRIVER */
return 0;
}
@ -81,14 +81,14 @@ static uintptr_t arm_sip_handler(unsigned int smc_fid,
#endif /* USE_DEBUGFS */
#if ARM_ETHOSN_NPU_DRIVER
#if ETHOSN_NPU_DRIVER
if (is_ethosn_fid(smc_fid)) {
return ethosn_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
handle, flags);
}
#endif /* ARM_ETHOSN_NPU_DRIVER */
#endif /* ETHOSN_NPU_DRIVER */
switch (smc_fid) {
case ARM_SIP_SVC_EXE_STATE_SWITCH: {
@ -114,10 +114,10 @@ static uintptr_t arm_sip_handler(unsigned int smc_fid,
/* PMF calls */
call_count += PMF_NUM_SMC_CALLS;
#if ARM_ETHOSN_NPU_DRIVER
#if ETHOSN_NPU_DRIVER
/* ETHOSN calls */
call_count += ETHOSN_NUM_SMC_CALLS;
#endif /* ARM_ETHOSN_NPU_DRIVER */
#endif /* ETHOSN_NPU_DRIVER */
/* State switch call */
call_count += 1;

56
plat/arm/common/fconf/arm_fconf_io.c
View file

@ -68,9 +68,9 @@ const io_uuid_spec_t arm_uuid_spec[MAX_NUMBER_IDS] = {
[TOS_FW_CONFIG_ID] = {UUID_TOS_FW_CONFIG},
[NT_FW_CONFIG_ID] = {UUID_NT_FW_CONFIG},
[RMM_IMAGE_ID] = {UUID_REALM_MONITOR_MGMT_FIRMWARE},
#if ARM_ETHOSN_NPU_TZMP1
[ARM_ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW},
#endif /* ARM_ETHOSN_NPU_TZMP1 */
#if ETHOSN_NPU_TZMP1
[ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW},
#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {UUID_TRUSTED_BOOT_FW_CERT},
@ -91,10 +91,10 @@ const io_uuid_spec_t arm_uuid_spec[MAX_NUMBER_IDS] = {
[SIP_SP_CONTENT_CERT_ID] = {UUID_SIP_SECURE_PARTITION_CONTENT_CERT},
[PLAT_SP_CONTENT_CERT_ID] = {UUID_PLAT_SECURE_PARTITION_CONTENT_CERT},
#endif
#if ARM_ETHOSN_NPU_TZMP1
[ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE},
[ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE},
#endif /* ARM_ETHOSN_NPU_TZMP1 */
#if ETHOSN_NPU_TZMP1
[ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE},
[ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE},
#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
};
@ -198,13 +198,13 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = {
(uintptr_t)&arm_uuid_spec[NT_FW_CONFIG_ID],
open_fip
},
#if ARM_ETHOSN_NPU_TZMP1
[ARM_ETHOSN_NPU_FW_IMAGE_ID] = {
#if ETHOSN_NPU_TZMP1
[ETHOSN_NPU_FW_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_IMAGE_ID],
(uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_IMAGE_ID],
open_fip
},
#endif /* ARM_ETHOSN_NPU_TZMP1 */
#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {
@ -285,18 +285,18 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = {
open_fip
},
#endif
#if ARM_ETHOSN_NPU_TZMP1
[ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = {
#if ETHOSN_NPU_TZMP1
[ETHOSN_NPU_FW_KEY_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_KEY_CERT_ID],
(uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_KEY_CERT_ID],
open_fip
},
[ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = {
[ETHOSN_NPU_FW_CONTENT_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID],
(uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_CONTENT_CERT_ID],
open_fip
},
#endif /* ARM_ETHOSN_NPU_TZMP1 */
#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
};
@ -305,11 +305,11 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = {
#define FCONF_ARM_IO_UUID_NUM_BASE U(10)
#if ARM_ETHOSN_NPU_TZMP1
#if ETHOSN_NPU_TZMP1
#define FCONF_ARM_IO_UUID_NUM_NPU U(1)
#else
#define FCONF_ARM_IO_UUID_NUM_NPU U(0)
#endif
#endif /* ETHOSN_NPU_TZMP1 */
#if TRUSTED_BOARD_BOOT
#define FCONF_ARM_IO_UUID_NUM_TBB U(12)
@ -323,11 +323,11 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = {
#define FCONF_ARM_IO_UUID_NUM_SPD U(0)
#endif /* TRUSTED_BOARD_BOOT && defined(SPD_spmd) */
#if TRUSTED_BOARD_BOOT && ARM_ETHOSN_NPU_TZMP1
#if TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1
#define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(2)
#else
#define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(0)
#endif /* TRUSTED_BOARD_BOOT && ARM_ETHOSN_NPU_TZMP1 */
#endif /* TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1 */
#define FCONF_ARM_IO_UUID_NUMBER FCONF_ARM_IO_UUID_NUM_BASE + \
FCONF_ARM_IO_UUID_NUM_NPU + \
@ -355,9 +355,9 @@ static const struct policies_load_info load_info[FCONF_ARM_IO_UUID_NUMBER] = {
{SOC_FW_CONFIG_ID, "soc_fw_cfg_uuid"},
{TOS_FW_CONFIG_ID, "tos_fw_cfg_uuid"},
{NT_FW_CONFIG_ID, "nt_fw_cfg_uuid"},
#if ARM_ETHOSN_NPU_TZMP1
{ARM_ETHOSN_NPU_FW_IMAGE_ID, "arm_ethosn_npu_fw_uuid"},
#endif /* ARM_ETHOSN_NPU_TZMP1 */
#if ETHOSN_NPU_TZMP1
{ETHOSN_NPU_FW_IMAGE_ID, "ethosn_npu_fw_uuid"},
#endif /* ETHOSN_NPU_TZMP1 */
#if TRUSTED_BOARD_BOOT
{CCA_CONTENT_CERT_ID, "cca_cert_uuid"},
{CORE_SWD_KEY_CERT_ID, "core_swd_cert_uuid"},
@ -375,10 +375,10 @@ static const struct policies_load_info load_info[FCONF_ARM_IO_UUID_NUMBER] = {
{SIP_SP_CONTENT_CERT_ID, "sip_sp_content_cert_uuid"},
{PLAT_SP_CONTENT_CERT_ID, "plat_sp_content_cert_uuid"},
#endif
#if ARM_ETHOSN_NPU_TZMP1
{ARM_ETHOSN_NPU_FW_KEY_CERT_ID, "arm_ethosn_npu_fw_key_cert_uuid"},
{ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID, "arm_ethosn_npu_fw_content_cert_uuid"},
#endif /* ARM_ETHOSN_NPU_TZMP1 */
#if ETHOSN_NPU_TZMP1
{ETHOSN_NPU_FW_KEY_CERT_ID, "ethosn_npu_fw_key_cert_uuid"},
{ETHOSN_NPU_FW_CONTENT_CERT_ID, "ethosn_npu_fw_content_cert_uuid"},
#endif /* ETHOSN_NPU_TZMP1 */
#endif /* TRUSTED_BOARD_BOOT */
};

4
tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
View file

@ -8,8 +8,8 @@ PLAT_DEF_UUID := yes
ifeq (${PLAT_DEF_UUID}, yes)
HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
HOSTCCFLAGS += -DARM_ETHOSN_NPU_TZMP1
ifeq (${ETHOSN_NPU_TZMP1},1)
HOSTCCFLAGS += -DETHOSN_NPU_TZMP1
endif
INCLUDE_PATHS += -I./ -I${PLAT_DIR}fip -I../../include/
OBJECTS += ${PLAT_DIR}fip/plat_def_uuid_config.o