Update version and release schedule for the upcoming TF-A
release v2.10.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I505fbb034a74ce1cc6bc20efdd26803e6fb8c0c1
* changes:
refactor(el3-runtime): plat_ic_has_interrupt_type returns bool
fix(el3-runtime): leverage generic interrupt controller helpers
fix(gicv3): map generic interrupt type to GICv3 group
chore(gicv2): use interrupt group instead of type
Remove the dcc_console_init() function. The initialization function
is not being used and serves no purpose.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I056d09e153998d686d3b95ad39c563f797184c18
Revise the AST2700 boot flow to the RESET_TO_BL31 scheme.
The execution of BL1/2 can be saved from ARM CA35 while most
low level platform initialization are moved to a preceding MCU.
This patch updates the build configuration and also adds
the SMP mailbox setup code to hold secondary cores until
they are being waken up.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I7e0aa6416b92b97036153db1d9a26baaa41b7b18
Implement firmware handoff from BL2 to BL33 on qemu platform
compliant to Firmware handoff specification v0.9.
Change-Id: Id8d5206a71ef6ec97cf3c97995de328ebf0600cc
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Add unregistration function for the JTAG DCC (Debug Communication
Channel) console.
The unregistration function flushes DCC buffer before unregistering
the dcc console to make sure that no output char is pending.
Since console_flush() flushes chars for all registered consoles on
the platform, which is not required in this case, dcc_console_flush()
is being called instead.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I6f15a07c6ee947dc0e7aa8fb069227618080e611
Remove the use of SMC_RET2 in the mtk_emi_mpu_sip_handler function. The
current smc driver in the atf driver has switched to using SMC_RET4 for
smc call clients. This change aligns the return value handling with the
updated driver behavior that ensures consistency and avoids potential
issues with the old return value.
Change-Id: I87f25b438d2119837c45bed80a8224fcfd141fb6
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
Rather than returning 0 or 1, the above function returns bool false
or true. No functional change.
Change-Id: Iea904ffc368568208fa8203e0d2e0cdaa500b1e0
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Rather than validating the type of interrupts supported by the
platform interrupt controller, the interrupt management framework can
directly use helper utilities implemented by the generic interrupt
controller driver.
Change-Id: I735f8d2742a2c7974d11c0a5ddc771ad807c635c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
The generic interrupt controller identifies an interrupt based on its
type whereas the GIC uses the notion of groups to identify an
interrupt.
Currently, they are used interchangeably in GICv3 driver. It did not
cause any functional issues since the matching type and group had the
same value for corresponding macros. This patch makes the necessary
fixes.
The generic interrupt controller APIs, such as
plat_ic_set_interrupt_type map interrupt type to interrupt group
supported by the GICv3 IP. Similarly, other generic interrupt
controller APIs map interrupt group to interrupt type as needed.
This patch also changes the name of the helper functions to use group
rather than type for handling interrupts.
Change-Id: Ie2d88a3260c71e4ab9c8baacde24cc21e551de3d
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
The generic interrupt controller identifies an interrupt based on its
type whereas the GIC uses the notion of groups to identify an
interrupt.
This patch changes the name of the helper functions to use group
rather than type for handling interrupts. No functional change in this
patch.
Change-Id: If13ec65cc6c87c2da73a3d54b033f02635ff924a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Provide a STATIC command line build option for platforms willing to
build fiptool statically and remove dependency to toolchain and OpenSSL
libraries.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I1d1b6676df50081828170e2b0ab7b71c4ec19d6e
Add transfer list APIs and firmware handoff build option.
Change-Id: I68a0ace22c7e50fcdacd101eb76b271d7b76d8ff
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Update the revision and variant information in the
errata ABI file for Cortex-A710, erratum ID - 2058056
to match the revision and variant in the cortex_a710.S
file.
Change-Id: I4b974ac1f94d770f3ae7c15c88f42380c944eb43
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
This patch fixes the mitigation for erratum 1941500 for the
Cortex-A78AE CPUs. The right fix is to set the bit 8, whereas
the current code clears it.
Reported-by: matthias.rosenfelder@nio.io
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ib7c3fddd567eeae6204756377e0f77a573c0a911
Add pkcs11 engine support which allows using keys that are securely
stored on a HSM or TPM. To use this feature the user has to supply
an RFC 7512 compliant PKCS11 URI to a key instead of a file as an
argument to one of the key options. This change is fully backwards
compatible.
This change makes use of the openssl engine API which is deprecated
since openssl 3.0 and will most likely be removed in version 4. So
pkcs11 support will have to be updated to the openssl provider API
in the near future.
Signed-off-by: Robin van der Gracht <robin@protonic.nl>
Change-Id: If96725988ca62c5613ec59123943bf15922f5d1f
key->key and k will point to the same if PEM_read_PrivateKey
(pem_read_bio_key_decoder) succeeds. There is no need for the temporary
'k' pointer here.
Signed-off-by: Robin van der Gracht <robin@protonic.nl>
Change-Id: I219c49d331eb6dd7200b49b75d47fd66da3d82dd
CONSOLE_FLAG_CRASH should be also setup to get crash logs on
the same console. Both platforms are using crash console
implementation from plat/common/aarch64/crash_console_helpers.S
that's why there is necessary to setup CONSOLE_FLAG_CRASH.
plat_crash_console_putc() implementation is saying:
"int plat_crash_console_putc(char c)
Prints the character on all consoles registered with the console
framework that have CONSOLE_FLAG_CRASH set. Note that this is only
helpful for crashes that occur after the platform intialization code
has registered a console. Platforms using this implementation need to
ensure that all console drivers they use that have the CRASH flag set
support this (i.e. are written in assembly and comply to the register
clobber requirements of plat_crash_console_putc()."
Change-Id: I314cacbcb0bfcc85fe734882e38718f2763cdbf4
Signed-off-by: Michal Simek <michal.simek@amd.com>
Private plat_crash_console_init() has all the setup commented
that's why it was never been tested.
pl011 uart is supposed to be used as crash console and it should be
enought to add CONSOLE_FLAG_CRASH and remove platform specific
implementation and use generic one.
Early console can't be used for early ASM debugging but that's
expected and not required.
Change-Id: I1267fd78c0d6532a0baddbcad8a5b2a7dfc7750b
Signed-off-by: Michal Simek <michal.simek@amd.com>
Commit(f5211420b refactor(cpufeat): refactor arch feature build
options) accidentally added nested virtualization support to mandatory
8.4 features move this to optional 8.4 features list.
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I3eb84ea489b6a5cc419359bc056aaadcced0ad0e
Neoverse V2 erratum 2743011 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I0e06ca723a1cce51fb027b7160f3dd06a4c93e64
Neoverse V2 erratum 2779510 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set bit[47] of CPUACTLR3_EL1 which might have a small impact on
power and negligible impact on performance.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I6d937747bdcbf2913a64c4037f99918cbc466e80
Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations
to other PE caches. There might be a small performance degradation
to this workaround for certain workloads that share data.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id026edcb7ee1ca93371ce0001d18f5a8282c49ba
Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all
revisions <= r0p2 and is still open. The workaround is to write the
value 4'b1001 to the PF_MODE bits in the IMP_CPUECTLR2_EL1 register
which will place the data prefetcher in the most conservative mode
instead of disabling it.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ic6c76375df465a4ad2e20dd7add7037477d973c1
RME patch series shown that we can build larger BL1 than we can run:
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.9(debug):v2.9.0-736-g08548888a
NOTICE: BL1: Built : 12:10:39, Sep 18 2023
INFO: BL1: RAM 0x3ffee000 - 0x3fffb000
INFO: BL1: Loading BL2
WARNING: Firmware Image Package header check failed.
RME pushed debug build BL1 over 0x8000 in size.
This exposed an error where FIP_BASE (supposed to be at BL1_SIZE offset
from start of flash) was actually 0x8000 and not 0x12000.
Make sure we have space for BL1 by deriving FIP_BASE from it.
Note: this is a breaking change for edk2 FD image generation, which had
similarly hardcoded a 0x8000 offset. These images must be updated in
lock-step.
Change-Id: I8a1a85e82319945a4412c424467d818d5b6e4ecd
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
