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fix(qemu_sbsa): align FIP base to BL1 size

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RME patch series shown that we can build larger BL1 than we can run:

NOTICE:  Booting Trusted Firmware
NOTICE:  BL1: v2.9(debug):v2.9.0-736-g08548888a
NOTICE:  BL1: Built : 12:10:39, Sep 18 2023
INFO:    BL1: RAM 0x3ffee000 - 0x3fffb000
INFO:    BL1: Loading BL2
WARNING: Firmware Image Package header check failed.

RME pushed debug build BL1 over 0x8000 in size.
This exposed an error where FIP_BASE (supposed to be at BL1_SIZE offset
from start of flash) was actually 0x8000 and not 0x12000.
Make sure we have space for BL1 by deriving FIP_BASE from it.

Note: this is a breaking change for edk2 FD image generation, which had
similarly hardcoded a 0x8000 offset. These images must be updated in
lock-step.

Change-Id: I8a1a85e82319945a4412c424467d818d5b6e4ecd
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
This commit is contained in:
Marcin Juszkiewicz 2023-09-18 12:47:45 +02:00 • committed by Leif Lindholm
parent cc933e1d12
commit 408cde8a59
1 changed files with 1 additions and 1 deletions
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2
plat/qemu/qemu_sbsa/include/platform_def.h
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@ -199,7 +199,7 @@
#define QEMU_FLASH1_BASE 0x10000000
#define QEMU_FLASH1_SIZE 0x10000000
#define PLAT_QEMU_FIP_BASE 0x00008000
#define PLAT_QEMU_FIP_BASE BL1_SIZE
#define PLAT_QEMU_FIP_MAX_SIZE 0x00400000
/* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */