Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-09 06:13:54 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge changes from topic "stm32mp2" into integration

Browse source 
* changes:
  feat(stm32mp2): generate stm32 file
  feat(stm32mp2-fdts): add stm32mp257f-ev1 board
  feat(stm32mp2-fdts): introduce stm32mp25 pinctrl files
  feat(stm32mp2-fdts): introduce stm32mp25 SoCs family
  feat(stm32mp2): add console configuration
  feat(st): add RCC registers list
  feat(st-uart): add AARCH64 stm32_console driver
  feat(st): introduce new platform STM32MP2
  feat(dt-bindings): add the STM32MP2 clock and reset bindings
  docs(changelog): add scopes for STM32MP2
  feat(docs): introduce STM32MP2 doc
  refactor(docs): add a sub-menu for ST platforms
  refactor(st): move plat_image_load.c
  refactor(st): rename PLAT_NB_FIXED_REGS
  refactor(st): move some storage definitions to common part
  refactor(st): move SDMMC definitions to driver
  feat(st-clock): stub fdt_get_rcc_secure_state
  feat(st-clock): allow aarch64 compilation of STGEN functions
  feat(st): allow AARCH64 compilation for common code
  refactor(st): rename QSPI macros
This commit is contained in:
Manish V Badarkhe 2023-09-15 09:41:44 +02:00 • committed by TrustedFirmware Code Review
commit cc933e1d12
49 changed files with 8405 additions and 346 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
changelog.yaml
View file

@ -589,6 +589,9 @@ subsections:
- title: STM32MP15
scope: stm32mp15
- title: STM32MP2
scope: stm32mp2
- title: Texas Instruments
scope: ti
@ -1225,6 +1228,9 @@ subsections:
- title: STM32MP15
scope: stm32mp15-fdts
- title: STM32MP2
scope: stm32mp2-fdts
- title: PIE
scope: pie

1
docs/about/maintainers.rst
View file

@ -789,6 +789,7 @@ STM32MP1 platform port
^^^^^^^^^^^^^^^^^^^^^^
:|M|: Yann Gautier <yann.gautier@st.com>
:|G|: `Yann-lms`_
:|F|: docs/plat/st/*
:|F|: docs/plat/stm32mp1.rst
:|F|: drivers/st/
:|F|: fdts/stm32\*

2
docs/plat/index.rst
View file

@ -42,7 +42,7 @@ Platform Ports
rockchip
socionext-uniphier
synquacer
stm32mp1
st/index
ti-k3
xilinx-versal-net
xilinx-versal

14
docs/plat/st/index.rst Normal file
View file

@ -0,0 +1,14 @@
STMicroelectronics STM32 MPUs
=============================
.. toctree::
:maxdepth: 1
:caption: Contents
stm32mpus
stm32mp1
stm32mp2
--------------
*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*

219
docs/plat/st/stm32mp1.rst Normal file
View file

@ -0,0 +1,219 @@
STM32MP1
========
STM32MP1 is a microprocessor designed by STMicroelectronics
based on Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.
More information can be found on `STM32MP1 Series`_ page.
For TF-A common configuration of STM32 MPUs, please check
:ref:`STM32 MPUs` page.
STM32MP1 Versions
-----------------
There are 2 variants for STM32MP1: STM32MP13 and STM32MP15
STM32MP13 Versions
~~~~~~~~~~~~~~~~~~
The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible:
- STM32MP131: Single Cortex-A7 core
- STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
- STM32MP135: STM32MP133 + DCMIPP, LTDC
Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
- A Cortex-A7 @ 650 MHz
- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
- D Cortex-A7 @ 900 MHz
- F Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz
STM32MP15 Versions
~~~~~~~~~~~~~~~~~~
The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible:
- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD
- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD
- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
- A Basic + Cortex-A7 @ 650 MHz
- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
- D Basic + Cortex-A7 @ 800 MHz
- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
The `STM32MP1 part number codification`_ page gives more information about part numbers.
Memory mapping
--------------
::
0x00000000 +-----------------+
| | ROM
0x00020000 +-----------------+
| |
| ... |
| |
0x2FFC0000 +-----------------+ \
| BL32 DTB | |
0x2FFC5000 +-----------------+ |
| BL32 | |
0x2FFDF000 +-----------------+ |
| ... | |
0x2FFE3000 +-----------------+ |
| BL2 DTB | | Embedded SRAM
0x2FFEA000 +-----------------+ |
| BL2 | |
0x2FFFF000 +-----------------+ |
| SCMI mailbox | |
0x30000000 +-----------------+ /
| |
| ... |
| |
0x40000000 +-----------------+
| |
| | Devices
| |
0xC0000000 +-----------------+ \
| | |
0xC0100000 +-----------------+ |
| BL33 | | Non-secure RAM (DDR)
| ... | |
| | |
0xFFFFFFFF +-----------------+ /
Build Instructions
------------------
STM32MP1x specific flags
~~~~~~~~~~~~~~~~~~~~~~~~
Dedicated STM32MP1 flags:
- | ``STM32_TF_VERSION``: to manage BL2 monotonic counter.
| Default: 0
- | ``STM32MP13``: to select STM32MP13 variant configuration.
| Default: 0
- | ``STM32MP15``: to select STM32MP15 variant configuration.
| Default: 1
Boot with FIP
~~~~~~~~~~~~~
You need to build BL2, BL32 (SP_min or OP-TEE) and BL33 (U-Boot) before building FIP binary.
U-Boot
______
.. code:: bash
cd <u-boot_directory>
make stm32mp15_trusted_defconfig
make DEVICE_TREE=stm32mp157c-ev1 all
OP-TEE (optional)
_________________
.. code:: bash
cd <optee_directory>
make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 \
CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts
TF-A BL32 (SP_min)
__________________
If you choose not to use OP-TEE, you can use TF-A SP_min.
To build TF-A BL32, and its device tree file:
.. code:: bash
make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-ev1.dtb bl32 dtbs
TF-A BL2
________
To build TF-A BL2 with its STM32 header for SD-card boot:
.. code:: bash
make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
DTB_FILE_NAME=stm32mp157c-ev1.dtb STM32MP_SDMMC=1
For other boot devices, you have to replace STM32MP_SDMMC in the previous command
with the desired device flag.
This BL2 is independent of the BL32 used (SP_min or OP-TEE)
FIP
___
With BL32 SP_min:
.. code:: bash
make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
AARCH32_SP=sp_min \
DTB_FILE_NAME=stm32mp157c-ev1.dtb \
BL33=<u-boot_directory>/u-boot-nodtb.bin \
BL33_CFG=<u-boot_directory>/u-boot.dtb \
fip
With OP-TEE:
.. code:: bash
make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
AARCH32_SP=optee \
DTB_FILE_NAME=stm32mp157c-ev1.dtb \
BL33=<u-boot_directory>/u-boot-nodtb.bin \
BL33_CFG=<u-boot_directory>/u-boot.dtb \
BL32=<optee_directory>/tee-header_v2.bin \
BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin
BL32_EXTRA2=<optee_directory>/tee-pageable_v2.bin
fip
Trusted Boot Board
__________________
.. code:: shell
tools/cert_create/cert_create -n --rot-key build/stm32mp1/release/rot_key.pem \
--tfw-nvctr 0 \
--ntfw-nvctr 0 \
--key-alg ecdsa --hash-alg sha256 \
--trusted-key-cert build/stm32mp1/release/trusted_key.crt \
--tos-fw <optee_directory>/tee-header_v2.bin \
--tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
--tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
--tos-fw-cert build/stm32mp1/release/tos_fw_content.crt \
--tos-fw-key-cert build/stm32mp1/release/tos_fw_key.crt \
--nt-fw <u-boot_directory>/u-boot-nodtb.bin \
--nt-fw-cert build/stm32mp1/release/nt_fw_content.crt \
--nt-fw-key-cert build/stm32mp1/release/nt_fw_key.crt \
--hw-config <u-boot_directory>/u-boot.dtb \
--fw-config build/stm32mp1/release/fdts/fw-config.dtb \
--stm32mp-cfg-cert build/stm32mp1/release/stm32mp_cfg_cert.crt
tools/fiptool/fiptool create --tos-fw <optee_directory>/tee-header_v2.bin \
--tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
--tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
--nt-fw <u-boot_directory>/u-boot-nodtb.bin \
--hw-config <u-boot_directory>/u-boot.dtb \
--fw-config build/stm32mp1/release/fdts/fw-config.dtb \
--tos-fw-cert build/stm32mp1/release/tos_fw_content.crt \
--tos-fw-key-cert build/stm32mp1/release/tos_fw_key.crt \
--nt-fw-cert build/stm32mp1/release/nt_fw_content.crt \
--nt-fw-key-cert build/stm32mp1/release/nt_fw_key.crt \
--stm32mp-cfg-cert build/stm32mp1/release/stm32mp_cfg_cert.crt \
build/stm32mp1/release/stm32mp1.fip
.. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification
*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*

133
docs/plat/st/stm32mp2.rst Normal file
View file

@ -0,0 +1,133 @@
STM32MP2
========
STM32MP2 is a microprocessor designed by STMicroelectronics
based on Arm Cortex-A35.
For TF-A common configuration of STM32 MPUs, please check
:ref:`STM32 MPUs` page.
STM32MP2 Versions
-----------------
The STM32MP25 series is available in 4 different lines which are pin-to-pin compatible:
- STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 - 3D GPU – AI / NN - LVDS
- STM32MP255: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - H264 - 3D GPU – AI / NN - LVDS
- STM32MP253: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - LVDS
- STM32MP251: Single Cortex-A35 core, Cortex-M33 core - 1x Ethernet
Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
- A Basic + Cortex-A35 @ 1GHz
- C Secure Boot + HW Crypto + Cortex-A35 @ 1GHz
- D Basic + Cortex-A35 @ 1.5GHz
- F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
Memory mapping
--------------
::
0x00000000 +-----------------+
| |
| ... |
| |
0x0E000000 +-----------------+ \
| BL31 | |
+-----------------+ |
| ... | |
0x0E012000 +-----------------+ |
| BL2 DTB | | Embedded SRAM
0x0E016000 +-----------------+ |
| BL2 | |
0x0E040000 +-----------------+ /
| |
| ... |
| |
0x40000000 +-----------------+
| |
| | Devices
| |
0x80000000 +-----------------+ \
| | |
| | | Non-secure RAM (DDR)
| | |
0xFFFFFFFF +-----------------+ /
Build Instructions
------------------
STM32MP2x specific flags
~~~~~~~~~~~~~~~~~~~~~~~~
Dedicated STM32MP2 build flags:
- | ``STM32MP_DDR_FIP_IO_STORAGE``: to store DDR firmware in FIP.
| Default: 1
- | ``STM32MP25``: to select STM32MP25 variant configuration.
| Default: 1
To compile the correct DDR driver, one flag must be set among:
- | ``STM32MP_DDR3_TYPE``: to compile DDR3 driver and DT.
| Default: 0
- | ``STM32MP_DDR4_TYPE``: to compile DDR4 driver and DT.
| Default: 0
- | ``STM32MP_LPDDR4_TYPE``: to compile LpDDR4 driver and DT.
| Default: 0
Boot with FIP
~~~~~~~~~~~~~
You need to build BL2, BL31, BL32 (OP-TEE) and BL33 (U-Boot) before building FIP binary.
U-Boot
______
.. code:: bash
cd <u-boot_directory>
make stm32mp25_defconfig
make DEVICE_TREE=stm32mp257f-ev1 all
OP-TEE
______
.. code:: bash
cd <optee_directory>
make CROSS_COMPILE64=aarch64-none-elf- CROSS_COMPILE32=arm-none-eabi-
ARCH=arm PLATFORM=stm32mp2 \
CFG_EMBED_DTB_SOURCE_FILE=stm32mp257f-ev1.dts
TF-A BL2 & BL31
_______________
To build TF-A BL2 with its STM32 header and BL31 for SD-card boot:
.. code:: bash
make CROSS_COMPILE=aarch64-none-elf- PLAT=stm32mp2 \
STM32MP_DDR4_TYPE=1 SPD=opteed \
DTB_FILE_NAME=stm32mp257f-ev1.dtb STM32MP_SDMMC=1
For other boot devices, you have to replace STM32MP_SDMMC in the previous command
with the desired device flag.
FIP
___
.. code:: bash
make CROSS_COMPILE=aarch64-none-elf- PLAT=stm32mp2 \
STM32MP_DDR4_TYPE=1 SPD=opteed \
DTB_FILE_NAME=stm32mp257f-ev1.dtb \
BL33=<u-boot_directory>/u-boot-nodtb.bin \
BL33_CFG=<u-boot_directory>/u-boot.dtb \
BL32=<optee_directory>/tee-header_v2.bin \
BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin
fip
*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*

78
docs/plat/st/stm32mpus.rst Normal file
View file

@ -0,0 +1,78 @@
STM32 MPUs
==========
STM32 MPUs are microprocessors designed by STMicroelectronics
based on Arm Cortex-A. This page presents the common configuration of STM32
MPUs, more details and dedicated configuration can be found in each STM32 MPU
page (:ref:`STM32MP1` or :ref:`STM32MP2`)
Design
------
The STM32 MPU resets in the ROM code of the Cortex-A.
The primary boot core (core 0) executes the boot sequence while
secondary boot core (core 1) is kept in a holding pen loop.
The ROM code boot sequence loads the TF-A binary image from boot device
to embedded SRAM.
The TF-A image must be properly formatted with a STM32 header structure
for ROM code is able to load this image.
Tool stm32image can be used to prepend this header to the generated TF-A binary.
Boot
~~~~
Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are
inside the FIP binary: BL31 (for Aarch64 platforms), BL32 (OP-TEE), U-Boot
and their respective device tree blobs.
Boot sequence
~~~~~~~~~~~~~
ROM code -> BL2 (compiled with RESET_TO_BL2) -> OP-TEE -> BL33 (U-Boot)
Build Instructions
------------------
Boot media(s) supported by BL2 must be specified in the build command.
Available storage medias are:
- ``STM32MP_SDMMC``
- ``STM32MP_EMMC``
- ``STM32MP_RAW_NAND``
- ``STM32MP_SPI_NAND``
- ``STM32MP_SPI_NOR``
Serial boot devices:
- ``STM32MP_UART_PROGRAMMER``
- ``STM32MP_USB_PROGRAMMER``
Other configuration flags:
- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used.
| Default: stm32mp157c-ev1.dtb
- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP,
| default location (end of the first 128MB) is used when absent
- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup.
| Default: 0 (disabled)
- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2).
| Default: 0 (disabled)
- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate.
| Default: 115200
Populate SD-card
----------------
Boot with FIP
~~~~~~~~~~~~~
The SD-card has to be formatted with GPT.
It should contain at least those partitions:
- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary (BL2)
- fip (GUID 19d5df83-11b0-457b-be2c-7559c13142a5): which contains the FIP binary
Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl.
--------------
*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*

284
docs/plat/stm32mp1.rst
View file

@ -1,280 +1,10 @@
STMicroelectronics STM32MP1
===========================
:orphan:
STM32MP1 is a microprocessor designed by STMicroelectronics
based on Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.
More information can be found on `STM32MP1 Series`_ page.
STMicroelectronics STM32MP1 (old page)
======================================
Please check :ref:`STM32 MPUs` page for generic information about
STMicroelectronics STM32 microprocessors in TF-A, and :ref:`STM32MP1` page
for specificities on STM32MP1x platforms.
STM32MP1 Versions
-----------------
There are 2 variants for STM32MP1: STM32MP13 and STM32MP15
STM32MP13 Versions
~~~~~~~~~~~~~~~~~~
The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible:
- STM32MP131: Single Cortex-A7 core
- STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
- STM32MP135: STM32MP133 + DCMIPP, LTDC
Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
- A Cortex-A7 @ 650 MHz
- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
- D Cortex-A7 @ 900 MHz
- F Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz
STM32MP15 Versions
~~~~~~~~~~~~~~~~~~
The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible:
- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD
- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD
- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
- A Basic + Cortex-A7 @ 650 MHz
- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
- D Basic + Cortex-A7 @ 800 MHz
- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
The `STM32MP1 part number codification`_ page gives more information about part numbers.
Design
------
The STM32MP1 resets in the ROM code of the Cortex-A7.
The primary boot core (core 0) executes the boot sequence while
secondary boot core (core 1) is kept in a holding pen loop.
The ROM code boot sequence loads the TF-A binary image from boot device
to embedded SRAM.
The TF-A image must be properly formatted with a STM32 header structure
for ROM code is able to load this image.
Tool stm32image can be used to prepend this header to the generated TF-A binary.
Boot with FIP
~~~~~~~~~~~~~
The use of FIP is now the recommended way to boot STM32MP1 platform.
Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are
inside the FIP binary: BL32 (SP_min or OP-TEE), U-Boot and their respective
device tree blobs.
Memory mapping
~~~~~~~~~~~~~~
::
0x00000000 +-----------------+
| | ROM
0x00020000 +-----------------+
| |
| ... |
| |
0x2FFC0000 +-----------------+ \
| BL32 DTB | |
0x2FFC5000 +-----------------+ |
| BL32 | |
0x2FFDF000 +-----------------+ |
| ... | |
0x2FFE3000 +-----------------+ |
| BL2 DTB | | Embedded SRAM
0x2FFEA000 +-----------------+ |
| BL2 | |
0x2FFFF000 +-----------------+ |
| SCMI mailbox | |
0x30000000 +-----------------+ /
| |
| ... |
| |
0x40000000 +-----------------+
| |
| | Devices
| |
0xC0000000 +-----------------+ \
| | |
0xC0100000 +-----------------+ |
| BL33 | | Non-secure RAM (DDR)
| ... | |
| | |
0xFFFFFFFF +-----------------+ /
Boot sequence
~~~~~~~~~~~~~
ROM code -> BL2(compiled with RESET_TO_BL2) -> BL32(SP_min)-> BL33(U-Boot)
or if Op-TEE is used:
ROM code -> BL2 (compiled with RESET_TO_BL2) -> OP-TEE -> BL33 (U-Boot)
Build Instructions
------------------
Boot media(s) supported by BL2 must be specified in the build command.
Available storage medias are:
- ``STM32MP_SDMMC``
- ``STM32MP_EMMC``
- ``STM32MP_RAW_NAND``
- ``STM32MP_SPI_NAND``
- ``STM32MP_SPI_NOR``
Serial boot devices:
- ``STM32MP_UART_PROGRAMMER``
- ``STM32MP_USB_PROGRAMMER``
Other configuration flags:
- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used.
| Default: stm32mp157c-ev1.dtb
- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP,
| default location (end of the first 128MB) is used when absent
- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup.
| Default: 0 (disabled)
- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2).
| Default: 0 (disabled)
- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate.
| Default: 115200
- | ``STM32_TF_VERSION``: to manage BL2 monotonic counter.
| Default: 0
- | ``STM32MP13``: to select STM32MP13 variant configuration.
| Default: 0
- | ``STM32MP15``: to select STM32MP15 variant configuration.
| Default: 1
Boot with FIP
~~~~~~~~~~~~~
You need to build BL2, BL32 (SP_min or OP-TEE) and BL33 (U-Boot) before building FIP binary.
U-Boot
______
.. code:: bash
cd <u-boot_directory>
make stm32mp15_trusted_defconfig
make DEVICE_TREE=stm32mp157c-ev1 all
OP-TEE (optional)
_________________
.. code:: bash
cd <optee_directory>
make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 \
CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts
TF-A BL32 (SP_min)
__________________
If you choose not to use OP-TEE, you can use TF-A SP_min.
To build TF-A BL32, and its device tree file:
.. code:: bash
make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-ev1.dtb bl32 dtbs
TF-A BL2
________
To build TF-A BL2 with its STM32 header for SD-card boot:
.. code:: bash
make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
DTB_FILE_NAME=stm32mp157c-ev1.dtb STM32MP_SDMMC=1
For other boot devices, you have to replace STM32MP_SDMMC in the previous command
with the desired device flag.
This BL2 is independent of the BL32 used (SP_min or OP-TEE)
FIP
___
With BL32 SP_min:
.. code:: bash
make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
AARCH32_SP=sp_min \
DTB_FILE_NAME=stm32mp157c-ev1.dtb \
BL33=<u-boot_directory>/u-boot-nodtb.bin \
BL33_CFG=<u-boot_directory>/u-boot.dtb \
fip
With OP-TEE:
.. code:: bash
make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
AARCH32_SP=optee \
DTB_FILE_NAME=stm32mp157c-ev1.dtb \
BL33=<u-boot_directory>/u-boot-nodtb.bin \
BL33_CFG=<u-boot_directory>/u-boot.dtb \
BL32=<optee_directory>/tee-header_v2.bin \
BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin
BL32_EXTRA2=<optee_directory>/tee-pageable_v2.bin
fip
Trusted Boot Board
__________________
.. code:: shell
tools/cert_create/cert_create -n --rot-key "build/stm32mp1/debug/rot_key.pem" \
--tfw-nvctr 0 \
--ntfw-nvctr 0 \
--key-alg ecdsa --hash-alg sha256 \
--trusted-key-cert build/stm32mp1/cert_images/trusted-key-cert.key-crt \
--tos-fw <optee_directory>/tee-header_v2.bin \
--tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
--tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
--tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \
--tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \
--nt-fw <u-boot_directory>/u-boot-nodtb.bin \
--nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \
--nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \
--hw-config <u-boot_directory>/u-boot.dtb \
--fw-config build/stm32mp1/debug/fdts/fw-config.dtb \
--stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt
tools/fiptool/fiptool create --tos-fw <optee_directory>/tee-header_v2.bin \
--tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
--tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
--nt-fw <u-boot_directory>/u-boot-nodtb.bin \
--hw-config <u-boot_directory>/u-boot.dtb \
--fw-config build/stm32mp1/debug/fdts/fw-config.dtb \
--tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \
--tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \
--nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \
--nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \
--stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt stm32mp1.fip
Populate SD-card
----------------
Boot with FIP
~~~~~~~~~~~~~
The SD-card has to be formatted with GPT.
It should contain at least those partitions:
- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary (BL2)
- fip: which contains the FIP binary
Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl.
.. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification
*Copyright (c) 2018-2023, STMicroelectronics - All Rights Reserved*

27
drivers/st/clk/stm32mp_clkfunc.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -248,6 +248,7 @@ const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp)
return cuint;
}
#if defined(IMAGE_BL32)
/*
* Get the secure state for rcc node in device tree.
* @return: true if rcc is configured for secure world access, false if not.
@ -266,6 +267,7 @@ bool fdt_get_rcc_secure_state(void)
return true;
}
#endif
/*
* Get the clock ID of the given node in device tree.
@ -319,6 +321,19 @@ unsigned long fdt_get_uart_clock_freq(uintptr_t instance)
return clk_get_rate((unsigned long)clk_id);
}
/*******************************************************************************
* This function sets the STGEN counter value.
******************************************************************************/
static void stgen_set_counter(unsigned long long counter)
{
#ifdef __aarch64__
mmio_write_64(STGEN_BASE + CNTCV_OFF, counter);
#else
mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter);
mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32));
#endif
}
/*******************************************************************************
* This function configures and restores the STGEN counter depending on the
* connected clock.
@ -337,8 +352,7 @@ void stm32mp_stgen_config(unsigned long rate)
mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
counter = stm32mp_stgen_get_counter() * rate / cntfid0;
mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter);
mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32));
stgen_set_counter(counter);
mmio_write_32(STGEN_BASE + CNTFID_OFF, rate);
mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
@ -353,8 +367,12 @@ void stm32mp_stgen_config(unsigned long rate)
******************************************************************************/
unsigned long long stm32mp_stgen_get_counter(void)
{
#ifdef __aarch64__
return mmio_read_64(STGEN_BASE + CNTCV_OFF);
#else
return (((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) |
mmio_read_32(STGEN_BASE + CNTCVL_OFF));
#endif
}
/*******************************************************************************
@ -371,7 +389,6 @@ void stm32mp_stgen_restore_counter(unsigned long long value,
mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U);
mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt);
mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32));
stgen_set_counter(cnt);
mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
}

8
drivers/st/mmc/stm32_sdmmc2.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved
* Copyright (c) 2018-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -131,6 +131,12 @@
#define SDMMC_FIFO_SIZE 64U
#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
static void stm32_sdmmc2_init(void);
static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd);
static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd);

10
drivers/st/regulator/regulator_fixed.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, STMicroelectronics - All Rights Reserved
* Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,8 +13,8 @@
#include <drivers/st/regulator_fixed.h>
#include <libfdt.h>
#ifndef PLAT_NB_FIXED_REGS
#error "Missing PLAT_NB_FIXED_REGS"
#ifndef PLAT_NB_FIXED_REGUS
#error "Missing PLAT_NB_FIXED_REGUS"
#endif
#define FIXED_NAME_LEN 32
@ -25,7 +25,7 @@ struct fixed_data {
struct regul_description desc;
};
static struct fixed_data data[PLAT_NB_FIXED_REGS];
static struct fixed_data data[PLAT_NB_FIXED_REGUS];
static int fixed_set_state(const struct regul_description *desc, bool state)
{
@ -79,7 +79,7 @@ int fixed_regulator_register(void)
}
count++;
assert(count <= PLAT_NB_FIXED_REGS);
assert(count <= PLAT_NB_FIXED_REGUS);
}

255
drivers/st/uart/aarch64/stm32_console.S Normal file
View file

@ -0,0 +1,255 @@
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm_macros.S>
#include <assert_macros.S>
#include <console_macros.S>
#include <drivers/st/stm32_console.h>
#include <drivers/st/stm32_uart_regs.h>
#define USART_TIMEOUT 0x1000
/*
* "core" functions are low-level implementations that don't require
* writeable memory and are thus safe to call in BL1 crash context.
*/
.globl console_stm32_core_init
.globl console_stm32_core_putc
.globl console_stm32_core_getc
.globl console_stm32_core_flush
.globl console_stm32_putc
.globl console_stm32_flush
/* -----------------------------------------------------------------
* int console_core_init(uintptr_t base_addr,
* unsigned int uart_clk,
* unsigned int baud_rate)
*
* Function to initialize the console without a C Runtime to print
* debug information. This function will be accessed by console_init
* and crash reporting.
*
* In: x0 - console base address
* w1 - Uart clock in Hz
* w2 - Baud rate
* Out: return 1 on success else 0 on error
* Clobber list : x1, x2, x3, x4
* -----------------------------------------------
*/
func console_stm32_core_init
/* Check the input base address */
cbz x0, core_init_fail
#if !defined(IMAGE_BL2)
#if STM32MP_RECONFIGURE_CONSOLE
/* UART clock rate is set to 0 in BL32, skip init in that case */
cbz x1, 1f
#else /* STM32MP_RECONFIGURE_CONSOLE */
/* Skip UART initialization if it is already enabled */
ldr w3, [x0, #USART_CR1]
tst w3, #USART_CR1_UE
b.ne 1f
#endif /* STM32MP_RECONFIGURE_CONSOLE */
#endif /* IMAGE_BL2 */
/* Check baud rate and uart clock for sanity */
cbz w1, core_init_fail
cbz w2, core_init_fail
/* Disable UART */
ldr w3, [x0, #USART_CR1]
mov w4, #USART_CR1_UE
bic w3, w3, w4
str w3, [x0, #USART_CR1]
/* Configure UART */
mov w4, #(USART_CR1_TE)
orr w4, w4, #(USART_CR1_FIFOEN)
orr w3, w3, w4
str w3, [x0, #USART_CR1]
ldr w3, [x0, #USART_CR2]
mov w4, #USART_CR2_STOP
bic w3, w3, w4
str w3, [x0, #USART_CR2]
/* Divisor = (Uart clock + (baudrate / 2)) / baudrate */
lsr w3, w2, #1
add w3, w1, w3
udiv w3, w3, w2
cmp w3, #16
b.hi 2f
/* Oversampling 8 */
/* Divisor = (2 * Uart clock + (baudrate / 2)) / baudrate */
lsr w3, w2, #1
add w3, w3, w1, lsl #1
udiv w3, w3, w2
and w1, w3, #USART_BRR_DIV_FRACTION
lsr w1, w1, #1
bic w3, w3, #USART_BRR_DIV_FRACTION
orr w3, w3, w1
ldr w1, [x0, #USART_CR1]
orr w1, w1, #USART_CR1_OVER8
str w1, [x0, #USART_CR1]
2:
str w3, [x0, #USART_BRR]
/* Enable UART */
ldr w3, [x0, #USART_CR1]
mov w4, #USART_CR1_UE
orr w3, w3, w4
str w3, [x0, #USART_CR1]
/* Check TEACK bit */
mov w2, #USART_TIMEOUT
teack_loop:
subs w2, w2, #1
beq core_init_fail
ldr w3, [x0, #USART_ISR]
tst w3, #USART_ISR_TEACK
beq teack_loop
1:
mov w0, #1
ret
core_init_fail:
mov w0, wzr
ret
endfunc console_stm32_core_init
.globl console_stm32_register
/* -------------------------------------------------------
* int console_stm32_register(uintptr_t baseaddr,
* uint32_t clock, uint32_t baud,
* console_t *console);
* Function to initialize and register a new STM32
* console. Storage passed in for the console struct
* *must* be persistent (i.e. not from the stack).
* In: x0 - UART register base address
* w1 - UART clock in Hz
* w2 - Baud rate
* x3 - pointer to empty console_t struct
* Out: return 1 on success, 0 on error
* Clobber list : x0, x1, x2, x6, x7, x14
* -------------------------------------------------------
*/
func console_stm32_register
mov x7, x30
mov x6, x3
cbz x6, register_fail
str x0, [x6, #CONSOLE_T_BASE]
bl console_stm32_core_init
cbz x0, register_fail
mov x0, x6
mov x30, x7
finish_console_register stm32 putc=1, getc=0, flush=1
register_fail:
ret x7
endfunc console_stm32_register
/* --------------------------------------------------------
* int console_stm32_core_putc(int c, uintptr_t base_addr)
* Function to output a character over the console. It
* returns the character printed on success or -1 on error.
* In : w0 - character to be printed
* x1 - console base address
* Out : return -1 on error else return character.
* Clobber list : x2
* --------------------------------------------------------
*/
func console_stm32_core_putc
#if ENABLE_ASSERTIONS
cmp x1, #0
ASM_ASSERT(ne)
#endif /* ENABLE_ASSERTIONS */
/* Check Transmit Data Register Empty */
txe_loop:
ldr w2, [x1, #USART_ISR]
tst w2, #USART_ISR_TXE
beq txe_loop
str w0, [x1, #USART_TDR]
/* Check transmit complete flag */
tc_loop:
ldr w2, [x1, #USART_ISR]
tst w2, #USART_ISR_TC
beq tc_loop
ret
endfunc console_stm32_core_putc
/* --------------------------------------------------------
* int console_stm32_putc(int c, console_t *console)
* Function to output a character over the console. It
* returns the character printed on success or -1 on error.
* In : w0 - character to be printed
* x1 - pointer to console_t structure
* Out : return -1 on error else return character.
* Clobber list : x2
* --------------------------------------------------------
*/
func console_stm32_putc
#if ENABLE_ASSERTIONS
cmp x1, #0
ASM_ASSERT(ne)
#endif /* ENABLE_ASSERTIONS */
ldr x1, [x1, #CONSOLE_T_BASE]
b console_stm32_core_putc
endfunc console_stm32_putc
/* ---------------------------------------------
* int console_stm32_core_getc(uintptr_t base_addr)
* Function to get a character from the console.
* It returns the character grabbed on success
* or -1 if no character is available.
* In : x0 - console base address
* Out: w0 - character if available, else -1
* Clobber list : x0, x1
* ---------------------------------------------
*/
func console_stm32_core_getc
/* Not supported */
mov w0, #-1
ret
endfunc console_stm32_core_getc
/* ---------------------------------------------
* int console_stm32_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - console base address
* Out : return -1 on error else return 0.
* Clobber list : x0, x1
* ---------------------------------------------
*/
func console_stm32_core_flush
#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif /* ENABLE_ASSERTIONS */
/* Check Transmit Data Register Empty */
txe_loop_3:
ldr w1, [x0, #USART_ISR]
tst w1, #USART_ISR_TXE
beq txe_loop_3
mov w0, #0
ret
endfunc console_stm32_core_flush
/* ---------------------------------------------
* int console_stm32_flush(console_t *console)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - pointer to console_t structure
* Out : return -1 on error else return 0.
* Clobber list : x0, x1
* ---------------------------------------------
*/
func console_stm32_flush
#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif /* ENABLE_ASSERTIONS */
ldr x0, [x0, #CONSOLE_T_BASE]
b console_stm32_core_flush
endfunc console_stm32_flush

6
fdts/stm32mp25-bl2.dtsi Normal file
View file

@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
*/
/omit-if-no-ref/ &usart2_pins_a;

21
fdts/stm32mp25-pinctrl.dtsi Normal file
View file

@ -0,0 +1,21 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
bias-disable;
};
};
};

289
fdts/stm32mp251.dtsi Normal file
View file

@ -0,0 +1,289 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/clock/stm32mp25-clks.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/stm32mp25-resets.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a35";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
};
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <48000000>;
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <64000000>;
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
clk_msi: clk-msi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <16000000>;
};
};
intc: interrupt-controller@4ac00000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
reg = <0x0 0x4ac10000 0x0 0x1000>,
<0x0 0x4ac20000 0x0 0x2000>,
<0x0 0x4ac40000 0x0 0x2000>,
<0x0 0x4ac60000 0x0 0x2000>;
};
timer: timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
always-on;
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges = <0x0 0x0 0x0 0x80000000>;
rifsc: rifsc@42080000 {
compatible = "st,stm32mp25-rifsc";
reg = <0x42080000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
usart2: serial@400e0000 {
compatible = "st,stm32h7-uart";
reg = <0x400e0000 0x400>;
clocks = <&rcc CK_KER_USART2>;
resets = <&rcc USART2_R>;
status = "disabled";
};
};
rcc: rcc@44200000 {
compatible = "st,stm32mp25-rcc";
reg = <0x44200000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pwr: pwr@44210000 {
compatible = "st,stm32mp25-pwr";
reg = <0x44210000 0x400>;
vddio1: vddio1 {
regulator-name = "vddio1";
};
vddio2: vddio2 {
regulator-name = "vddio2";
};
vddio3: vddio3 {
regulator-name = "vddio3";
};
vddio4: vddio4 {
regulator-name = "vddio4";
};
vddio: vddio {
regulator-name = "vddio";
};
};
syscfg: syscon@44230000 {
compatible = "st,stm32mp25-syscfg", "syscon";
reg = <0x44230000 0x10000>;
};
pinctrl: pinctrl@44240000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp257-pinctrl";
ranges = <0 0x44240000 0xa0400>;
pins-are-numbered;
gpioa: gpio@44240000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc CK_BUS_GPIOA>;
st,bank-name = "GPIOA";
status = "disabled";
};
gpiob: gpio@44250000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10000 0x400>;
clocks = <&rcc CK_BUS_GPIOB>;
st,bank-name = "GPIOB";
status = "disabled";
};
gpioc: gpio@44260000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x20000 0x400>;
clocks = <&rcc CK_BUS_GPIOC>;
st,bank-name = "GPIOC";
status = "disabled";
};
gpiod: gpio@44270000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x30000 0x400>;
clocks = <&rcc CK_BUS_GPIOD>;
st,bank-name = "GPIOD";
status = "disabled";
};
gpioe: gpio@44280000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x40000 0x400>;
clocks = <&rcc CK_BUS_GPIOE>;
st,bank-name = "GPIOE";
status = "disabled";
};
gpiof: gpio@44290000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x50000 0x400>;
clocks = <&rcc CK_BUS_GPIOF>;
st,bank-name = "GPIOF";
status = "disabled";
};
gpiog: gpio@442a0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x60000 0x400>;
clocks = <&rcc CK_BUS_GPIOG>;
st,bank-name = "GPIOG";
status = "disabled";
};
gpioh: gpio@442b0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x70000 0x400>;
clocks = <&rcc CK_BUS_GPIOH>;
st,bank-name = "GPIOH";
status = "disabled";
};
gpioi: gpio@442c0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x80000 0x400>;
clocks = <&rcc CK_BUS_GPIOI>;
st,bank-name = "GPIOI";
status = "disabled";
};
gpioj: gpio@442d0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x90000 0x400>;
clocks = <&rcc CK_BUS_GPIOJ>;
st,bank-name = "GPIOJ";
status = "disabled";
};
gpiok: gpio@442e0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xa0000 0x400>;
clocks = <&rcc CK_BUS_GPIOK>;
st,bank-name = "GPIOK";
status = "disabled";
};
};
pinctrl_z: pinctrl@46200000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp257-z-pinctrl";
ranges = <0 0x46200000 0x400>;
pins-are-numbered;
gpioz: gpio@46200000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x400>;
clocks = <&rcc CK_BUS_GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
status = "disabled";
};
};
};
};

6
fdts/stm32mp253.dtsi Normal file
View file

@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp251.dtsi"

9
fdts/stm32mp255.dtsi Normal file
View file

@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp253.dtsi"
/ {
};

9
fdts/stm32mp257.dtsi Normal file
View file

@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp255.dtsi"
/ {
};

36
fdts/stm32mp257f-ev1.dts Normal file
View file

@ -0,0 +1,36 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp257.dtsi"
#include "stm32mp25xf.dtsi"
#include "stm32mp25-pinctrl.dtsi"
#include "stm32mp25xxai-pinctrl.dtsi"
/ {
model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
aliases {
serial0 = &usart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x00000000>;
};
};
&usart2 {
pinctrl-names = "default";
pinctrl-0 = <&usart2_pins_a>;
status = "okay";
};

8
fdts/stm32mp25xc.dtsi Normal file
View file

@ -0,0 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
};

8
fdts/stm32mp25xf.dtsi Normal file
View file

@ -0,0 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
};

81
fdts/stm32mp25xxai-pinctrl.dtsi Normal file
View file

@ -0,0 +1,81 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
&pinctrl {
gpioa: gpio@44240000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@44250000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@44260000 {
status = "okay";
ngpios = <14>;
gpio-ranges = <&pinctrl 0 32 14>;
};
gpiod: gpio@44270000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@44280000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@44290000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@442a0000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@442b0000 {
status = "okay";
ngpios = <12>;
gpio-ranges = <&pinctrl 2 114 12>;
};
gpioi: gpio@442c0000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioj: gpio@442d0000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 144 16>;
};
gpiok: gpio@442e0000 {
status = "okay";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 160 8>;
};
};
&pinctrl_z {
gpioz: gpio@46200000 {
status = "okay";
ngpios = <10>;
gpio-ranges = <&pinctrl_z 0 400 10>;
};
};

69
fdts/stm32mp25xxak-pinctrl.dtsi Normal file
View file

@ -0,0 +1,69 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
&pinctrl {
gpioa: gpio@44240000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@44250000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@44260000 {
status = "okay";
ngpios = <14>;
gpio-ranges = <&pinctrl 0 32 14>;
};
gpiod: gpio@44270000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@44280000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@44290000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@442a0000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@442b0000 {
status = "okay";
ngpios = <12>;
gpio-ranges = <&pinctrl 2 114 12>;
};
gpioi: gpio@442c0000 {
status = "okay";
ngpios = <12>;
gpio-ranges = <&pinctrl 0 128 12>;
};
};
&pinctrl_z {
gpioz: gpio@46200000 {
status = "okay";
ngpios = <10>;
gpio-ranges = <&pinctrl_z 0 400 10>;
};
};

69
fdts/stm32mp25xxal-pinctrl.dtsi Normal file
View file

@ -0,0 +1,69 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
&pinctrl {
gpioa: gpio@44240000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@44250000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@44260000 {
status = "okay";
ngpios = <14>;
gpio-ranges = <&pinctrl 0 32 14>;
};
gpiod: gpio@44270000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@44280000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@44290000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@442a0000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@442b0000 {
status = "okay";
ngpios = <12>;
gpio-ranges = <&pinctrl 2 114 12>;
};
gpioi: gpio@442c0000 {
status = "okay";
ngpios = <12>;
gpio-ranges = <&pinctrl 0 128 12>;
};
};
&pinctrl_z {
gpioz: gpio@46200000 {
status = "okay";
ngpios = <10>;
gpio-ranges = <&pinctrl_z 0 400 10>;
};
};

4986
include/drivers/st/stm32mp25_rcc.h Normal file
View file

File diff suppressed because it is too large Load diff

494
include/dt-bindings/clock/stm32mp25-clks.h Normal file
View file

@ -0,0 +1,494 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP25_CLKS_H_
#define _DT_BINDINGS_STM32MP25_CLKS_H_
/* INTERNAL/EXTERNAL OSCILLATORS */
#define HSI_CK 0
#define HSE_CK 1
#define MSI_CK 2
#define LSI_CK 3
#define LSE_CK 4
#define I2S_CK 5
#define RTC_CK 6
#define SPDIF_CK_SYMB 7
/* PLL CLOCKS */
#define PLL1_CK 8
#define PLL2_CK 9
#define PLL3_CK 10
#define PLL4_CK 11
#define PLL5_CK 12
#define PLL6_CK 13
#define PLL7_CK 14
#define PLL8_CK 15
#define CK_CPU1 16
/* APB DIV CLOCKS */
#define CK_ICN_APB1 17
#define CK_ICN_APB2 18
#define CK_ICN_APB3 19
#define CK_ICN_APB4 20
#define CK_ICN_APBDBG 21
/* GLOBAL TIMER */
#define TIMG1_CK 22
#define TIMG2_CK 23
/* FLEXGEN CLOCKS */
#define CK_ICN_HS_MCU 24
#define CK_ICN_SDMMC 25
#define CK_ICN_DDR 26
#define CK_ICN_DISPLAY 27
#define CK_ICN_HSL 28
#define CK_ICN_NIC 29
#define CK_ICN_VID 30
#define CK_FLEXGEN_07 31
#define CK_FLEXGEN_08 32
#define CK_FLEXGEN_09 33
#define CK_FLEXGEN_10 34
#define CK_FLEXGEN_11 35
#define CK_FLEXGEN_12 36
#define CK_FLEXGEN_13 37
#define CK_FLEXGEN_14 38
#define CK_FLEXGEN_15 39
#define CK_FLEXGEN_16 40
#define CK_FLEXGEN_17 41
#define CK_FLEXGEN_18 42
#define CK_FLEXGEN_19 43
#define CK_FLEXGEN_20 44
#define CK_FLEXGEN_21 45
#define CK_FLEXGEN_22 46
#define CK_FLEXGEN_23 47
#define CK_FLEXGEN_24 48
#define CK_FLEXGEN_25 49
#define CK_FLEXGEN_26 50
#define CK_FLEXGEN_27 51
#define CK_FLEXGEN_28 52
#define CK_FLEXGEN_29 53
#define CK_FLEXGEN_30 54
#define CK_FLEXGEN_31 55
#define CK_FLEXGEN_32 56
#define CK_FLEXGEN_33 57
#define CK_FLEXGEN_34 58
#define CK_FLEXGEN_35 59
#define CK_FLEXGEN_36 60
#define CK_FLEXGEN_37 61
#define CK_FLEXGEN_38 62
#define CK_FLEXGEN_39 63
#define CK_FLEXGEN_40 64
#define CK_FLEXGEN_41 65
#define CK_FLEXGEN_42 66
#define CK_FLEXGEN_43 67
#define CK_FLEXGEN_44 68
#define CK_FLEXGEN_45 69
#define CK_FLEXGEN_46 70
#define CK_FLEXGEN_47 71
#define CK_FLEXGEN_48 72
#define CK_FLEXGEN_49 73
#define CK_FLEXGEN_50 74
#define CK_FLEXGEN_51 75
#define CK_FLEXGEN_52 76
#define CK_FLEXGEN_53 77
#define CK_FLEXGEN_54 78
#define CK_FLEXGEN_55 79
#define CK_FLEXGEN_56 80
#define CK_FLEXGEN_57 81
#define CK_FLEXGEN_58 82
#define CK_FLEXGEN_59 83
#define CK_FLEXGEN_60 84
#define CK_FLEXGEN_61 85
#define CK_FLEXGEN_62 86
#define CK_FLEXGEN_63 87
/* LOW SPEED MCU CLOCK */
#define CK_ICN_LS_MCU 88
#define CK_BUS_STM500 89
#define CK_BUS_FMC 90
#define CK_BUS_GPU 91
#define CK_BUS_ETH1 92
#define CK_BUS_ETH2 93
#define CK_BUS_PCIE 94
#define CK_BUS_DDRPHYC 95
#define CK_BUS_SYSCPU1 96
#define CK_BUS_ETHSW 97
#define CK_BUS_HPDMA1 98
#define CK_BUS_HPDMA2 99
#define CK_BUS_HPDMA3 100
#define CK_BUS_ADC12 101
#define CK_BUS_ADC3 102
#define CK_BUS_IPCC1 103
#define CK_BUS_CCI 104
#define CK_BUS_CRC 105
#define CK_BUS_MDF1 106
#define CK_BUS_OSPIIOM 107
#define CK_BUS_BKPSRAM 108
#define CK_BUS_HASH 109
#define CK_BUS_RNG 110
#define CK_BUS_CRYP1 111
#define CK_BUS_CRYP2 112
#define CK_BUS_SAES 113
#define CK_BUS_PKA 114
#define CK_BUS_GPIOA 115
#define CK_BUS_GPIOB 116
#define CK_BUS_GPIOC 117
#define CK_BUS_GPIOD 118
#define CK_BUS_GPIOE 119
#define CK_BUS_GPIOF 120
#define CK_BUS_GPIOG 121
#define CK_BUS_GPIOH 122
#define CK_BUS_GPIOI 123
#define CK_BUS_GPIOJ 124
#define CK_BUS_GPIOK 125
#define CK_BUS_LPSRAM1 126
#define CK_BUS_LPSRAM2 127
#define CK_BUS_LPSRAM3 128
#define CK_BUS_GPIOZ 129
#define CK_BUS_LPDMA 130
#define CK_BUS_HSEM 131
#define CK_BUS_IPCC2 132
#define CK_BUS_RTC 133
#define CK_BUS_SPI8 134
#define CK_BUS_LPUART1 135
#define CK_BUS_I2C8 136
#define CK_BUS_LPTIM3 137
#define CK_BUS_LPTIM4 138
#define CK_BUS_LPTIM5 139
#define CK_BUS_IWDG5 140
#define CK_BUS_WWDG2 141
#define CK_BUS_I3C4 142
#define CK_BUS_TIM2 143
#define CK_BUS_TIM3 144
#define CK_BUS_TIM4 145
#define CK_BUS_TIM5 146
#define CK_BUS_TIM6 147
#define CK_BUS_TIM7 148
#define CK_BUS_TIM10 149
#define CK_BUS_TIM11 150
#define CK_BUS_TIM12 151
#define CK_BUS_TIM13 152
#define CK_BUS_TIM14 153
#define CK_BUS_LPTIM1 154
#define CK_BUS_LPTIM2 155
#define CK_BUS_SPI2 156
#define CK_BUS_SPI3 157
#define CK_BUS_SPDIFRX 158
#define CK_BUS_USART2 159
#define CK_BUS_USART3 160
#define CK_BUS_UART4 161
#define CK_BUS_UART5 162
#define CK_BUS_I2C1 163
#define CK_BUS_I2C2 164
#define CK_BUS_I2C3 165
#define CK_BUS_I2C4 166
#define CK_BUS_I2C5 167
#define CK_BUS_I2C6 168
#define CK_BUS_I2C7 169
#define CK_BUS_I3C1 170
#define CK_BUS_I3C2 171
#define CK_BUS_I3C3 172
#define CK_BUS_TIM1 173
#define CK_BUS_TIM8 174
#define CK_BUS_TIM15 175
#define CK_BUS_TIM16 176
#define CK_BUS_TIM17 177
#define CK_BUS_TIM20 178
#define CK_BUS_SAI1 179
#define CK_BUS_SAI2 180
#define CK_BUS_SAI3 181
#define CK_BUS_SAI4 182
#define CK_BUS_USART1 183
#define CK_BUS_USART6 184
#define CK_BUS_UART7 185
#define CK_BUS_UART8 186
#define CK_BUS_UART9 187
#define CK_BUS_FDCAN 188
#define CK_BUS_SPI1 189
#define CK_BUS_SPI4 190
#define CK_BUS_SPI5 191
#define CK_BUS_SPI6 192
#define CK_BUS_SPI7 193
#define CK_BUS_BSEC 194
#define CK_BUS_IWDG1 195
#define CK_BUS_IWDG2 196
#define CK_BUS_IWDG3 197
#define CK_BUS_IWDG4 198
#define CK_BUS_WWDG1 199
#define CK_BUS_VREF 200
#define CK_BUS_DTS 201
#define CK_BUS_SERC 202
#define CK_BUS_HDP 203
#define CK_BUS_IS2M 204
#define CK_BUS_DSI 205
#define CK_BUS_LTDC 206
#define CK_BUS_CSI 207
#define CK_BUS_DCMIPP 208
#define CK_BUS_DDRC 209
#define CK_BUS_DDRCFG 210
#define CK_BUS_GICV2M 211
#define CK_BUS_USBTC 212
#define CK_BUS_BUSPERFM 213
#define CK_BUS_USB3PCIEPHY 214
#define CK_BUS_STGEN 215
#define CK_BUS_VDEC 216
#define CK_BUS_VENC 217
#define CK_SYSDBG 218
#define CK_KER_TIM2 219
#define CK_KER_TIM3 220
#define CK_KER_TIM4 221
#define CK_KER_TIM5 222
#define CK_KER_TIM6 223
#define CK_KER_TIM7 224
#define CK_KER_TIM10 225
#define CK_KER_TIM11 226
#define CK_KER_TIM12 227
#define CK_KER_TIM13 228
#define CK_KER_TIM14 229
#define CK_KER_TIM1 230
#define CK_KER_TIM8 231
#define CK_KER_TIM15 232
#define CK_KER_TIM16 233
#define CK_KER_TIM17 234
#define CK_KER_TIM20 235
#define CK_BUS_SYSRAM 236
#define CK_BUS_VDERAM 237
#define CK_BUS_RETRAM 238
#define CK_BUS_OSPI1 239
#define CK_BUS_OSPI2 240
#define CK_BUS_OTFD1 241
#define CK_BUS_OTFD2 242
#define CK_BUS_SRAM1 243
#define CK_BUS_SRAM2 244
#define CK_BUS_SDMMC1 245
#define CK_BUS_SDMMC2 246
#define CK_BUS_SDMMC3 247
#define CK_BUS_DDR 248
#define CK_BUS_RISAF4 249
#define CK_BUS_USB2OHCI 250
#define CK_BUS_USB2EHCI 251
#define CK_BUS_USB3DRD 252
#define CK_KER_LPTIM1 253
#define CK_KER_LPTIM2 254
#define CK_KER_USART2 255
#define CK_KER_UART4 256
#define CK_KER_USART3 257
#define CK_KER_UART5 258
#define CK_KER_SPI2 259
#define CK_KER_SPI3 260
#define CK_KER_SPDIFRX 261
#define CK_KER_I2C1 262
#define CK_KER_I2C2 263
#define CK_KER_I3C1 264
#define CK_KER_I3C2 265
#define CK_KER_I2C3 266
#define CK_KER_I2C5 267
#define CK_KER_I3C3 268
#define CK_KER_I2C4 269
#define CK_KER_I2C6 270
#define CK_KER_I2C7 271
#define CK_KER_SPI1 272
#define CK_KER_SPI4 273
#define CK_KER_SPI5 274
#define CK_KER_SPI6 275
#define CK_KER_SPI7 276
#define CK_KER_USART1 277
#define CK_KER_USART6 278
#define CK_KER_UART7 279
#define CK_KER_UART8 280
#define CK_KER_UART9 281
#define CK_KER_MDF1 282
#define CK_KER_SAI1 283
#define CK_KER_SAI2 284
#define CK_KER_SAI3 285
#define CK_KER_SAI4 286
#define CK_KER_FDCAN 287
#define CK_KER_DSIBLANE 288
#define CK_KER_DSIPHY 289
#define CK_KER_CSI 290
#define CK_KER_CSITXESC 291
#define CK_KER_CSIPHY 292
#define CK_KER_LVDSPHY 293
#define CK_KER_STGEN 294
#define CK_KER_USB3PCIEPHY 295
#define CK_KER_USB2PHY2EN 296
#define CK_KER_I3C4 297
#define CK_KER_SPI8 298
#define CK_KER_I2C8 299
#define CK_KER_LPUART1 300
#define CK_KER_LPTIM3 301
#define CK_KER_LPTIM4 302
#define CK_KER_LPTIM5 303
#define CK_KER_TSDBG 304
#define CK_KER_TPIU 305
#define CK_BUS_ETR 306
#define CK_BUS_SYSATB 307
#define CK_KER_ADC12 308
#define CK_KER_ADC3 309
#define CK_KER_OSPI1 310
#define CK_KER_OSPI2 311
#define CK_KER_FMC 312
#define CK_KER_SDMMC1 313
#define CK_KER_SDMMC2 314
#define CK_KER_SDMMC3 315
#define CK_KER_ETH1 316
#define CK_KER_ETH2 317
#define CK_KER_ETH1PTP 318
#define CK_KER_ETH2PTP 319
#define CK_KER_USB2PHY1 320
#define CK_KER_USB2PHY2 321
#define CK_KER_ETHSW 322
#define CK_KER_ETHSWREF 323
#define CK_MCO1 324
#define CK_MCO2 325
#define CK_KER_DTS 326
#define CK_ETH1_RX 327
#define CK_ETH1_TX 328
#define CK_ETH1_MAC 329
#define CK_ETH2_RX 330
#define CK_ETH2_TX 331
#define CK_ETH2_MAC 332
#define CK_ETH1_STP 333
#define CK_ETH2_STP 334
#define CK_KER_USBTC 335
#define CK_BUS_ADF1 336
#define CK_KER_ADF1 337
#define CK_BUS_LVDS 338
#define CK_KER_LTDC 339
#define CK_KER_GPU 340
#define CK_BUS_ETHSWACMCFG 341
#define CK_BUS_ETHSWACMMSG 342
#define HSE_DIV2_CK 343
#define STM32MP25_LAST_CLK 344
#define CK_SCMI_ICN_HS_MCU 0
#define CK_SCMI_ICN_SDMMC 1
#define CK_SCMI_ICN_DDR 2
#define CK_SCMI_ICN_DISPLAY 3
#define CK_SCMI_ICN_HSL 4
#define CK_SCMI_ICN_NIC 5
#define CK_SCMI_ICN_VID 6
#define CK_SCMI_FLEXGEN_07 7
#define CK_SCMI_FLEXGEN_08 8
#define CK_SCMI_FLEXGEN_09 9
#define CK_SCMI_FLEXGEN_10 10
#define CK_SCMI_FLEXGEN_11 11
#define CK_SCMI_FLEXGEN_12 12
#define CK_SCMI_FLEXGEN_13 13
#define CK_SCMI_FLEXGEN_14 14
#define CK_SCMI_FLEXGEN_15 15
#define CK_SCMI_FLEXGEN_16 16
#define CK_SCMI_FLEXGEN_17 17
#define CK_SCMI_FLEXGEN_18 18
#define CK_SCMI_FLEXGEN_19 19
#define CK_SCMI_FLEXGEN_20 20
#define CK_SCMI_FLEXGEN_21 21
#define CK_SCMI_FLEXGEN_22 22
#define CK_SCMI_FLEXGEN_23 23
#define CK_SCMI_FLEXGEN_24 24
#define CK_SCMI_FLEXGEN_25 25
#define CK_SCMI_FLEXGEN_26 26
#define CK_SCMI_FLEXGEN_27 27
#define CK_SCMI_FLEXGEN_28 28
#define CK_SCMI_FLEXGEN_29 29
#define CK_SCMI_FLEXGEN_30 30
#define CK_SCMI_FLEXGEN_31 31
#define CK_SCMI_FLEXGEN_32 32
#define CK_SCMI_FLEXGEN_33 33
#define CK_SCMI_FLEXGEN_34 34
#define CK_SCMI_FLEXGEN_35 35
#define CK_SCMI_FLEXGEN_36 36
#define CK_SCMI_FLEXGEN_37 37
#define CK_SCMI_FLEXGEN_38 38
#define CK_SCMI_FLEXGEN_39 39
#define CK_SCMI_FLEXGEN_40 40
#define CK_SCMI_FLEXGEN_41 41
#define CK_SCMI_FLEXGEN_42 42
#define CK_SCMI_FLEXGEN_43 43
#define CK_SCMI_FLEXGEN_44 44
#define CK_SCMI_FLEXGEN_45 45
#define CK_SCMI_FLEXGEN_46 46
#define CK_SCMI_FLEXGEN_47 47
#define CK_SCMI_FLEXGEN_48 48
#define CK_SCMI_FLEXGEN_49 49
#define CK_SCMI_FLEXGEN_50 50
#define CK_SCMI_FLEXGEN_51 51
#define CK_SCMI_FLEXGEN_52 52
#define CK_SCMI_FLEXGEN_53 53
#define CK_SCMI_FLEXGEN_54 54
#define CK_SCMI_FLEXGEN_55 55
#define CK_SCMI_FLEXGEN_56 56
#define CK_SCMI_FLEXGEN_57 57
#define CK_SCMI_FLEXGEN_58 58
#define CK_SCMI_FLEXGEN_59 59
#define CK_SCMI_FLEXGEN_60 60
#define CK_SCMI_FLEXGEN_61 61
#define CK_SCMI_FLEXGEN_62 62
#define CK_SCMI_FLEXGEN_63 63
#define CK_SCMI_ICN_LS_MCU 64
#define CK_SCMI_HSE 65
#define CK_SCMI_LSE 66
#define CK_SCMI_HSI 67
#define CK_SCMI_LSI 68
#define CK_SCMI_MSI 69
#define CK_SCMI_HSE_DIV2 70
#define CK_SCMI_CPU1 71
#define CK_SCMI_SYSCPU1 72
#define CK_SCMI_PLL2 73
#define CK_SCMI_PLL3 74
#define CK_SCMI_RTC 75
#define CK_SCMI_RTCCK 76
#define CK_SCMI_ICN_APB1 77
#define CK_SCMI_ICN_APB2 78
#define CK_SCMI_ICN_APB3 79
#define CK_SCMI_ICN_APB4 80
#define CK_SCMI_ICN_APBDBG 81
#define CK_SCMI_TIMG1 82
#define CK_SCMI_TIMG2 83
#define CK_SCMI_BKPSRAM 84
#define CK_SCMI_BSEC 85
#define CK_SCMI_BUSPERFM 86
#define CK_SCMI_ETR 87
#define CK_SCMI_FMC 88
#define CK_SCMI_GPIOA 89
#define CK_SCMI_GPIOB 90
#define CK_SCMI_GPIOC 91
#define CK_SCMI_GPIOD 92
#define CK_SCMI_GPIOE 93
#define CK_SCMI_GPIOF 94
#define CK_SCMI_GPIOG 95
#define CK_SCMI_GPIOH 96
#define CK_SCMI_GPIOI 97
#define CK_SCMI_GPIOJ 98
#define CK_SCMI_GPIOK 99
#define CK_SCMI_GPIOZ 100
#define CK_SCMI_HPDMA1 101
#define CK_SCMI_HPDMA2 102
#define CK_SCMI_HPDMA3 103
#define CK_SCMI_HSEM 104
#define CK_SCMI_IPCC1 105
#define CK_SCMI_IPCC2 106
#define CK_SCMI_LPDMA 107
#define CK_SCMI_RETRAM 108
#define CK_SCMI_SRAM1 109
#define CK_SCMI_SRAM2 110
#define CK_SCMI_LPSRAM1 111
#define CK_SCMI_LPSRAM2 112
#define CK_SCMI_LPSRAM3 113
#define CK_SCMI_VDERAM 114
#define CK_SCMI_SYSRAM 115
#define CK_SCMI_OSPI1 116
#define CK_SCMI_OSPI2 117
#define CK_SCMI_TPIU 118
#define CK_SCMI_SYSDBG 119
#define CK_SCMI_SYSATB 120
#define CK_SCMI_TSDBG 121
#define CK_SCMI_STM500 122
#endif /* _DT_BINDINGS_STM32MP25_CLKS_H_ */

226
include/dt-bindings/clock/stm32mp25-clksrc.h Normal file
View file

@ -0,0 +1,226 @@
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
*/
#ifndef _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_
#define _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_
#define CMD_DIV 0
#define CMD_MUX 1
#define CMD_CLK 2
#define CMD_FLEXGEN 3
#define CMD_ADDR_BIT 0x80000000
#define CMD_SHIFT 26
#define CMD_MASK 0xFC000000
#define CMD_DATA_MASK 0x03FFFFFF
#define DIV_ID_SHIFT 8
#define DIV_ID_MASK 0x0000FF00
#define DIV_DIVN_SHIFT 0
#define DIV_DIVN_MASK 0x000000FF
#define MUX_ID_SHIFT 4
#define MUX_ID_MASK 0x00000FF0
#define MUX_SEL_SHIFT 0
#define MUX_SEL_MASK 0x0000000F
/* CLK define */
#define CLK_ON_MASK BIT(21)
#define CLK_ON_SHIFT 21
#define CLK_ID_MASK GENMASK_32(20, 12)
#define CLK_ID_SHIFT 12
#define CLK_NO_DIV_MASK 0x0000080
#define CLK_DIV_MASK GENMASK_32(10, 5)
#define CLK_DIV_SHIFT 5
#define CLK_NO_SEL_MASK 0x00000010
#define CLK_SEL_MASK GENMASK_32(3, 0)
#define CLK_SEL_SHIFT 0
#define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\
((state) << CLK_ON_SHIFT) |\
((clk_id) << CLK_ID_SHIFT) |\
((div) << CLK_DIV_SHIFT) |\
((sel) << CLK_SEL_SHIFT))
#define CLK_OFF 0
#define CLK_ON 1
#define CLK_NODIV 0x00000040
#define CLK_NOMUX 0x00000010
/* Flexgen define */
#define FLEX_ID_SHIFT 13
#define FLEX_SEL_SHIFT 9
#define FLEX_PDIV_SHIFT 6
#define FLEX_FDIV_SHIFT 0
#define FLEX_ID_MASK GENMASK_32(18, 13)
#define FLEX_SEL_MASK GENMASK_32(12, 9)
#define FLEX_PDIV_MASK GENMASK_32(8, 6)
#define FLEX_FDIV_MASK GENMASK_32(5, 0)
#define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\
((div_id) << DIV_ID_SHIFT |\
(div)))
#define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\
((mux_id) << MUX_ID_SHIFT |\
(sel)))
#define CLK_ADDR_SHIFT 16
#define CLK_ADDR_MASK 0x7FFF0000
#define CLK_ADDR_VAL_MASK 0xFFFF
#define DIV_LSMCU 0
#define DIV_APB1 1
#define DIV_APB2 2
#define DIV_APB3 3
#define DIV_APB4 4
#define DIV_APBDBG 5
#define DIV_RTC 6
#define DIV_NB 7
#define MUX_MUXSEL0 0
#define MUX_MUXSEL1 1
#define MUX_MUXSEL2 2
#define MUX_MUXSEL3 3
#define MUX_MUXSEL4 4
#define MUX_MUXSEL5 5
#define MUX_MUXSEL6 6
#define MUX_MUXSEL7 7
#define MUX_XBARSEL 8
#define MUX_RTC 9
#define MUX_MCO1 10
#define MUX_MCO2 11
#define MUX_ADC12 12
#define MUX_ADC3 13
#define MUX_USB2PHY1 14
#define MUX_USB2PHY2 15
#define MUX_USB3PCIEPHY 16
#define MUX_DSIBLANE 17
#define MUX_DSIPHY 18
#define MUX_LVDSPHY 19
#define MUX_DTS 20
#define MUX_CPU1 21
#define MUX_D3PER 22
#define MUX_NB 23
#define MUXSEL_HSI 0
#define MUXSEL_HSE 1
#define MUXSEL_MSI 2
/* KERNEL source clocks */
#define MUX_RTC_DISABLED 0x0
#define MUX_RTC_LSE 0x1
#define MUX_RTC_LSI 0x2
#define MUX_RTC_HSE 0x3
#define MUX_MCO1_FLEX61 0x0
#define MUX_MCO1_OBSER0 0x1
#define MUX_MCO2_FLEX62 0x0
#define MUX_MCO2_OBSER1 0x1
#define MUX_ADC12_FLEX46 0x0
#define MUX_ADC12_LSMCU 0x1
#define MUX_ADC3_FLEX47 0x0
#define MUX_ADC3_LSMCU 0x1
#define MUX_ADC3_FLEX46 0x2
#define MUX_USB2PHY1_FLEX57 0x0
#define MUX_USB2PHY1_HSE 0x1
#define MUX_USB2PHY2_FLEX58 0x0
#define MUX_USB2PHY2_HSE 0x1
#define MUX_USB3PCIEPHY_FLEX34 0x0
#define MUX_USB3PCIEPHY_HSE 0x1
#define MUX_DSIBLANE_FLEX28 0x0
#define MUX_DSIBLANE_FLEX27 0x1
#define MUX_DSIPHY_FLEX28 0x0
#define MUX_DSIPHY_HSE 0x1
#define MUX_LVDSPHY_FLEX32 0x0
#define MUX_LVDSPHY_HSE 0x1
#define MUX_DTS_HSI 0x0
#define MUX_DTS_HSE 0x1
#define MUX_DTS_MSI 0x2
#define MUX_D3PER_MSI 0x0
#define MUX_D3PER_LSI 0x1
#define MUX_D3PER_LSE 0x2
/* PLLs source clocks */
#define PLL_SRC_HSI 0x0
#define PLL_SRC_HSE 0x1
#define PLL_SRC_MSI 0x2
#define PLL_SRC_DISABLED 0x3
/* XBAR source clocks */
#define XBAR_SRC_PLL4 0x0
#define XBAR_SRC_PLL5 0x1
#define XBAR_SRC_PLL6 0x2
#define XBAR_SRC_PLL7 0x3
#define XBAR_SRC_PLL8 0x4
#define XBAR_SRC_HSI 0x5
#define XBAR_SRC_HSE 0x6
#define XBAR_SRC_MSI 0x7
#define XBAR_SRC_HSI_KER 0x8
#define XBAR_SRC_HSE_KER 0x9
#define XBAR_SRC_MSI_KER 0xA
#define XBAR_SRC_SPDIF_SYMB 0xB
#define XBAR_SRC_I2S 0xC
#define XBAR_SRC_LSI 0xD
#define XBAR_SRC_LSE 0xE
/*
* Configure a XBAR channel with its clock source
* channel_nb: XBAR channel number from 0 to 63
* channel_src: one of the 15 previous XBAR source clocks defines
* channel_prediv: value of the PREDIV in channel RCC_PREDIVxCFGR register
* can be either 1, 2, 4 or 1024
* channel_findiv: value of the FINDIV in channel RCC_FINDIVxCFGR register
* from 1 to 64
*/
#define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\
((ch) << FLEX_ID_SHIFT) |\
((sel) << FLEX_SEL_SHIFT) |\
((pdiv) << FLEX_PDIV_SHIFT) |\
((fdiv) << FLEX_FDIV_SHIFT))
/* Register addresses of MCO1 & MCO2 */
#define MCO1 0x494
#define MCO2 0x498
#define MCO_OFF 0
#define MCO_ON 1
#define MCO_STATUS_SHIFT 8
#define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\
((addr) << CLK_ADDR_SHIFT) |\
((status) << MCO_STATUS_SHIFT) |\
(sel))
/* define for st,pll /csg */
#define SSCG_MODE_CENTER_SPREAD 0
#define SSCG_MODE_DOWN_SPREAD 1
/* define for st,drive */
#define LSEDRV_LOWEST 0
#define LSEDRV_MEDIUM_LOW 1
#define LSEDRV_MEDIUM_HIGH 2
#define LSEDRV_HIGHEST 3
#endif /* _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ */

164
include/dt-bindings/reset/stm32mp25-resets.h Normal file
View file

@ -0,0 +1,164 @@
/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP25_RESET_H_
#define _DT_BINDINGS_STM32MP25_RESET_H_
#define SYS_R 8192
#define C1_R 8224
#define C1P1POR_R 8256
#define C1P1_R 8257
#define C2_R 8288
#define C2_HOLDBOOT_R 8608
#define C1_HOLDBOOT_R 8609
#define VSW_R 8703
#define C1MS_R 8808
#define IWDG2_KER_R 9074
#define IWDG4_KER_R 9202
#define C3_R 9312
#define DDRCP_R 9856
#define DDRCAPB_R 9888
#define DDRPHYCAPB_R 9920
#define DDRCFG_R 9984
#define DDR_R 10016
#define OSPI1_R 10400
#define OSPI1DLL_R 10416
#define OSPI2_R 10432
#define OSPI2DLL_R 10448
#define FMC_R 10464
#define DBG_R 10508
#define GPIOA_R 10592
#define GPIOB_R 10624
#define GPIOC_R 10656
#define GPIOD_R 10688
#define GPIOE_R 10720
#define GPIOF_R 10752
#define GPIOG_R 10784
#define GPIOH_R 10816
#define GPIOI_R 10848
#define GPIOJ_R 10880
#define GPIOK_R 10912
#define GPIOZ_R 10944
#define HPDMA1_R 10976
#define HPDMA2_R 11008
#define HPDMA3_R 11040
#define LPDMA_R 11072
#define HSEM_R 11104
#define IPCC1_R 11136
#define IPCC2_R 11168
#define IS2M_R 11360
#define SSMOD_R 11392
#define TIM1_R 14336
#define TIM2_R 14368
#define TIM3_R 14400
#define TIM4_R 14432
#define TIM5_R 14464
#define TIM6_R 14496
#define TIM7_R 14528
#define TIM8_R 14560
#define TIM10_R 14592
#define TIM11_R 14624
#define TIM12_R 14656
#define TIM13_R 14688
#define TIM14_R 14720
#define TIM15_R 14752
#define TIM16_R 14784
#define TIM17_R 14816
#define TIM20_R 14848
#define LPTIM1_R 14880
#define LPTIM2_R 14912
#define LPTIM3_R 14944
#define LPTIM4_R 14976
#define LPTIM5_R 15008
#define SPI1_R 15040
#define SPI2_R 15072
#define SPI3_R 15104
#define SPI4_R 15136
#define SPI5_R 15168
#define SPI6_R 15200
#define SPI7_R 15232
#define SPI8_R 15264
#define SPDIFRX_R 15296
#define USART1_R 15328
#define USART2_R 15360
#define USART3_R 15392
#define UART4_R 15424
#define UART5_R 15456
#define USART6_R 15488
#define UART7_R 15520
#define UART8_R 15552
#define UART9_R 15584
#define LPUART1_R 15616
#define I2C1_R 15648
#define I2C2_R 15680
#define I2C3_R 15712
#define I2C4_R 15744
#define I2C5_R 15776
#define I2C6_R 15808
#define I2C7_R 15840
#define I2C8_R 15872
#define SAI1_R 15904
#define SAI2_R 15936
#define SAI3_R 15968
#define SAI4_R 16000
#define MDF1_R 16064
#define MDF2_R 16096
#define FDCAN_R 16128
#define HDP_R 16160
#define ADC12_R 16192
#define ADC3_R 16224
#define ETH1_R 16256
#define ETH2_R 16288
#define USB2_R 16352
#define USB2PHY1_R 16384
#define USB2PHY2_R 16416
#define USB3DRD_R 16448
#define USB3PCIEPHY_R 16480
#define PCIE_R 16512
#define USBTC_R 16544
#define ETHSW_R 16576
#define SDMMC1_R 16768
#define SDMMC1DLL_R 16784
#define SDMMC2_R 16800
#define SDMMC2DLL_R 16816
#define SDMMC3_R 16832
#define SDMMC3DLL_R 16848
#define GPU_R 16864
#define LTDC_R 16896
#define DSI_R 16928
#define LVDS_R 17024
#define CSI_R 17088
#define DCMIPP_R 17120
#define CCI_R 17152
#define VDEC_R 17184
#define VENC_R 17216
#define RNG_R 17280
#define PKA_R 17312
#define SAES_R 17344
#define HASH_R 17376
#define CRYP1_R 17408
#define CRYP2_R 17440
#define WWDG1_R 17632
#define WWDG2_R 17664
#define BUSPERFM_R 17696
#define VREF_R 17728
#define DTS_R 17760
#define CRC_R 17824
#define SERC_R 17856
#define OSPIIOM_R 17888
#define I3C1_R 17984
#define I3C2_R 18016
#define I3C3_R 18048
#define I3C4_R 18080
#define RST_SCMI_C1_R 0
#define RST_SCMI_C2_R 1
#define RST_SCMI_C1_HOLDBOOT_R 2
#define RST_SCMI_C2_HOLDBOOT_R 3
#define RST_SCMI_FMC 4
#define RST_SCMI_PCIE 5
#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */

18
plat/st/common/bl2_io_storage.c
View file

@ -191,13 +191,13 @@ static void print_boot_device(boot_api_context_t *boot_context)
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
INFO("Using EMMC\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
INFO("Using QSPI NOR\n");
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
INFO("Using SPI NOR\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
INFO("Using FMC NAND\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
INFO("Using SPI NAND\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
@ -433,7 +433,7 @@ void stm32mp_io_setup(void)
break;
#endif
#if STM32MP_SPI_NOR
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
dmbsy();
boot_spi_nor(boot_context);
break;
@ -445,7 +445,7 @@ void stm32mp_io_setup(void)
break;
#endif
#if STM32MP_SPI_NAND
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
dmbsy();
boot_spi_nand(boot_context);
break;
@ -530,14 +530,14 @@ int bl2_plat_handle_pre_image_load(unsigned int image_id)
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
#endif
#if STM32MP_SPI_NAND
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
#endif
image_block_spec.offset = STM32MP_NAND_FIP_OFFSET;
break;
#endif
#if STM32MP_SPI_NOR
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
/*
* With FWU Multi Bank feature enabled, the selection of
* the image to boot will be done by fwu_init calling the
@ -694,7 +694,7 @@ void plat_fwu_set_images_source(const struct fwu_metadata *metadata)
break;
#endif
#if STM32MP_SPI_NOR
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
if (guidcmp(img_uuid, &STM32MP_NOR_FIP_A_GUID) == 0) {
image_spec->offset = STM32MP_NOR_FIP_A_OFFSET;
} else if (guidcmp(img_uuid, &STM32MP_NOR_FIP_B_GUID) == 0) {
@ -747,7 +747,7 @@ static int plat_set_image_source(unsigned int image_id,
#endif
#if STM32MP_SPI_NOR
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
if (image_id == FWU_METADATA_IMAGE_ID) {
spec->offset = STM32MP_NOR_METADATA1_OFFSET;
} else {

1
plat/st/common/common.mk
View file

@ -146,6 +146,7 @@ BL2_SOURCES += $(ZLIB_SOURCES)
BL2_SOURCES += drivers/io/io_fip.c \
plat/st/common/bl2_io_storage.c \
plat/st/common/plat_image_load.c \
plat/st/common/stm32mp_fconf_io.c
BL2_SOURCES += drivers/io/io_block.c \

3
plat/st/common/include/stm32mp_common.h
View file

@ -14,6 +14,9 @@
#define JEDEC_ST_BKID U(0x0)
#define JEDEC_ST_MFID U(0x20)
/* FWU configuration (max supported value is 15) */
#define FWU_MAX_TRIAL_REBOOT U(3)
/* Functions to save and get boot context address given by ROM code */
void stm32mp_save_boot_ctx_address(uintptr_t address);
uintptr_t stm32mp_get_boot_ctx_address(void);

51
plat/st/common/include/stm32mp_io_storage.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
* Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,6 +10,55 @@
#include <drivers/io/io_storage.h>
/*******************************************************************************
* STM32MP1 RAW partition offset for devices without GPT
******************************************************************************/
#define STM32MP_EMMC_BOOT_FIP_OFFSET U(0x00040000)
#if PSA_FWU_SUPPORT
#define STM32MP_NOR_METADATA1_OFFSET U(0x00080000)
#define STM32MP_NOR_METADATA2_OFFSET U(0x000C0000)
#define STM32MP_NOR_FIP_A_OFFSET U(0x00100000)
#define STM32MP_NOR_FIP_A_GUID (const struct efi_guid)EFI_GUID(0x4fd84c93, \
0x54ef, 0x463f, 0xa7, 0xef, 0xae, 0x25, 0xff,\
0x88, 0x70, 0x87)
#define STM32MP_NOR_FIP_B_OFFSET U(0x00500000)
#define STM32MP_NOR_FIP_B_GUID (const struct efi_guid)EFI_GUID(0x09c54952, \
0xd5bf, 0x45af, 0xac, 0xee, 0x33, 0x53, 0x03,\
0x76, 0x6f, 0xb3)
#define STM32MP_NAND_METADATA1_OFFSET U(0x00100000)
#define STM32MP_NAND_METADATA2_OFFSET U(0x00180000)
#define STM32MP_NAND_FIP_A_OFFSET U(0x00200000)
#define STM32MP_NAND_FIP_A_GUID (const struct efi_guid)EFI_GUID(0x4fd84c93, \
0x54ef, 0x463f, 0xa7, 0xef, 0xae, 0x25, 0xff,\
0x88, 0x70, 0x87)
#define STM32MP_NAND_FIP_B_OFFSET U(0x00A00000)
#define STM32MP_NAND_FIP_B_GUID (const struct efi_guid)EFI_GUID(0x09c54952, \
0xd5bf, 0x45af, 0xac, 0xee, 0x33, 0x53, 0x03,\
0x76, 0x6f, 0xb3)
#define STM32MP_NAND_FIP_B_MAX_OFFSET U(0x01200000)
#else /* PSA_FWU_SUPPORT */
#ifndef STM32MP_NOR_FIP_OFFSET
#define STM32MP_NOR_FIP_OFFSET U(0x00080000)
#endif
#ifndef STM32MP_NAND_FIP_OFFSET
#define STM32MP_NAND_FIP_OFFSET U(0x00200000)
#endif
#endif /* PSA_FWU_SUPPORT */
/*
* Only used for MTD devices that need some backup blocks.
* Must define a maximum size for a partition.
*/
#define PLATFORM_MTD_MAX_PART_SIZE U(0x00400000)
#define FIP_IMAGE_NAME "fip"
#define METADATA_PART_1 "metadata1"
#define METADATA_PART_2 "metadata2"
/* IO devices handle */
extern uintptr_t storage_dev_handle;
extern uintptr_t fip_dev_handle;

2
plat/st/stm32mp1/plat_image_load.c → plat/st/common/plat_image_load.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

4
plat/st/common/stm32mp_common.c
View file

@ -113,7 +113,11 @@ bool stm32mp_lock_available(void)
const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT;
/* The spinlocks are used only when MMU and data cache are enabled */
#ifdef __aarch64__
return (read_sctlr_el3() & c_m_bits) == c_m_bits;
#else
return (read_sctlr() & c_m_bits) == c_m_bits;
#endif
}
int stm32mp_map_ddr_non_cacheable(void)

6
plat/st/stm32mp1/include/boot_api.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -47,7 +47,7 @@
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC 0x3U
/* Boot occurred on QSPI NOR */
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI 0x4U
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI 0x4U
/* Boot occurred on UART */
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART 0x5U
@ -56,7 +56,7 @@
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB 0x6U
/* Boot occurred on QSPI NAND */
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI 0x7U
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI 0x7U
/**
* @brief Possible value of boot context field 'EmmcXferStatus'

6
plat/st/stm32mp1/include/platform_def.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -25,10 +25,6 @@
#define PLATFORM_STACK_SIZE 0xC00
#endif
#define FIP_IMAGE_NAME "fip"
#define METADATA_PART_1 "metadata1"
#define METADATA_PART_2 "metadata2"
#define STM32MP_PRIMARY_CPU U(0x0)
#define STM32MP_SECONDARY_CPU U(0x1)

2
plat/st/stm32mp1/platform.mk
View file

@ -277,8 +277,6 @@ endif
BL2_SOURCES += drivers/st/ddr/stm32mp1_ddr.c \
drivers/st/ddr/stm32mp1_ram.c
BL2_SOURCES += plat/st/stm32mp1/plat_image_load.c
ifeq ($(AARCH32_SP),sp_min)
# Create DTB file for BL32
${BUILD_PLAT}/fdts/%-bl32.dts: fdts/%.dts fdts/${BL32_DTSI} | ${BUILD_PLAT} fdt_dirs

12
plat/st/stm32mp1/stm32mp1_def.h
View file

@ -195,6 +195,7 @@ enum ddr_type {
SRAM1_SIZE - \
PLATFORM_MTD_MAX_PAGE_SIZE)
#endif
/*******************************************************************************
* STM32MP1 device/io map related constants (used for MMU)
******************************************************************************/
@ -416,12 +417,6 @@ enum ddr_type {
#define STM32MP_SDMMC2_BASE U(0x58007000)
#define STM32MP_SDMMC3_BASE U(0x48004000)
#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
/*******************************************************************************
* STM32MP1 BSEC / OTP
******************************************************************************/
@ -540,9 +535,6 @@ enum ddr_type {
/* UID OTP */
#define UID_WORD_NB U(3)
/* FWU configuration (max supported value is 15) */
#define FWU_MAX_TRIAL_REBOOT U(3)
/*******************************************************************************
* STM32MP1 TAMP
******************************************************************************/
@ -642,7 +634,7 @@ static inline uintptr_t tamp_bkpr(uint32_t idx)
/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
#define PLAT_NB_RDEVS U(19)
/* 2 FIXED */
#define PLAT_NB_FIXED_REGS U(2)
#define PLAT_NB_FIXED_REGUS U(2)
/*******************************************************************************
* Device Tree defines

26
plat/st/stm32mp1/stm32mp1_fip_def.h
View file

@ -124,30 +124,4 @@
#define MAX_MMAP_REGIONS 10
#endif
/*******************************************************************************
* STM32MP1 RAW partition offset for devices without GPT
******************************************************************************/
#define STM32MP_EMMC_BOOT_FIP_OFFSET U(0x00040000)
#if PSA_FWU_SUPPORT
#define STM32MP_NOR_METADATA1_OFFSET U(0x00080000)
#define STM32MP_NOR_METADATA2_OFFSET U(0x000C0000)
#define STM32MP_NOR_FIP_A_OFFSET U(0x00100000)
#define STM32MP_NOR_FIP_A_GUID (const struct efi_guid)EFI_GUID(0x4fd84c93, \
0x54ef, 0x463f, 0xa7, 0xef, 0xae, 0x25, 0xff,\
0x88, 0x70, 0x87)
#define STM32MP_NOR_FIP_B_OFFSET U(0x00500000)
#define STM32MP_NOR_FIP_B_GUID (const struct efi_guid)EFI_GUID(0x09c54952, \
0xd5bf, 0x45af, 0xac, 0xee, 0x33, 0x53, 0x03,\
0x76, 0x6f, 0xb3)
#else /* PSA_FWU_SUPPORT */
#ifndef STM32MP_NOR_FIP_OFFSET
#define STM32MP_NOR_FIP_OFFSET U(0x00080000)
#endif
#ifndef STM32MP_NAND_FIP_OFFSET
#define STM32MP_NAND_FIP_OFFSET U(0x00200000)
#endif
#endif /* PSA_FWU_SUPPORT */
#endif /* STM32MP1_FIP_DEF_H */

11
plat/st/stm32mp2/aarch64/stm32mp2.S Normal file
View file

@ -0,0 +1,11 @@
/*
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
.section .bl2_image
.incbin BL2_BIN_PATH
.section .dtb_image
.incbin DTB_BIN_PATH

71
plat/st/stm32mp2/aarch64/stm32mp2.ld.S Normal file
View file

@ -0,0 +1,71 @@
/*
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP2_LD_S
#define STM32MP2_LD_S
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <platform_def.h>
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
ENTRY(__BL2_IMAGE_START__)
MEMORY {
HEADER (rw) : ORIGIN = 0x00000000, LENGTH = STM32MP_HEADER_RESERVED_SIZE
RAM (rwx) : ORIGIN = STM32MP_BINARY_BASE, LENGTH = STM32MP_BINARY_SIZE
}
SECTIONS
{
/*
* TF mapping must conform to ROM code specification.
*/
.header : {
__HEADER_START__ = .;
KEEP(*(.header))
. = ALIGN(4);
__HEADER_END__ = .;
} >HEADER
. = STM32MP_BINARY_BASE;
.data . : {
. = ALIGN(PAGE_SIZE);
__DATA_START__ = .;
*(.data*)
/*
* dtb.
* The strongest and only alignment contraint is MMU 4K page.
* Indeed as images below will be removed, 4K pages will be re-used.
*/
. = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE );
__DTB_IMAGE_START__ = .;
*(.dtb_image*)
__DTB_IMAGE_END__ = .;
/*
* bl2.
* The strongest and only alignment contraint is MMU 4K page.
* Indeed as images below will be removed, 4K pages will be re-used.
*/
#if SEPARATE_CODE_AND_RODATA
. = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE );
#else
. = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
#endif
__BL2_IMAGE_START__ = .;
*(.bl2_image*)
__BL2_IMAGE_END__ = .;
__DATA_END__ = .;
} >RAM
__TF_END__ = .;
}
#endif /* STM32MP2_LD_S */

194
plat/st/stm32mp2/aarch64/stm32mp2_helper.S Normal file
View file

@ -0,0 +1,194 @@
/*
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm_macros.S>
#include <drivers/st/stm32_gpio.h>
#include <platform_def.h>
#define GPIO_TX_SHIFT (DEBUG_UART_TX_GPIO_PORT << 1)
.globl platform_mem_init
.globl plat_secondary_cold_boot_setup
.globl plat_is_my_cpu_primary
.globl plat_crash_console_init
.globl plat_crash_console_flush
.globl plat_crash_console_putc
.globl plat_report_exception
func platform_mem_init
/* Nothing to do, don't need to init SYSRAM */
ret
endfunc platform_mem_init
/* ---------------------------------------------
* void plat_secondary_cold_boot_setup (void);
*
* Set secondary core in WFI waiting for core reset.
* ---------------------------------------------
*/
func plat_secondary_cold_boot_setup
dsb sy
wfi
/* This shouldn't be reached */
b .
endfunc plat_secondary_cold_boot_setup
/* ----------------------------------------------
* unsigned int plat_is_my_cpu_primary(void);
* This function checks if this is the primary CPU
* ----------------------------------------------
*/
func plat_is_my_cpu_primary
mrs x0, mpidr_el1
and x0, x0, #(MPIDR_CPU_MASK)
cmp x0, #STM32MP_PRIMARY_CPU
cset x0, eq
ret
endfunc plat_is_my_cpu_primary
/* ---------------------------------------------
* int plat_crash_console_init(void)
*
* Initialize the crash console without a C Runtime stack.
* ---------------------------------------------
*/
func plat_crash_console_init
/* Reset UART peripheral */
mov_imm x1, (RCC_BASE + DEBUG_UART_RST_REG)
ldr x2, =DEBUG_UART_RST_BIT
ldr x0, [x1]
orr x0, x0, x2
str x0, [x1]
1:
ldr x0, [x1]
ands x2, x0, x2
beq 1b
bic x2, x2, #DEBUG_UART_RST_BIT
str x2, [x1]
2:
ldr x0, [x1]
ands x2, x0, x2
bne 2b
/* Enable GPIOs for UART TX */
mov_imm x1, (RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)
ldr w2, [x1]
/* Configure GPIO */
orr w2, w2, #DEBUG_UART_TX_GPIO_BANK_CLK_EN
str w2, [x1]
mov_imm x1, DEBUG_UART_TX_GPIO_BANK_ADDRESS
/* Set GPIO mode alternate */
ldr w2, [x1, #GPIO_MODE_OFFSET]
bic w2, w2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT)
orr w2, w2, #(GPIO_MODE_ALTERNATE << GPIO_TX_SHIFT)
str w2, [x1, #GPIO_MODE_OFFSET]
/* Set GPIO speed low */
ldr w2, [x1, #GPIO_SPEED_OFFSET]
bic w2, w2, #(GPIO_SPEED_MASK << GPIO_TX_SHIFT)
str w2, [x1, #GPIO_SPEED_OFFSET]
/* Set no-pull */
ldr w2, [x1, #GPIO_PUPD_OFFSET]
bic w2, w2, #(GPIO_PULL_MASK << GPIO_TX_SHIFT)
str w2, [x1, #GPIO_PUPD_OFFSET]
/* Set alternate */
#if DEBUG_UART_TX_GPIO_PORT >= GPIO_ALT_LOWER_LIMIT
ldr w2, [x1, #GPIO_AFRH_OFFSET]
bic w2, w2, #(GPIO_ALTERNATE_MASK << \
((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2))
orr w2, w2, #(DEBUG_UART_TX_GPIO_ALTERNATE << \
((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2))
str w2, [x1, #GPIO_AFRH_OFFSET]
#else
ldr w2, [x1, #GPIO_AFRL_OFFSET]
bic w2, w2, #(GPIO_ALTERNATE_MASK << (DEBUG_UART_TX_GPIO_PORT << 2))
orr w2, w2, #(DEBUG_UART_TX_GPIO_ALTERNATE << (DEBUG_UART_TX_GPIO_PORT << 2))
str w2, [x1, #GPIO_AFRL_OFFSET]
#endif
/* Clear UART clock flexgen divisors, keep enable bit */
mov_imm x1, (RCC_BASE + DEBUG_UART_PREDIV_CFGR)
mov x2, #0
str w2, [x1]
mov_imm x1, (RCC_BASE + DEBUG_UART_FINDIV_CFGR)
mov x2, #0x40
str w2, [x1]
/* Enable UART clock, with its source */
mov_imm x1, (RCC_BASE + DEBUG_UART_TX_CLKSRC_REG)
mov_imm w2, (DEBUG_UART_TX_CLKSRC | RCC_XBARxCFGR_XBARxEN)
str w2, [x1]
mov_imm x1, (RCC_BASE + DEBUG_UART_TX_EN_REG)
ldr w2, [x1]
orr w2, w2, #DEBUG_UART_TX_EN
str w2, [x1]
mov_imm x0, STM32MP_DEBUG_USART_BASE
mov_imm x1, STM32MP_DEBUG_USART_CLK_FRQ
mov_imm x2, STM32MP_UART_BAUDRATE
b console_stm32_core_init
endfunc plat_crash_console_init
func plat_crash_console_flush
mov_imm x0, STM32MP_DEBUG_USART_BASE
b console_stm32_core_flush
endfunc plat_crash_console_flush
func plat_crash_console_putc
mov_imm x1, STM32MP_DEBUG_USART_BASE
cmp x0, #'\n'
b.ne 1f
mov x15, x30
mov x0, #'\r'
bl console_stm32_core_putc
mov x30, x15
mov x0, #'\n'
1:
b console_stm32_core_putc
endfunc plat_crash_console_putc
#ifdef IMAGE_BL2
/* ---------------------------------------------
* void plat_report_exception(unsigned int type)
* Function to report an unhandled exception
* with platform-specific means.
* ---------------------------------------------
*/
func plat_report_exception
mov x8, x30
adr x4, plat_err_str
bl asm_print_str
adr x4, esr_el3_str
bl asm_print_str
mrs x4, esr_el3
bl asm_print_hex
adr x4, elr_el3_str
bl asm_print_str
mrs x4, elr_el3
bl asm_print_hex
adr x4, far_el3_str
bl asm_print_str
mrs x4, far_el3
bl asm_print_hex
mov x30, x8
ret
endfunc plat_report_exception
.section .rodata.rev_err_str, "aS"
plat_err_str:
.asciz "\nPlatform exception reporting:"
esr_el3_str:
.asciz "\nESR_EL3: "
elr_el3_str:
.asciz "\nELR_EL3: "
far_el3_str:
.asciz "\nFAR_EL3: "
#endif /* IMAGE_BL2 */

26
plat/st/stm32mp2/bl2_plat_setup.c Normal file
View file

@ -0,0 +1,26 @@
/*
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <cdefs.h>
#include <stdint.h>
#include <stm32mp_common.h>
void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
u_register_t arg1 __unused,
u_register_t arg2 __unused,
u_register_t arg3 __unused)
{
stm32mp_setup_early_console();
}
void bl2_platform_setup(void)
{
}
void bl2_el3_plat_arch_setup(void)
{
}

406
plat/st/stm32mp2/include/boot_api.h Normal file
View file

@ -0,0 +1,406 @@
/*
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BOOT_API_H
#define BOOT_API_H
#include <stdint.h>
#include <stdio.h>
/*
* Exported constants
*/
/*
* Boot Context related definitions
*/
/*
* Possible value of boot context field 'auth_status'
*/
/* No authentication done */
#define BOOT_API_CTX_AUTH_NO 0x0U
/* Authentication done and failed */
#define BOOT_API_CTX_AUTH_FAILED 0x1U
/* Authentication done and succeeded */
#define BOOT_API_CTX_AUTH_SUCCESS 0x2U
/*
* Possible value of boot context field 'boot_interface_sel'
*/
/* Value of field 'boot_interface_sel' when no boot occurred */
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_NO 0x0U
/* Boot occurred on SD */
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD 0x1U
/* Boot occurred on EMMC */
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC 0x2U
/* Boot occurred on FMC */
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC 0x3U
/* Boot occurred on OSPI NOR */
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI 0x4U
/* Boot occurred on UART */
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART 0x5U
/* Boot occurred on USB */
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB 0x6U
/* Boot occurred on OSPI NAND */
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI 0x7U
/* Boot occurred on HyperFlash QSPI */
#define BOOT_API_CTX_BOOT_INTERFACE_SEL_HYPERFLASH_OSPI 0x8U
/*
* Possible value of boot context field 'emmc_xfer_status'
*/
#define BOOT_API_CTX_EMMC_XFER_STATUS_NOT_STARTED 0x0U
#define BOOT_API_CTX_EMMC_XFER_STATUS_DATAEND_DETECTED 0x1U
#define BOOT_API_CTX_EMMC_XFER_STATUS_XFER_DATA_TIMEOUT 0x2U
/*
* Possible value of boot context field 'emmc_error_status'
*/
#define BOOT_API_CTX_EMMC_ERROR_STATUS_NONE 0x0U
#define BOOT_API_CTX_EMMC_ERROR_STATUS_CMD_TIMEOUT 0x1U
#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_TIMEOUT 0x2U
#define BOOT_API_CTX_EMMC_ERROR_STATUS_DATA_CRC_FAIL 0x3U
#define BOOT_API_CTX_EMMC_ERROR_STATUS_NOT_ENOUGH_BOOT_DATA_RX 0x4U
#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_NOT_FOUND 0x5U
#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_SIZE_ZERO 0x6U
#define BOOT_API_CTX_EMMC_ERROR_STATUS_IMAGE_NOT_COMPLETE 0x7U
#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_ERROR 0x8U
/* Definitions relative to 'p_rom_version_info->platform_type_ver' field */
#define BOOT_API_CTX_ROM_VERSION_PLAT_VER_IC_EMU_FPGA 0xAA
#define BOOT_API_CTX_ROM_VERSION_PLAT_VER_FPGA_ONLY 0xBB
/* Image Header related definitions */
/* Definition of header version */
#define BOOT_API_HEADER_VERSION 0x00020000U
/*
* Magic number used to detect header in memory
* Its value must be 'S' 'T' 'M' 0x32, i.e 0x324D5453 as field
* 'bootapi_image_header_t.magic'
* This identifies the start of a boot image.
*/
#define BOOT_API_IMAGE_HEADER_MAGIC_NB 0x324D5453U
/* Definitions related to Authentication used in image header structure */
#define BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES 64
#define BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES 64
#define BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES 32
/* Possible values of the field 'boot_api_image_header_t.ecc_algo_type' */
#define BOOT_API_ECDSA_ALGO_TYPE_P256NIST 1
#define BOOT_API_ECDSA_ALGO_TYPE_BRAINPOOL256 2
/*
* Extension headers related definitions
*/
/* 'bootapi_image_header_t.extension_flag' used for authentication feature */
#define BOOT_API_AUTHENTICATION_EXTENSION_BIT BIT(0)
/* 'bootapi_image_header_t.extension_flag' used for FSBL decryption feature */
#define BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT BIT(1)
/* 'bootapi_image_header_t.extension_flag' used for padding header feature */
#define BOOT_API_PADDING_EXTENSION_BIT BIT(31)
/*
* mask of bits of field 'bootapi_image_header_t.extension_flag'
* used for extension headers
*/
#define BOOT_API_ALL_EXTENSIONS_MASK \
(BOOT_API_AUTHENTICATION_EXTENSION_BIT | \
BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT | \
BOOT_API_PADDING_EXTENSION_BIT)
/*
* Magic number of FSBL decryption extension header
* The value shall gives the four bytes 'S','T',0x00,0x01 in memory
*/
#define BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB 0x01005453U
/*
* Magic number of PKH revocation extension header
* The value shall gives the four bytes 'S','T',0x00,0x02 in memory
*/
#define BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB 0x02005453U
/* Max number of ECDSA public key hash in table */
#define BOOT_API_AUTHENTICATION_NB_PKH_MAX 8U
/* ECDSA public key hash table size in bytes */
#define BOOT_API_AUTHENTICATION_TABLE_SIZE_BYTES \
(BOOT_API_AUTHENTICATION_NB_PKH_MAX * \
BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES)
/*
* Magic number of padding extension header
* The value shall gives the four bytes 'S','T',0xFF,0xFF in memory
*/
#define BOOT_API_PADDING_HEADER_MAGIC_NB 0xFFFF5453U
/*
* Related to binaryType
* 0x00: U-Boot
* 0x10-0x1F: TF-A
* 0x20-0X2F: OPTEE
* 0x30: CM33 image
*/
#define BOOT_API_IMAGE_TYPE_UBOOT 0x0
#define BOOT_API_IMAGE_TYPE_M33 0x30
/*
* Cores secure magic numbers
* Constant to be stored in bakcup register
* BOOT_API_MAGIC_NUMBER_TAMP_BCK_REG_IDX
*/
#define BOOT_API_A35_CORE0_MAGIC_NUMBER 0xCA7FACE0U
#define BOOT_API_A35_CORE1_MAGIC_NUMBER 0xCA7FACE1U
/*
* TAMP_BCK9R register index
* This register is used to write a Magic Number in order to restart
* Cortex A35 Core 1 and make it execute @ branch address from TAMP_BCK5R
*/
#define BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX 9U
/*
* TAMP_BCK10R register index
* This register is used to contain the branch address of
* Cortex A35 Core 1 when restarted by a TAMP_BCK4R magic number writing
*/
#define BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX 10U
/*
* Possible value of boot context field 'hse_clock_value_in_hz'
*/
#define BOOT_API_CTX_HSE_CLOCK_VALUE_UNDEFINED 0U
#define BOOT_API_CTX_HSE_CLOCK_VALUE_19_2_MHZ 19200000U
#define BOOT_API_CTX_HSE_CLOCK_VALUE_24_MHZ 24000000U
#define BOOT_API_CTX_HSE_CLOCK_VALUE_25_MHZ 25000000U
#define BOOT_API_CTX_HSE_CLOCK_VALUE_26_MHZ 26000000U
#define BOOT_API_CTX_HSE_CLOCK_VALUE_40_MHZ 40000000U
#define BOOT_API_CTX_HSE_CLOCK_VALUE_48_MHZ 48000000U
/*
* Possible value of boot context field 'boot_partition_used_toboot'
*/
#define BOOT_API_CTX_BOOT_PARTITION_UNDEFINED 0U
/* Used FSBL1 to boot */
#define BOOT_API_CTX_BOOT_PARTITION_FSBL1 1U
/* Used FSBL2 to boot */
#define BOOT_API_CTX_BOOT_PARTITION_FSBL2 2U
#define BOOT_API_RETURN_OK 0x66U
/*
* Possible values of boot context field
* 'ssp_config_ptr_in->ssp_cmd'
*/
/* 'K' 'B' 'U' 'P' -.> 'PUBK' */
#define BOOT_API_CTX_SSP_CMD_CALC_CHIP_PUBK 0x4B425550
/*
* Exported types
*/
/*
* bootROM version information structure definition
* Total size = 24 bytes = 6 uint32_t
*/
typedef struct {
/* Chip Version */
uint32_t chip_ver;
/* Cut version within a fixed chip version */
uint32_t cut_ver;
/* Version of ROM Mask within a fixed cut version */
uint32_t rom_mask_ver;
/* Internal Version of bootROM code */
uint32_t bootrom_ver;
/* Version of bootROM adapted */
uint32_t for_chip_design_rtl_ver;
/* Restriction on compiled platform when it applies */
uint32_t platform_type_ver;
} boot_api_rom_version_info_t;
/*
* Boot Context related definitions
*/
/*
* Boot core boot configuration structure
* Specifies all items of the secure boot configuration
* Memory and peripheral part.
*/
typedef struct {
/* Boot partition: ie FSBL partition on which the boot was successful */
uint32_t boot_partition_used_toboot;
uint32_t reserved1[3];
/*
* Information specific to an SD boot
* Updated each time an SD boot is at least attempted,
* even if not successful
* Note : This is useful to understand why an SD boot failed
* in particular
*/
uint32_t sd_err_internal_timeout_cnt;
uint32_t sd_err_dcrc_fail_cnt;
uint32_t sd_err_dtimeout_cnt;
uint32_t sd_err_ctimeout_cnt;
uint32_t sd_err_ccrc_fail_cnt;
uint32_t sd_overall_retry_cnt;
/*
* Information specific to an eMMC boot
* Updated each time an eMMC boot is at least attempted,
* even if not successful
* Note : This is useful to understand why an eMMC boot failed
* in particular
*/
uint32_t emmc_xfer_status;
uint32_t emmc_error_status;
uint32_t emmc_nbbytes_rxcopied_tosysram_download_area;
uint32_t reserved[4];
/*
* Boot interface used to boot : take values from defines
* BOOT_API_CTX_BOOT_INTERFACE_SEL_XXX above
*/
uint16_t boot_interface_selected;
uint16_t boot_interface_instance;
uint32_t hse_clock_value_in_hz;
uint32_t nand_fsbl_first_block;
/*
* Returned authentication status : take values from defines
* BOOT_API_CTX_AUTH_XXX above
*/
uint32_t auth_status;
/* Pointer on ROM constant containing ROM information */
const boot_api_rom_version_info_t *p_rom_version_info;
} __packed boot_api_context_t;
/*
* Image Header related definitions
*/
/*
* Structure used to define the common Header format used for FSBL, xloader,
* ... and in particular used by bootROM for FSBL header readout.
* FSBL header size is 256 Bytes = 0x100
*/
typedef struct {
/* BOOT_API_IMAGE_HEADER_MAGIC_NB */
uint32_t magic;
uint8_t image_signature[BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES];
/*
* Checksum of payload
* 32-bit sum all payload bytes considered as 8 bit unsigned
* numbers, discarding any overflow bits.
* Use to check UART/USB downloaded image integrity when signature
* is not used
*/
uint32_t payload_checksum;
/* Image header version : should have value BOOT_API_HEADER_VERSION */
uint32_t header_version;
/* Image length in bytes */
uint32_t image_length;
/*
* Image Entry point address : should be in the SYSRAM area
* and at least within the download area range
*/
uint32_t image_entry_point;
/* Reserved */
uint32_t reserved1;
/*
* Image load address : not used by bootROM but to be consistent
* with header format for other packages (xloader, ...)
*/
uint32_t load_address;
/* Reserved */
uint32_t reserved2;
/* Image version to be compared by bootROM with FSBL_A or FSBL_M version
* counter value in OTP prior executing the downloaded image
*/
uint32_t image_version;
/*
* Extension flags :
*
* Bit 0 : Authentication extension header
* value 0 : No signature check request
* Bit 1 : Encryption extension header
* Bit 2 : Padding extension header
*/
uint32_t extension_flags;
/* Length in bytes of all extension headers */
uint32_t extension_headers_length;
/* Add binary type information */
uint32_t binary_type;
/* Pad up to 128 byte total size */
uint8_t pad[16];
/* Followed by extension header */
uint8_t ext_header[];
} __packed boot_api_image_header_t;
typedef uint8_t boot_api_sha256_t[BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES];
typedef struct {
/* Extension header type:
* BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB or
* BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB
* BOOT_API_PADDING_HEADER_MAGIC_NB
*/
uint32_t type;
/* Extension header len in byte */
uint32_t len;
/* parameters of this extension */
uint8_t params[];
} __packed boot_extension_header_t;
typedef struct {
/* Idx of ECDSA public key to be used in table */
uint32_t pk_idx;
/* Number of ECDSA public key in table */
uint32_t nb_pk;
/*
* Type of ECC algorithm to use :
* value 1 : for P-256 NIST algorithm
* value 2 : for Brainpool 256 algorithm
* See definitions 'BOOT_API_ECDSA_ALGO_TYPE_XXX' above.
*/
uint32_t ecc_algo_type;
/* ECDSA public key to be used to check signature. */
uint8_t ecc_pubk[BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES];
/* table of Hash of Algo+ECDSA public key */
boot_api_sha256_t pk_hashes[];
} __packed boot_ext_header_params_authentication_t;
typedef struct {
/* Size of encryption key (128 or 256) */
uint32_t key_size;
uint32_t derivation_cont;
/* 128 msb bits of plain payload SHA256 */
uint32_t hash[4];
} __packed boot_ext_header_params_encrypted_fsbl_t;
#endif /* BOOT_API_H */

13
plat/st/stm32mp2/include/plat_macros.S Normal file
View file

@ -0,0 +1,13 @@
/*
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLAT_MACROS_S
#define PLAT_MACROS_S
.macro plat_crash_print_regs
.endm
#endif /* PLAT_MACROS_S */

87
plat/st/stm32mp2/include/platform_def.h Normal file
View file

@ -0,0 +1,87 @@
/*
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <arch.h>
#include <lib/utils_def.h>
#include <plat/common/common_def.h>
#include "../stm32mp2_def.h"
/*******************************************************************************
* Generic platform constants
******************************************************************************/
/* Size of cacheable stacks */
#define PLATFORM_STACK_SIZE 0xC00
#define STM32MP_PRIMARY_CPU U(0x0)
#define STM32MP_SECONDARY_CPU U(0x1)
#define MAX_IO_DEVICES U(4)
#define MAX_IO_HANDLES U(4)
#define MAX_IO_BLOCK_DEVICES U(1)
#define MAX_IO_MTD_DEVICES U(1)
#define PLATFORM_CLUSTER_COUNT U(1)
#define PLATFORM_CORE_COUNT U(2)
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
#define PLAT_MAX_PWR_LVL U(5)
#define PLAT_MAX_CPU_SUSPEND_PWR_LVL U(5)
#define PLAT_NUM_PWR_DOMAINS U(7)
/* Local power state for power domains in Run state. */
#define STM32MP_LOCAL_STATE_RUN U(0)
/* Local power state for retention. */
#define STM32MP_LOCAL_STATE_RET U(1)
#define STM32MP_LOCAL_STATE_LP U(2)
#define PLAT_MAX_RET_STATE STM32MP_LOCAL_STATE_LP
/* Local power state for OFF/power-down. */
#define STM32MP_LOCAL_STATE_OFF U(3)
#define PLAT_MAX_OFF_STATE STM32MP_LOCAL_STATE_OFF
/* Macros to parse the state information from State-ID (recommended encoding) */
#define PLAT_LOCAL_PSTATE_WIDTH U(4)
#define PLAT_LOCAL_PSTATE_MASK GENMASK(PLAT_LOCAL_PSTATE_WIDTH - 1U, 0)
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
/*
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth.
*/
#define BL2_BASE STM32MP_BL2_BASE
#define BL2_LIMIT (STM32MP_BL2_BASE + \
STM32MP_BL2_SIZE)
/*******************************************************************************
* BL33 specific defines.
******************************************************************************/
#define BL33_BASE STM32MP_BL33_BASE
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 33)
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 33)
/*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.
******************************************************************************/
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
#endif /* PLATFORM_DEF_H */

20
plat/st/stm32mp2/plat_bl2_mem_params_desc.c Normal file
View file

@ -0,0 +1,20 @@
/*
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/desc_image_load.h>
/*******************************************************************************
* Following descriptor provides BL image/ep information that gets used
* by BL2 to load the images and also subset of this information is
* passed to next BL image. The image loading sequence is managed by
* populating the images in required loading order. The image execution
* sequence is managed by populating the `next_handoff_image_id` with
* the next executable image id.
******************************************************************************/
static bl_mem_params_node_t bl2_mem_params_descs[] = {
};
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)

52
plat/st/stm32mp2/platform.mk Normal file
View file

@ -0,0 +1,52 @@
#
# Copyright (c) 2023, STMicroelectronics - All Rights Reserved
#
# SPDX-License-Identifier: BSD-3-Clause
#
include plat/st/common/common.mk
CRASH_REPORTING := 1
ENABLE_PIE := 1
PROGRAMMABLE_RESET_ADDRESS := 1
# Default Device tree
DTB_FILE_NAME ?= stm32mp257f-ev1.dtb
STM32MP25 := 1
# STM32 image header version v2.2
STM32_HEADER_VERSION_MAJOR := 2
STM32_HEADER_VERSION_MINOR := 2
# Number of TF-A copies in the device
STM32_TF_A_COPIES := 2
# PLAT_PARTITION_MAX_ENTRIES must take care of STM32_TF-A_COPIES and other partitions
# such as metadata (2) and fsbl-m (2) to find all the FIP partitions (default is 2).
PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 6)))
# Device tree
BL2_DTSI := stm32mp25-bl2.dtsi
FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
# Macros and rules to build TF binary
STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S
STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S
# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI
# Disable mbranch-protection to avoid adding useless code
TF_CFLAGS += -mbranch-protection=none
# Include paths and source files
PLAT_INCLUDES += -Iplat/st/stm32mp2/include/
PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S
PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c
include plat/st/common/common_rules.mk

222
plat/st/stm32mp2/stm32mp2_def.h Normal file
View file

@ -0,0 +1,222 @@
/*
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP2_DEF_H
#define STM32MP2_DEF_H
#include <common/tbbr/tbbr_img_def.h>
#ifndef __ASSEMBLER__
#include <drivers/st/bsec.h>
#endif
#include <drivers/st/stm32mp25_rcc.h>
#include <dt-bindings/clock/stm32mp25-clks.h>
#include <dt-bindings/clock/stm32mp25-clksrc.h>
#include <dt-bindings/reset/stm32mp25-resets.h>
#ifndef __ASSEMBLER__
#include <boot_api.h>
#include <stm32mp_common.h>
#include <stm32mp_dt.h>
#include <stm32mp_shared_resources.h>
#endif
/*******************************************************************************
* STM32MP2 memory map related constants
******************************************************************************/
#define STM32MP_SYSRAM_BASE U(0x0E000000)
#define STM32MP_SYSRAM_SIZE U(0x00040000)
#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
#define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
/* DDR configuration */
#define STM32MP_DDR_BASE U(0x80000000)
#define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */
/* DDR power initializations */
#ifndef __ASSEMBLER__
enum ddr_type {
STM32MP_DDR3,
STM32MP_DDR4,
STM32MP_LPDDR4
};
#endif
/* Section used inside TF binaries */
#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
/* 512 Octets reserved for header */
#define STM32MP_HEADER_SIZE U(0x00000200)
#define STM32MP_HEADER_BASE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_PARAM_LOAD_SIZE)
/* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
#define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_PARAM_LOAD_SIZE + \
STM32MP_HEADER_SIZE)
#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
(STM32MP_PARAM_LOAD_SIZE + \
STM32MP_HEADER_SIZE))
#define STM32MP_BL2_SIZE U(0x0002A000) /* 168 KB for BL2 */
#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
/* BL2 and BL32/sp_min require 4 tables */
#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
/*
* MAX_MMAP_REGIONS is usually:
* BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup
*/
#define MAX_MMAP_REGIONS 6
/* DTB initialization value */
#define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
STM32MP_BL2_DTB_SIZE)
#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000))
#define STM32MP_BL33_MAX_SIZE U(0x400000)
/*******************************************************************************
* STM32MP2 RCC
******************************************************************************/
#define RCC_BASE U(0x44200000)
/*******************************************************************************
* STM32MP2 PWR
******************************************************************************/
#define PWR_BASE U(0x44210000)
/*******************************************************************************
* STM32MP2 GPIO
******************************************************************************/
#define GPIOA_BASE U(0x44240000)
#define GPIOB_BASE U(0x44250000)
#define GPIOC_BASE U(0x44260000)
#define GPIOD_BASE U(0x44270000)
#define GPIOE_BASE U(0x44280000)
#define GPIOF_BASE U(0x44290000)
#define GPIOG_BASE U(0x442A0000)
#define GPIOH_BASE U(0x442B0000)
#define GPIOI_BASE U(0x442C0000)
#define GPIOJ_BASE U(0x442D0000)
#define GPIOK_BASE U(0x442E0000)
#define GPIOZ_BASE U(0x46200000)
#define GPIO_BANK_OFFSET U(0x10000)
#define STM32MP_GPIOS_PIN_MAX_COUNT 16
#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
/*******************************************************************************
* STM32MP2 UART
******************************************************************************/
#define USART1_BASE U(0x40330000)
#define USART2_BASE U(0x400E0000)
#define USART3_BASE U(0x400F0000)
#define UART4_BASE U(0x40100000)
#define UART5_BASE U(0x40110000)
#define USART6_BASE U(0x40220000)
#define UART7_BASE U(0x40370000)
#define UART8_BASE U(0x40380000)
#define UART9_BASE U(0x402C0000)
#define STM32MP_NB_OF_UART U(9)
/* For UART crash console */
#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
/* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */
#define STM32MP_DEBUG_USART_BASE USART2_BASE
#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE
#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR
#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN
#define DEBUG_UART_TX_GPIO_PORT 4
#define DEBUG_UART_TX_GPIO_ALTERNATE 6
#define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR
#define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI
#define DEBUG_UART_TX_EN_REG RCC_USART2CFGR
#define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN
#define DEBUG_UART_RST_REG RCC_USART2CFGR
#define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST
#define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR
#define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR
/*******************************************************************************
* STM32MP2 SDMMC
******************************************************************************/
#define STM32MP_SDMMC1_BASE U(0x48220000)
#define STM32MP_SDMMC2_BASE U(0x48230000)
#define STM32MP_SDMMC3_BASE U(0x48240000)
/*******************************************************************************
* STM32MP2 TAMP
******************************************************************************/
#define PLAT_MAX_TAMP_INT U(5)
#define PLAT_MAX_TAMP_EXT U(3)
#define TAMP_BASE U(0x46010000)
#define TAMP_SMCR (TAMP_BASE + U(0x20))
#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
#define TAMP_BKP_REG_CLK CK_BUS_RTC
#define TAMP_BKP_SEC_NUMBER U(10)
#define TAMP_COUNTR U(0x40)
#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
static inline uintptr_t tamp_bkpr(uint32_t idx)
{
return TAMP_BKP_REGISTER_BASE + (idx << 2);
}
#endif
/*******************************************************************************
* STM32MP2 DDRCTRL
******************************************************************************/
#define DDRCTRL_BASE U(0x48040000)
/*******************************************************************************
* STM32MP2 DDRDBG
******************************************************************************/
#define DDRDBG_BASE U(0x48050000)
/*******************************************************************************
* STM32MP2 DDRPHYC
******************************************************************************/
#define DDRPHYC_BASE U(0x48C00000)
/*******************************************************************************
* Miscellaneous STM32MP1 peripherals base address
******************************************************************************/
#define BSEC_BASE U(0x44000000)
#define DBGMCU_BASE U(0x4A010000)
#define HASH_BASE U(0x42010000)
#define RTC_BASE U(0x46000000)
#define STGEN_BASE U(0x48080000)
#define SYSCFG_BASE U(0x44230000)
/*******************************************************************************
* REGULATORS
******************************************************************************/
/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
#define PLAT_NB_RDEVS U(19)
/* 2 FIXED */
#define PLAT_NB_FIXED_REGUS U(2)
/* No GPIO regu */
#define PLAT_NB_GPIO_REGUS U(0)
/*******************************************************************************
* Device Tree defines
******************************************************************************/
#define DT_BSEC_COMPAT "st,stm32mp25-bsec"
#define DT_DDR_COMPAT "st,stm32mp2-ddr"
#define DT_PWR_COMPAT "st,stm32mp25-pwr"
#define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
#define DT_UART_COMPAT "st,stm32h7-uart"
#endif /* STM32MP2_DEF_H */