mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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35527fb418
This new STMicroelectronics SoC is based on a dual Cortex-A35. For the moment, only BL2 is compiled with the common parts for ST platforms. Change-Id: I1bc4e6835dba4230359ea9b26d736791e27258aa Signed-off-by: Yann Gautier <yann.gautier@st.com>
406 lines
12 KiB
C
406 lines
12 KiB
C
/*
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* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOOT_API_H
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#define BOOT_API_H
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#include <stdint.h>
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#include <stdio.h>
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/*
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* Exported constants
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*/
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/*
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* Boot Context related definitions
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*/
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/*
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* Possible value of boot context field 'auth_status'
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*/
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/* No authentication done */
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#define BOOT_API_CTX_AUTH_NO 0x0U
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/* Authentication done and failed */
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#define BOOT_API_CTX_AUTH_FAILED 0x1U
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/* Authentication done and succeeded */
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#define BOOT_API_CTX_AUTH_SUCCESS 0x2U
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/*
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* Possible value of boot context field 'boot_interface_sel'
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*/
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/* Value of field 'boot_interface_sel' when no boot occurred */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_NO 0x0U
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/* Boot occurred on SD */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD 0x1U
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/* Boot occurred on EMMC */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC 0x2U
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/* Boot occurred on FMC */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC 0x3U
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/* Boot occurred on OSPI NOR */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI 0x4U
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/* Boot occurred on UART */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART 0x5U
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/* Boot occurred on USB */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB 0x6U
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/* Boot occurred on OSPI NAND */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI 0x7U
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/* Boot occurred on HyperFlash QSPI */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_HYPERFLASH_OSPI 0x8U
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/*
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* Possible value of boot context field 'emmc_xfer_status'
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*/
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#define BOOT_API_CTX_EMMC_XFER_STATUS_NOT_STARTED 0x0U
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#define BOOT_API_CTX_EMMC_XFER_STATUS_DATAEND_DETECTED 0x1U
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#define BOOT_API_CTX_EMMC_XFER_STATUS_XFER_DATA_TIMEOUT 0x2U
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/*
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* Possible value of boot context field 'emmc_error_status'
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*/
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_NONE 0x0U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_CMD_TIMEOUT 0x1U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_TIMEOUT 0x2U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_DATA_CRC_FAIL 0x3U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_NOT_ENOUGH_BOOT_DATA_RX 0x4U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_NOT_FOUND 0x5U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_SIZE_ZERO 0x6U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_IMAGE_NOT_COMPLETE 0x7U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_ERROR 0x8U
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/* Definitions relative to 'p_rom_version_info->platform_type_ver' field */
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#define BOOT_API_CTX_ROM_VERSION_PLAT_VER_IC_EMU_FPGA 0xAA
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#define BOOT_API_CTX_ROM_VERSION_PLAT_VER_FPGA_ONLY 0xBB
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/* Image Header related definitions */
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/* Definition of header version */
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#define BOOT_API_HEADER_VERSION 0x00020000U
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/*
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* Magic number used to detect header in memory
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* Its value must be 'S' 'T' 'M' 0x32, i.e 0x324D5453 as field
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* 'bootapi_image_header_t.magic'
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* This identifies the start of a boot image.
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*/
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#define BOOT_API_IMAGE_HEADER_MAGIC_NB 0x324D5453U
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/* Definitions related to Authentication used in image header structure */
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#define BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES 64
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#define BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES 64
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#define BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES 32
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/* Possible values of the field 'boot_api_image_header_t.ecc_algo_type' */
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#define BOOT_API_ECDSA_ALGO_TYPE_P256NIST 1
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#define BOOT_API_ECDSA_ALGO_TYPE_BRAINPOOL256 2
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/*
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* Extension headers related definitions
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*/
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/* 'bootapi_image_header_t.extension_flag' used for authentication feature */
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#define BOOT_API_AUTHENTICATION_EXTENSION_BIT BIT(0)
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/* 'bootapi_image_header_t.extension_flag' used for FSBL decryption feature */
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#define BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT BIT(1)
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/* 'bootapi_image_header_t.extension_flag' used for padding header feature */
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#define BOOT_API_PADDING_EXTENSION_BIT BIT(31)
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/*
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* mask of bits of field 'bootapi_image_header_t.extension_flag'
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* used for extension headers
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*/
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#define BOOT_API_ALL_EXTENSIONS_MASK \
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(BOOT_API_AUTHENTICATION_EXTENSION_BIT | \
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BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT | \
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BOOT_API_PADDING_EXTENSION_BIT)
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/*
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* Magic number of FSBL decryption extension header
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* The value shall gives the four bytes 'S','T',0x00,0x01 in memory
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*/
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#define BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB 0x01005453U
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/*
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* Magic number of PKH revocation extension header
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* The value shall gives the four bytes 'S','T',0x00,0x02 in memory
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*/
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#define BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB 0x02005453U
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/* Max number of ECDSA public key hash in table */
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#define BOOT_API_AUTHENTICATION_NB_PKH_MAX 8U
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/* ECDSA public key hash table size in bytes */
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#define BOOT_API_AUTHENTICATION_TABLE_SIZE_BYTES \
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(BOOT_API_AUTHENTICATION_NB_PKH_MAX * \
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BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES)
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/*
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* Magic number of padding extension header
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* The value shall gives the four bytes 'S','T',0xFF,0xFF in memory
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*/
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#define BOOT_API_PADDING_HEADER_MAGIC_NB 0xFFFF5453U
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/*
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* Related to binaryType
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* 0x00: U-Boot
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* 0x10-0x1F: TF-A
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* 0x20-0X2F: OPTEE
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* 0x30: CM33 image
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*/
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#define BOOT_API_IMAGE_TYPE_UBOOT 0x0
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#define BOOT_API_IMAGE_TYPE_M33 0x30
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/*
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* Cores secure magic numbers
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* Constant to be stored in bakcup register
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* BOOT_API_MAGIC_NUMBER_TAMP_BCK_REG_IDX
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*/
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#define BOOT_API_A35_CORE0_MAGIC_NUMBER 0xCA7FACE0U
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#define BOOT_API_A35_CORE1_MAGIC_NUMBER 0xCA7FACE1U
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/*
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* TAMP_BCK9R register index
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* This register is used to write a Magic Number in order to restart
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* Cortex A35 Core 1 and make it execute @ branch address from TAMP_BCK5R
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*/
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#define BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX 9U
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/*
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* TAMP_BCK10R register index
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* This register is used to contain the branch address of
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* Cortex A35 Core 1 when restarted by a TAMP_BCK4R magic number writing
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*/
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#define BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX 10U
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/*
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* Possible value of boot context field 'hse_clock_value_in_hz'
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*/
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_UNDEFINED 0U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_19_2_MHZ 19200000U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_24_MHZ 24000000U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_25_MHZ 25000000U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_26_MHZ 26000000U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_40_MHZ 40000000U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_48_MHZ 48000000U
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/*
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* Possible value of boot context field 'boot_partition_used_toboot'
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*/
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#define BOOT_API_CTX_BOOT_PARTITION_UNDEFINED 0U
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/* Used FSBL1 to boot */
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#define BOOT_API_CTX_BOOT_PARTITION_FSBL1 1U
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/* Used FSBL2 to boot */
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#define BOOT_API_CTX_BOOT_PARTITION_FSBL2 2U
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#define BOOT_API_RETURN_OK 0x66U
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/*
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* Possible values of boot context field
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* 'ssp_config_ptr_in->ssp_cmd'
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*/
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/* 'K' 'B' 'U' 'P' -.> 'PUBK' */
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#define BOOT_API_CTX_SSP_CMD_CALC_CHIP_PUBK 0x4B425550
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/*
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* Exported types
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*/
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/*
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* bootROM version information structure definition
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* Total size = 24 bytes = 6 uint32_t
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*/
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typedef struct {
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/* Chip Version */
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uint32_t chip_ver;
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/* Cut version within a fixed chip version */
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uint32_t cut_ver;
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/* Version of ROM Mask within a fixed cut version */
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uint32_t rom_mask_ver;
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/* Internal Version of bootROM code */
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uint32_t bootrom_ver;
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/* Version of bootROM adapted */
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uint32_t for_chip_design_rtl_ver;
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/* Restriction on compiled platform when it applies */
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uint32_t platform_type_ver;
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} boot_api_rom_version_info_t;
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/*
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* Boot Context related definitions
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*/
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/*
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* Boot core boot configuration structure
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* Specifies all items of the secure boot configuration
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* Memory and peripheral part.
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*/
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typedef struct {
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/* Boot partition: ie FSBL partition on which the boot was successful */
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uint32_t boot_partition_used_toboot;
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uint32_t reserved1[3];
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/*
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* Information specific to an SD boot
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* Updated each time an SD boot is at least attempted,
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* even if not successful
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* Note : This is useful to understand why an SD boot failed
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* in particular
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*/
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uint32_t sd_err_internal_timeout_cnt;
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uint32_t sd_err_dcrc_fail_cnt;
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uint32_t sd_err_dtimeout_cnt;
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uint32_t sd_err_ctimeout_cnt;
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uint32_t sd_err_ccrc_fail_cnt;
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uint32_t sd_overall_retry_cnt;
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/*
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* Information specific to an eMMC boot
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* Updated each time an eMMC boot is at least attempted,
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* even if not successful
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* Note : This is useful to understand why an eMMC boot failed
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* in particular
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*/
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uint32_t emmc_xfer_status;
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uint32_t emmc_error_status;
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uint32_t emmc_nbbytes_rxcopied_tosysram_download_area;
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uint32_t reserved[4];
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/*
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* Boot interface used to boot : take values from defines
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* BOOT_API_CTX_BOOT_INTERFACE_SEL_XXX above
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*/
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uint16_t boot_interface_selected;
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uint16_t boot_interface_instance;
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uint32_t hse_clock_value_in_hz;
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uint32_t nand_fsbl_first_block;
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/*
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* Returned authentication status : take values from defines
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* BOOT_API_CTX_AUTH_XXX above
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*/
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uint32_t auth_status;
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/* Pointer on ROM constant containing ROM information */
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const boot_api_rom_version_info_t *p_rom_version_info;
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} __packed boot_api_context_t;
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/*
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* Image Header related definitions
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*/
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/*
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* Structure used to define the common Header format used for FSBL, xloader,
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* ... and in particular used by bootROM for FSBL header readout.
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* FSBL header size is 256 Bytes = 0x100
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*/
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typedef struct {
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/* BOOT_API_IMAGE_HEADER_MAGIC_NB */
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uint32_t magic;
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uint8_t image_signature[BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES];
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/*
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* Checksum of payload
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* 32-bit sum all payload bytes considered as 8 bit unsigned
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* numbers, discarding any overflow bits.
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* Use to check UART/USB downloaded image integrity when signature
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* is not used
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*/
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uint32_t payload_checksum;
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/* Image header version : should have value BOOT_API_HEADER_VERSION */
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uint32_t header_version;
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/* Image length in bytes */
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uint32_t image_length;
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/*
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* Image Entry point address : should be in the SYSRAM area
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* and at least within the download area range
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*/
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uint32_t image_entry_point;
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/* Reserved */
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uint32_t reserved1;
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/*
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* Image load address : not used by bootROM but to be consistent
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* with header format for other packages (xloader, ...)
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*/
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uint32_t load_address;
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/* Reserved */
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uint32_t reserved2;
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/* Image version to be compared by bootROM with FSBL_A or FSBL_M version
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* counter value in OTP prior executing the downloaded image
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*/
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uint32_t image_version;
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/*
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* Extension flags :
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*
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* Bit 0 : Authentication extension header
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* value 0 : No signature check request
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* Bit 1 : Encryption extension header
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* Bit 2 : Padding extension header
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*/
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uint32_t extension_flags;
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/* Length in bytes of all extension headers */
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uint32_t extension_headers_length;
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/* Add binary type information */
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uint32_t binary_type;
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/* Pad up to 128 byte total size */
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uint8_t pad[16];
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/* Followed by extension header */
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uint8_t ext_header[];
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} __packed boot_api_image_header_t;
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typedef uint8_t boot_api_sha256_t[BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES];
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typedef struct {
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/* Extension header type:
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* BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB or
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* BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB
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* BOOT_API_PADDING_HEADER_MAGIC_NB
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*/
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uint32_t type;
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/* Extension header len in byte */
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uint32_t len;
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/* parameters of this extension */
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uint8_t params[];
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} __packed boot_extension_header_t;
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typedef struct {
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/* Idx of ECDSA public key to be used in table */
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uint32_t pk_idx;
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/* Number of ECDSA public key in table */
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uint32_t nb_pk;
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/*
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* Type of ECC algorithm to use :
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* value 1 : for P-256 NIST algorithm
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* value 2 : for Brainpool 256 algorithm
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* See definitions 'BOOT_API_ECDSA_ALGO_TYPE_XXX' above.
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*/
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uint32_t ecc_algo_type;
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/* ECDSA public key to be used to check signature. */
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uint8_t ecc_pubk[BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES];
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/* table of Hash of Algo+ECDSA public key */
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boot_api_sha256_t pk_hashes[];
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} __packed boot_ext_header_params_authentication_t;
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typedef struct {
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/* Size of encryption key (128 or 256) */
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uint32_t key_size;
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uint32_t derivation_cont;
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/* 128 msb bits of plain payload SHA256 */
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uint32_t hash[4];
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} __packed boot_ext_header_params_encrypted_fsbl_t;
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#endif /* BOOT_API_H */
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