mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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feat(st): introduce new platform STM32MP2
This new STMicroelectronics SoC is based on a dual Cortex-A35. For the moment, only BL2 is compiled with the common parts for ST platforms. Change-Id: I1bc4e6835dba4230359ea9b26d736791e27258aa Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier
parent
3ccb708ece
commit
35527fb418
8 changed files with 800 additions and 0 deletions
63
plat/st/stm32mp2/aarch64/stm32mp2_helper.S
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63
plat/st/stm32mp2/aarch64/stm32mp2_helper.S
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@ -0,0 +1,63 @@
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/*
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* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <platform_def.h>
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.globl platform_mem_init
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl plat_crash_console_init
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.globl plat_crash_console_flush
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.globl plat_crash_console_putc
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func platform_mem_init
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/* Nothing to do, don't need to init SYSRAM */
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ret
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endfunc platform_mem_init
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/* ---------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* Set secondary core in WFI waiting for core reset.
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* ---------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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dsb sy
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wfi
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/* This shouldn't be reached */
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b .
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endfunc plat_secondary_cold_boot_setup
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/* ----------------------------------------------
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* unsigned int plat_is_my_cpu_primary(void);
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* This function checks if this is the primary CPU
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* ----------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CPU_MASK)
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cmp x0, #STM32MP_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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*
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* Initialize the crash console without a C Runtime stack.
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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endfunc plat_crash_console_init
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func plat_crash_console_flush
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endfunc plat_crash_console_flush
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func plat_crash_console_putc
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endfunc plat_crash_console_putc
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23
plat/st/stm32mp2/bl2_plat_setup.c
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23
plat/st/stm32mp2/bl2_plat_setup.c
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@ -0,0 +1,23 @@
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/*
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* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <cdefs.h>
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#include <stdint.h>
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void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
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u_register_t arg1 __unused,
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u_register_t arg2 __unused,
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u_register_t arg3 __unused)
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{
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}
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void bl2_platform_setup(void)
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{
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}
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void bl2_el3_plat_arch_setup(void)
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{
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}
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406
plat/st/stm32mp2/include/boot_api.h
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406
plat/st/stm32mp2/include/boot_api.h
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@ -0,0 +1,406 @@
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/*
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* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOOT_API_H
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#define BOOT_API_H
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#include <stdint.h>
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#include <stdio.h>
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/*
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* Exported constants
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*/
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/*
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* Boot Context related definitions
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*/
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/*
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* Possible value of boot context field 'auth_status'
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*/
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/* No authentication done */
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#define BOOT_API_CTX_AUTH_NO 0x0U
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/* Authentication done and failed */
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#define BOOT_API_CTX_AUTH_FAILED 0x1U
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/* Authentication done and succeeded */
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#define BOOT_API_CTX_AUTH_SUCCESS 0x2U
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/*
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* Possible value of boot context field 'boot_interface_sel'
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*/
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/* Value of field 'boot_interface_sel' when no boot occurred */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_NO 0x0U
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/* Boot occurred on SD */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD 0x1U
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/* Boot occurred on EMMC */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC 0x2U
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/* Boot occurred on FMC */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC 0x3U
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/* Boot occurred on OSPI NOR */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI 0x4U
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/* Boot occurred on UART */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART 0x5U
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/* Boot occurred on USB */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB 0x6U
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/* Boot occurred on OSPI NAND */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI 0x7U
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/* Boot occurred on HyperFlash QSPI */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_HYPERFLASH_OSPI 0x8U
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/*
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* Possible value of boot context field 'emmc_xfer_status'
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*/
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#define BOOT_API_CTX_EMMC_XFER_STATUS_NOT_STARTED 0x0U
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#define BOOT_API_CTX_EMMC_XFER_STATUS_DATAEND_DETECTED 0x1U
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#define BOOT_API_CTX_EMMC_XFER_STATUS_XFER_DATA_TIMEOUT 0x2U
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/*
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* Possible value of boot context field 'emmc_error_status'
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*/
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_NONE 0x0U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_CMD_TIMEOUT 0x1U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_TIMEOUT 0x2U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_DATA_CRC_FAIL 0x3U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_NOT_ENOUGH_BOOT_DATA_RX 0x4U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_NOT_FOUND 0x5U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_SIZE_ZERO 0x6U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_IMAGE_NOT_COMPLETE 0x7U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_ERROR 0x8U
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/* Definitions relative to 'p_rom_version_info->platform_type_ver' field */
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#define BOOT_API_CTX_ROM_VERSION_PLAT_VER_IC_EMU_FPGA 0xAA
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#define BOOT_API_CTX_ROM_VERSION_PLAT_VER_FPGA_ONLY 0xBB
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/* Image Header related definitions */
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/* Definition of header version */
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#define BOOT_API_HEADER_VERSION 0x00020000U
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/*
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* Magic number used to detect header in memory
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* Its value must be 'S' 'T' 'M' 0x32, i.e 0x324D5453 as field
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* 'bootapi_image_header_t.magic'
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* This identifies the start of a boot image.
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*/
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#define BOOT_API_IMAGE_HEADER_MAGIC_NB 0x324D5453U
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/* Definitions related to Authentication used in image header structure */
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#define BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES 64
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#define BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES 64
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#define BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES 32
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/* Possible values of the field 'boot_api_image_header_t.ecc_algo_type' */
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#define BOOT_API_ECDSA_ALGO_TYPE_P256NIST 1
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#define BOOT_API_ECDSA_ALGO_TYPE_BRAINPOOL256 2
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/*
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* Extension headers related definitions
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*/
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/* 'bootapi_image_header_t.extension_flag' used for authentication feature */
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#define BOOT_API_AUTHENTICATION_EXTENSION_BIT BIT(0)
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/* 'bootapi_image_header_t.extension_flag' used for FSBL decryption feature */
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#define BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT BIT(1)
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/* 'bootapi_image_header_t.extension_flag' used for padding header feature */
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#define BOOT_API_PADDING_EXTENSION_BIT BIT(31)
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/*
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* mask of bits of field 'bootapi_image_header_t.extension_flag'
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* used for extension headers
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*/
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#define BOOT_API_ALL_EXTENSIONS_MASK \
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(BOOT_API_AUTHENTICATION_EXTENSION_BIT | \
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BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT | \
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BOOT_API_PADDING_EXTENSION_BIT)
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/*
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* Magic number of FSBL decryption extension header
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* The value shall gives the four bytes 'S','T',0x00,0x01 in memory
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*/
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#define BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB 0x01005453U
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/*
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* Magic number of PKH revocation extension header
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* The value shall gives the four bytes 'S','T',0x00,0x02 in memory
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*/
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#define BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB 0x02005453U
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/* Max number of ECDSA public key hash in table */
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#define BOOT_API_AUTHENTICATION_NB_PKH_MAX 8U
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/* ECDSA public key hash table size in bytes */
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#define BOOT_API_AUTHENTICATION_TABLE_SIZE_BYTES \
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(BOOT_API_AUTHENTICATION_NB_PKH_MAX * \
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BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES)
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/*
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* Magic number of padding extension header
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* The value shall gives the four bytes 'S','T',0xFF,0xFF in memory
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*/
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#define BOOT_API_PADDING_HEADER_MAGIC_NB 0xFFFF5453U
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/*
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* Related to binaryType
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* 0x00: U-Boot
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* 0x10-0x1F: TF-A
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* 0x20-0X2F: OPTEE
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* 0x30: CM33 image
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*/
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#define BOOT_API_IMAGE_TYPE_UBOOT 0x0
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#define BOOT_API_IMAGE_TYPE_M33 0x30
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/*
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* Cores secure magic numbers
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* Constant to be stored in bakcup register
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* BOOT_API_MAGIC_NUMBER_TAMP_BCK_REG_IDX
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*/
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#define BOOT_API_A35_CORE0_MAGIC_NUMBER 0xCA7FACE0U
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#define BOOT_API_A35_CORE1_MAGIC_NUMBER 0xCA7FACE1U
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/*
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* TAMP_BCK9R register index
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* This register is used to write a Magic Number in order to restart
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* Cortex A35 Core 1 and make it execute @ branch address from TAMP_BCK5R
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*/
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#define BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX 9U
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/*
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* TAMP_BCK10R register index
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* This register is used to contain the branch address of
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* Cortex A35 Core 1 when restarted by a TAMP_BCK4R magic number writing
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*/
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#define BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX 10U
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/*
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* Possible value of boot context field 'hse_clock_value_in_hz'
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*/
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_UNDEFINED 0U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_19_2_MHZ 19200000U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_24_MHZ 24000000U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_25_MHZ 25000000U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_26_MHZ 26000000U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_40_MHZ 40000000U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_48_MHZ 48000000U
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/*
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* Possible value of boot context field 'boot_partition_used_toboot'
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*/
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#define BOOT_API_CTX_BOOT_PARTITION_UNDEFINED 0U
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/* Used FSBL1 to boot */
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#define BOOT_API_CTX_BOOT_PARTITION_FSBL1 1U
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/* Used FSBL2 to boot */
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#define BOOT_API_CTX_BOOT_PARTITION_FSBL2 2U
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#define BOOT_API_RETURN_OK 0x66U
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/*
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* Possible values of boot context field
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* 'ssp_config_ptr_in->ssp_cmd'
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*/
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/* 'K' 'B' 'U' 'P' -.> 'PUBK' */
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#define BOOT_API_CTX_SSP_CMD_CALC_CHIP_PUBK 0x4B425550
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/*
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* Exported types
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*/
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/*
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* bootROM version information structure definition
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* Total size = 24 bytes = 6 uint32_t
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*/
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typedef struct {
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/* Chip Version */
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uint32_t chip_ver;
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/* Cut version within a fixed chip version */
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uint32_t cut_ver;
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/* Version of ROM Mask within a fixed cut version */
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uint32_t rom_mask_ver;
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/* Internal Version of bootROM code */
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uint32_t bootrom_ver;
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/* Version of bootROM adapted */
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uint32_t for_chip_design_rtl_ver;
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/* Restriction on compiled platform when it applies */
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uint32_t platform_type_ver;
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} boot_api_rom_version_info_t;
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/*
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* Boot Context related definitions
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*/
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/*
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* Boot core boot configuration structure
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* Specifies all items of the secure boot configuration
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* Memory and peripheral part.
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*/
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typedef struct {
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/* Boot partition: ie FSBL partition on which the boot was successful */
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uint32_t boot_partition_used_toboot;
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uint32_t reserved1[3];
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/*
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* Information specific to an SD boot
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* Updated each time an SD boot is at least attempted,
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* even if not successful
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* Note : This is useful to understand why an SD boot failed
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* in particular
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*/
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uint32_t sd_err_internal_timeout_cnt;
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uint32_t sd_err_dcrc_fail_cnt;
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uint32_t sd_err_dtimeout_cnt;
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uint32_t sd_err_ctimeout_cnt;
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uint32_t sd_err_ccrc_fail_cnt;
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uint32_t sd_overall_retry_cnt;
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/*
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* Information specific to an eMMC boot
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* Updated each time an eMMC boot is at least attempted,
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* even if not successful
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* Note : This is useful to understand why an eMMC boot failed
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* in particular
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*/
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uint32_t emmc_xfer_status;
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uint32_t emmc_error_status;
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uint32_t emmc_nbbytes_rxcopied_tosysram_download_area;
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uint32_t reserved[4];
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/*
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* Boot interface used to boot : take values from defines
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* BOOT_API_CTX_BOOT_INTERFACE_SEL_XXX above
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*/
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uint16_t boot_interface_selected;
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uint16_t boot_interface_instance;
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uint32_t hse_clock_value_in_hz;
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uint32_t nand_fsbl_first_block;
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/*
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* Returned authentication status : take values from defines
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* BOOT_API_CTX_AUTH_XXX above
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*/
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uint32_t auth_status;
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/* Pointer on ROM constant containing ROM information */
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const boot_api_rom_version_info_t *p_rom_version_info;
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} __packed boot_api_context_t;
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|
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/*
|
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* Image Header related definitions
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*/
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||||
|
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/*
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* Structure used to define the common Header format used for FSBL, xloader,
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* ... and in particular used by bootROM for FSBL header readout.
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* FSBL header size is 256 Bytes = 0x100
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*/
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typedef struct {
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/* BOOT_API_IMAGE_HEADER_MAGIC_NB */
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uint32_t magic;
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uint8_t image_signature[BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES];
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/*
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* Checksum of payload
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* 32-bit sum all payload bytes considered as 8 bit unsigned
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* numbers, discarding any overflow bits.
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* Use to check UART/USB downloaded image integrity when signature
|
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* is not used
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*/
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uint32_t payload_checksum;
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/* Image header version : should have value BOOT_API_HEADER_VERSION */
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uint32_t header_version;
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/* Image length in bytes */
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uint32_t image_length;
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/*
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* Image Entry point address : should be in the SYSRAM area
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* and at least within the download area range
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*/
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uint32_t image_entry_point;
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/* Reserved */
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uint32_t reserved1;
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/*
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* Image load address : not used by bootROM but to be consistent
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* with header format for other packages (xloader, ...)
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*/
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uint32_t load_address;
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/* Reserved */
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uint32_t reserved2;
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/* Image version to be compared by bootROM with FSBL_A or FSBL_M version
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* counter value in OTP prior executing the downloaded image
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*/
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uint32_t image_version;
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/*
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* Extension flags :
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*
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* Bit 0 : Authentication extension header
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* value 0 : No signature check request
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* Bit 1 : Encryption extension header
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* Bit 2 : Padding extension header
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*/
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uint32_t extension_flags;
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/* Length in bytes of all extension headers */
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uint32_t extension_headers_length;
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/* Add binary type information */
|
||||
uint32_t binary_type;
|
||||
/* Pad up to 128 byte total size */
|
||||
uint8_t pad[16];
|
||||
/* Followed by extension header */
|
||||
uint8_t ext_header[];
|
||||
} __packed boot_api_image_header_t;
|
||||
|
||||
typedef uint8_t boot_api_sha256_t[BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES];
|
||||
|
||||
typedef struct {
|
||||
/* Extension header type:
|
||||
* BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB or
|
||||
* BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB
|
||||
* BOOT_API_PADDING_HEADER_MAGIC_NB
|
||||
*/
|
||||
uint32_t type;
|
||||
/* Extension header len in byte */
|
||||
uint32_t len;
|
||||
/* parameters of this extension */
|
||||
uint8_t params[];
|
||||
} __packed boot_extension_header_t;
|
||||
|
||||
typedef struct {
|
||||
/* Idx of ECDSA public key to be used in table */
|
||||
uint32_t pk_idx;
|
||||
/* Number of ECDSA public key in table */
|
||||
uint32_t nb_pk;
|
||||
/*
|
||||
* Type of ECC algorithm to use :
|
||||
* value 1 : for P-256 NIST algorithm
|
||||
* value 2 : for Brainpool 256 algorithm
|
||||
* See definitions 'BOOT_API_ECDSA_ALGO_TYPE_XXX' above.
|
||||
*/
|
||||
uint32_t ecc_algo_type;
|
||||
/* ECDSA public key to be used to check signature. */
|
||||
uint8_t ecc_pubk[BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES];
|
||||
/* table of Hash of Algo+ECDSA public key */
|
||||
boot_api_sha256_t pk_hashes[];
|
||||
} __packed boot_ext_header_params_authentication_t;
|
||||
|
||||
typedef struct {
|
||||
/* Size of encryption key (128 or 256) */
|
||||
uint32_t key_size;
|
||||
uint32_t derivation_cont;
|
||||
/* 128 msb bits of plain payload SHA256 */
|
||||
uint32_t hash[4];
|
||||
} __packed boot_ext_header_params_encrypted_fsbl_t;
|
||||
|
||||
#endif /* BOOT_API_H */
|
||||
13
plat/st/stm32mp2/include/plat_macros.S
Normal file
13
plat/st/stm32mp2/include/plat_macros.S
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_MACROS_S
|
||||
#define PLAT_MACROS_S
|
||||
|
||||
.macro plat_crash_print_regs
|
||||
.endm
|
||||
|
||||
#endif /* PLAT_MACROS_S */
|
||||
87
plat/st/stm32mp2/include/platform_def.h
Normal file
87
plat/st/stm32mp2/include/platform_def.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <arch.h>
|
||||
#include <lib/utils_def.h>
|
||||
#include <plat/common/common_def.h>
|
||||
|
||||
#include "../stm32mp2_def.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Generic platform constants
|
||||
******************************************************************************/
|
||||
|
||||
/* Size of cacheable stacks */
|
||||
#define PLATFORM_STACK_SIZE 0xC00
|
||||
|
||||
#define STM32MP_PRIMARY_CPU U(0x0)
|
||||
#define STM32MP_SECONDARY_CPU U(0x1)
|
||||
|
||||
#define MAX_IO_DEVICES U(4)
|
||||
#define MAX_IO_HANDLES U(4)
|
||||
#define MAX_IO_BLOCK_DEVICES U(1)
|
||||
#define MAX_IO_MTD_DEVICES U(1)
|
||||
|
||||
#define PLATFORM_CLUSTER_COUNT U(1)
|
||||
#define PLATFORM_CORE_COUNT U(2)
|
||||
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
|
||||
|
||||
#define PLAT_MAX_PWR_LVL U(5)
|
||||
#define PLAT_MAX_CPU_SUSPEND_PWR_LVL U(5)
|
||||
#define PLAT_NUM_PWR_DOMAINS U(7)
|
||||
|
||||
/* Local power state for power domains in Run state. */
|
||||
#define STM32MP_LOCAL_STATE_RUN U(0)
|
||||
/* Local power state for retention. */
|
||||
#define STM32MP_LOCAL_STATE_RET U(1)
|
||||
#define STM32MP_LOCAL_STATE_LP U(2)
|
||||
#define PLAT_MAX_RET_STATE STM32MP_LOCAL_STATE_LP
|
||||
/* Local power state for OFF/power-down. */
|
||||
#define STM32MP_LOCAL_STATE_OFF U(3)
|
||||
#define PLAT_MAX_OFF_STATE STM32MP_LOCAL_STATE_OFF
|
||||
|
||||
/* Macros to parse the state information from State-ID (recommended encoding) */
|
||||
#define PLAT_LOCAL_PSTATE_WIDTH U(4)
|
||||
#define PLAT_LOCAL_PSTATE_MASK GENMASK(PLAT_LOCAL_PSTATE_WIDTH - 1U, 0)
|
||||
|
||||
/*******************************************************************************
|
||||
* BL2 specific defines.
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
|
||||
* size plus a little space for growth.
|
||||
*/
|
||||
#define BL2_BASE STM32MP_BL2_BASE
|
||||
#define BL2_LIMIT (STM32MP_BL2_BASE + \
|
||||
STM32MP_BL2_SIZE)
|
||||
|
||||
/*******************************************************************************
|
||||
* BL33 specific defines.
|
||||
******************************************************************************/
|
||||
#define BL33_BASE STM32MP_BL33_BASE
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 33)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 33)
|
||||
|
||||
/*******************************************************************************
|
||||
* Declarations and constants to access the mailboxes safely. Each mailbox is
|
||||
* aligned on the biggest cache line size in the platform. This is known only
|
||||
* to the platform as it might have a combination of integrated and external
|
||||
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
|
||||
* line at any cache level. They could belong to different cpus/clusters &
|
||||
* get written while being protected by different locks causing corruption of
|
||||
* a valid mailbox address.
|
||||
******************************************************************************/
|
||||
#define CACHE_WRITEBACK_SHIFT 6
|
||||
#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
20
plat/st/stm32mp2/plat_bl2_mem_params_desc.c
Normal file
20
plat/st/stm32mp2/plat_bl2_mem_params_desc.c
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/desc_image_load.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Following descriptor provides BL image/ep information that gets used
|
||||
* by BL2 to load the images and also subset of this information is
|
||||
* passed to next BL image. The image loading sequence is managed by
|
||||
* populating the images in required loading order. The image execution
|
||||
* sequence is managed by populating the `next_handoff_image_id` with
|
||||
* the next executable image id.
|
||||
******************************************************************************/
|
||||
static bl_mem_params_node_t bl2_mem_params_descs[] = {
|
||||
};
|
||||
|
||||
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
|
||||
43
plat/st/stm32mp2/platform.mk
Normal file
43
plat/st/stm32mp2/platform.mk
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
#
|
||||
# Copyright (c) 2023, STMicroelectronics - All Rights Reserved
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
include plat/st/common/common.mk
|
||||
|
||||
CRASH_REPORTING := 1
|
||||
ENABLE_PIE := 1
|
||||
PROGRAMMABLE_RESET_ADDRESS := 1
|
||||
|
||||
# Default Device tree
|
||||
DTB_FILE_NAME ?= stm32mp257f-ev1.dtb
|
||||
|
||||
STM32MP25 := 1
|
||||
|
||||
# STM32 image header version v2.2
|
||||
STM32_HEADER_VERSION_MAJOR := 2
|
||||
STM32_HEADER_VERSION_MINOR := 2
|
||||
|
||||
# Number of TF-A copies in the device
|
||||
STM32_TF_A_COPIES := 2
|
||||
|
||||
# PLAT_PARTITION_MAX_ENTRIES must take care of STM32_TF-A_COPIES and other partitions
|
||||
# such as metadata (2) and fsbl-m (2) to find all the FIP partitions (default is 2).
|
||||
PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 6)))
|
||||
|
||||
# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI
|
||||
# Disable mbranch-protection to avoid adding useless code
|
||||
TF_CFLAGS += -mbranch-protection=none
|
||||
|
||||
# Include paths and source files
|
||||
PLAT_INCLUDES += -Iplat/st/stm32mp2/include/
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
|
||||
|
||||
BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
|
||||
BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c
|
||||
|
||||
include plat/st/common/common_rules.mk
|
||||
145
plat/st/stm32mp2/stm32mp2_def.h
Normal file
145
plat/st/stm32mp2/stm32mp2_def.h
Normal file
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef STM32MP2_DEF_H
|
||||
#define STM32MP2_DEF_H
|
||||
|
||||
#include <common/tbbr/tbbr_img_def.h>
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <drivers/st/bsec.h>
|
||||
#endif
|
||||
#include <dt-bindings/clock/stm32mp25-clks.h>
|
||||
#include <dt-bindings/clock/stm32mp25-clksrc.h>
|
||||
#include <dt-bindings/reset/stm32mp25-resets.h>
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <boot_api.h>
|
||||
#include <stm32mp_common.h>
|
||||
#include <stm32mp_dt.h>
|
||||
#include <stm32mp_shared_resources.h>
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP2 memory map related constants
|
||||
******************************************************************************/
|
||||
#define STM32MP_SYSRAM_BASE U(0x0E000000)
|
||||
#define STM32MP_SYSRAM_SIZE U(0x00040000)
|
||||
|
||||
#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
|
||||
#define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
|
||||
|
||||
/* DDR configuration */
|
||||
#define STM32MP_DDR_BASE U(0x80000000)
|
||||
#define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */
|
||||
|
||||
/* DDR power initializations */
|
||||
#ifndef __ASSEMBLER__
|
||||
enum ddr_type {
|
||||
STM32MP_DDR3,
|
||||
STM32MP_DDR4,
|
||||
STM32MP_LPDDR4
|
||||
};
|
||||
#endif
|
||||
|
||||
#define STM32MP_BL2_SIZE U(0x0002A000) /* 168 KB for BL2 */
|
||||
|
||||
#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
|
||||
STM32MP_SEC_SYSRAM_SIZE - \
|
||||
STM32MP_BL2_SIZE)
|
||||
|
||||
/* BL2 and BL32/sp_min require 4 tables */
|
||||
#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
|
||||
|
||||
/*
|
||||
* MAX_MMAP_REGIONS is usually:
|
||||
* BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup
|
||||
*/
|
||||
#define MAX_MMAP_REGIONS 6
|
||||
|
||||
#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000))
|
||||
#define STM32MP_BL33_MAX_SIZE U(0x400000)
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP2 RCC
|
||||
******************************************************************************/
|
||||
#define RCC_BASE U(0x44200000)
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP2 PWR
|
||||
******************************************************************************/
|
||||
#define PWR_BASE U(0x44210000)
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP2 SDMMC
|
||||
******************************************************************************/
|
||||
#define STM32MP_SDMMC1_BASE U(0x48220000)
|
||||
#define STM32MP_SDMMC2_BASE U(0x48230000)
|
||||
#define STM32MP_SDMMC3_BASE U(0x48240000)
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP2 TAMP
|
||||
******************************************************************************/
|
||||
#define PLAT_MAX_TAMP_INT U(5)
|
||||
#define PLAT_MAX_TAMP_EXT U(3)
|
||||
#define TAMP_BASE U(0x46010000)
|
||||
#define TAMP_SMCR (TAMP_BASE + U(0x20))
|
||||
#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
|
||||
#define TAMP_BKP_REG_CLK CK_BUS_RTC
|
||||
#define TAMP_BKP_SEC_NUMBER U(10)
|
||||
#define TAMP_COUNTR U(0x40)
|
||||
|
||||
#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
|
||||
static inline uintptr_t tamp_bkpr(uint32_t idx)
|
||||
{
|
||||
return TAMP_BKP_REGISTER_BASE + (idx << 2);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP2 DDRCTRL
|
||||
******************************************************************************/
|
||||
#define DDRCTRL_BASE U(0x48040000)
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP2 DDRDBG
|
||||
******************************************************************************/
|
||||
#define DDRDBG_BASE U(0x48050000)
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP2 DDRPHYC
|
||||
******************************************************************************/
|
||||
#define DDRPHYC_BASE U(0x48C00000)
|
||||
|
||||
/*******************************************************************************
|
||||
* Miscellaneous STM32MP1 peripherals base address
|
||||
******************************************************************************/
|
||||
#define BSEC_BASE U(0x44000000)
|
||||
#define DBGMCU_BASE U(0x4A010000)
|
||||
#define HASH_BASE U(0x42010000)
|
||||
#define RTC_BASE U(0x46000000)
|
||||
#define STGEN_BASE U(0x48080000)
|
||||
#define SYSCFG_BASE U(0x44230000)
|
||||
|
||||
/*******************************************************************************
|
||||
* REGULATORS
|
||||
******************************************************************************/
|
||||
/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
|
||||
#define PLAT_NB_RDEVS U(19)
|
||||
/* 2 FIXED */
|
||||
#define PLAT_NB_FIXED_REGUS U(2)
|
||||
/* No GPIO regu */
|
||||
#define PLAT_NB_GPIO_REGUS U(0)
|
||||
|
||||
/*******************************************************************************
|
||||
* Device Tree defines
|
||||
******************************************************************************/
|
||||
#define DT_BSEC_COMPAT "st,stm32mp25-bsec"
|
||||
#define DT_DDR_COMPAT "st,stm32mp2-ddr"
|
||||
#define DT_PWR_COMPAT "st,stm32mp25-pwr"
|
||||
#define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
|
||||
#define DT_UART_COMPAT "st,stm32h7-uart"
|
||||
|
||||
#endif /* STM32MP2_DEF_H */
|
||||
Loading…
Add table
Reference in a new issue