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https://github.com/ARM-software/arm-trusted-firmware.git
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e5839ed79e
To be able to boot, STM32MPU platforms require the BL2 binary (together with its DT) to be preceded with an STM32 header. Add the required files and macro to properly generate this header. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I675de2c5cb733fe9d9e9baf76a941741a06dfac8
222 lines
7.7 KiB
C
222 lines
7.7 KiB
C
/*
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* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP2_DEF_H
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#define STM32MP2_DEF_H
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#include <common/tbbr/tbbr_img_def.h>
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#ifndef __ASSEMBLER__
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#include <drivers/st/bsec.h>
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#endif
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#include <drivers/st/stm32mp25_rcc.h>
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#include <dt-bindings/clock/stm32mp25-clks.h>
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#include <dt-bindings/clock/stm32mp25-clksrc.h>
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#include <dt-bindings/reset/stm32mp25-resets.h>
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#ifndef __ASSEMBLER__
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#include <boot_api.h>
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#include <stm32mp_common.h>
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#include <stm32mp_dt.h>
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#include <stm32mp_shared_resources.h>
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#endif
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/*******************************************************************************
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* STM32MP2 memory map related constants
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******************************************************************************/
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#define STM32MP_SYSRAM_BASE U(0x0E000000)
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#define STM32MP_SYSRAM_SIZE U(0x00040000)
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#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
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#define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
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/* DDR configuration */
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#define STM32MP_DDR_BASE U(0x80000000)
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#define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */
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/* DDR power initializations */
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#ifndef __ASSEMBLER__
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enum ddr_type {
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STM32MP_DDR3,
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STM32MP_DDR4,
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STM32MP_LPDDR4
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};
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#endif
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/* Section used inside TF binaries */
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#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
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/* 512 Octets reserved for header */
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#define STM32MP_HEADER_SIZE U(0x00000200)
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#define STM32MP_HEADER_BASE (STM32MP_SEC_SYSRAM_BASE + \
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STM32MP_PARAM_LOAD_SIZE)
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/* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
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#define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
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#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
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STM32MP_PARAM_LOAD_SIZE + \
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STM32MP_HEADER_SIZE)
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#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
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(STM32MP_PARAM_LOAD_SIZE + \
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STM32MP_HEADER_SIZE))
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#define STM32MP_BL2_SIZE U(0x0002A000) /* 168 KB for BL2 */
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#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
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STM32MP_SEC_SYSRAM_SIZE - \
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STM32MP_BL2_SIZE)
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/* BL2 and BL32/sp_min require 4 tables */
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#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
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/*
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* MAX_MMAP_REGIONS is usually:
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* BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup
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*/
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#define MAX_MMAP_REGIONS 6
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/* DTB initialization value */
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#define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
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#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
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STM32MP_BL2_DTB_SIZE)
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#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000))
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#define STM32MP_BL33_MAX_SIZE U(0x400000)
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/*******************************************************************************
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* STM32MP2 RCC
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******************************************************************************/
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#define RCC_BASE U(0x44200000)
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/*******************************************************************************
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* STM32MP2 PWR
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******************************************************************************/
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#define PWR_BASE U(0x44210000)
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/*******************************************************************************
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* STM32MP2 GPIO
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******************************************************************************/
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#define GPIOA_BASE U(0x44240000)
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#define GPIOB_BASE U(0x44250000)
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#define GPIOC_BASE U(0x44260000)
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#define GPIOD_BASE U(0x44270000)
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#define GPIOE_BASE U(0x44280000)
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#define GPIOF_BASE U(0x44290000)
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#define GPIOG_BASE U(0x442A0000)
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#define GPIOH_BASE U(0x442B0000)
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#define GPIOI_BASE U(0x442C0000)
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#define GPIOJ_BASE U(0x442D0000)
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#define GPIOK_BASE U(0x442E0000)
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#define GPIOZ_BASE U(0x46200000)
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#define GPIO_BANK_OFFSET U(0x10000)
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#define STM32MP_GPIOS_PIN_MAX_COUNT 16
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#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
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/*******************************************************************************
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* STM32MP2 UART
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******************************************************************************/
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#define USART1_BASE U(0x40330000)
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#define USART2_BASE U(0x400E0000)
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#define USART3_BASE U(0x400F0000)
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#define UART4_BASE U(0x40100000)
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#define UART5_BASE U(0x40110000)
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#define USART6_BASE U(0x40220000)
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#define UART7_BASE U(0x40370000)
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#define UART8_BASE U(0x40380000)
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#define UART9_BASE U(0x402C0000)
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#define STM32MP_NB_OF_UART U(9)
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/* For UART crash console */
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#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
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/* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */
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#define STM32MP_DEBUG_USART_BASE USART2_BASE
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#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE
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#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR
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#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN
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#define DEBUG_UART_TX_GPIO_PORT 4
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#define DEBUG_UART_TX_GPIO_ALTERNATE 6
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#define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR
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#define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI
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#define DEBUG_UART_TX_EN_REG RCC_USART2CFGR
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#define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN
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#define DEBUG_UART_RST_REG RCC_USART2CFGR
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#define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST
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#define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR
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#define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR
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/*******************************************************************************
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* STM32MP2 SDMMC
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******************************************************************************/
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#define STM32MP_SDMMC1_BASE U(0x48220000)
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#define STM32MP_SDMMC2_BASE U(0x48230000)
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#define STM32MP_SDMMC3_BASE U(0x48240000)
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/*******************************************************************************
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* STM32MP2 TAMP
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******************************************************************************/
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#define PLAT_MAX_TAMP_INT U(5)
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#define PLAT_MAX_TAMP_EXT U(3)
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#define TAMP_BASE U(0x46010000)
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#define TAMP_SMCR (TAMP_BASE + U(0x20))
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#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
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#define TAMP_BKP_REG_CLK CK_BUS_RTC
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#define TAMP_BKP_SEC_NUMBER U(10)
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#define TAMP_COUNTR U(0x40)
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#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
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static inline uintptr_t tamp_bkpr(uint32_t idx)
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{
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return TAMP_BKP_REGISTER_BASE + (idx << 2);
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}
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#endif
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/*******************************************************************************
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* STM32MP2 DDRCTRL
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******************************************************************************/
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#define DDRCTRL_BASE U(0x48040000)
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/*******************************************************************************
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* STM32MP2 DDRDBG
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******************************************************************************/
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#define DDRDBG_BASE U(0x48050000)
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/*******************************************************************************
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* STM32MP2 DDRPHYC
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******************************************************************************/
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#define DDRPHYC_BASE U(0x48C00000)
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/*******************************************************************************
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* Miscellaneous STM32MP1 peripherals base address
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******************************************************************************/
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#define BSEC_BASE U(0x44000000)
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#define DBGMCU_BASE U(0x4A010000)
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#define HASH_BASE U(0x42010000)
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#define RTC_BASE U(0x46000000)
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#define STGEN_BASE U(0x48080000)
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#define SYSCFG_BASE U(0x44230000)
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/*******************************************************************************
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* REGULATORS
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******************************************************************************/
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/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
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#define PLAT_NB_RDEVS U(19)
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/* 2 FIXED */
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#define PLAT_NB_FIXED_REGUS U(2)
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/* No GPIO regu */
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#define PLAT_NB_GPIO_REGUS U(0)
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/*******************************************************************************
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* Device Tree defines
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******************************************************************************/
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#define DT_BSEC_COMPAT "st,stm32mp25-bsec"
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#define DT_DDR_COMPAT "st,stm32mp2-ddr"
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#define DT_PWR_COMPAT "st,stm32mp25-pwr"
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#define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
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#define DT_UART_COMPAT "st,stm32h7-uart"
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#endif /* STM32MP2_DEF_H */
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