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Merge "chore: remove MULTI_CONSOLE_API references" into integration

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This commit is contained in:
Joanna Farley 2023-09-19 14:48:43 +02:00 • committed by TrustedFirmware Code Review
commit 455cd0d3b5
15 changed files with 0 additions and 25 deletions
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5
docs/plat/rpi3.rst
View file

@ -296,11 +296,6 @@ The following is not currently supported:
address by changing the file ``armstub8.bin``, so there's no point in using
TF-A in this case.
- ``MULTI_CONSOLE_API=0``: The multi console API must be enabled. Note that the
crash console uses the internal 16550 driver functions directly in order to be
able to print error messages during early crashes before setting up the
multi console API.
Building the firmware for kernels that don't support PSCI
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

2
plat/arm/board/a5ds/platform.mk
View file

@ -102,8 +102,6 @@ ifeq (${AARCH32_SP},none)
$(error Variable AARCH32_SP has to be set for AArch32)
endif
MULTI_CONSOLE_API := 1
ARM_DISABLE_TRUSTED_WDOG := 1
PLAT_BL_COMMON_SOURCES += lib/xlat_tables/aarch32/nonlpae_tables.c

1
plat/imx/imx7/picopi/platform.mk
View file

@ -34,7 +34,6 @@ SEPARATE_CODE_AND_RODATA := 1
USE_COHERENT_MEM := 1
# Use multi console API
MULTI_CONSOLE_API := 1
PLAT_PICOPI_UART :=5
$(eval $(call add_define,PLAT_PICOPI_UART))

1
plat/intel/soc/agilex/platform.mk
View file

@ -79,5 +79,4 @@ BL31_SOURCES += \
PROGRAMMABLE_RESET_ADDRESS := 0
RESET_TO_BL2 := 1
BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1
USE_COHERENT_MEM := 1

1
plat/intel/soc/agilex5/platform.mk
View file

@ -104,4 +104,3 @@ $(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
PROGRAMMABLE_RESET_ADDRESS := 0
RESET_TO_BL2 := 1
BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1

1
plat/intel/soc/n5x/platform.mk
View file

@ -49,5 +49,4 @@ BL31_SOURCES += \
PROGRAMMABLE_RESET_ADDRESS := 0
RESET_TO_BL2 := 1
BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1
USE_COHERENT_MEM := 1

1
plat/mediatek/common/common_config.mk
View file

@ -6,7 +6,6 @@
# indicate the reset vector address can be programmed
PROGRAMMABLE_RESET_ADDRESS := 1
MULTI_CONSOLE_API := 1
COLD_BOOT_SINGLE_CPU := 1
# Build flag to include AArch32 registers in cpu context save and restore during
# world switch. This flag must be set to 0 for AArch64-only platforms.

2
plat/mediatek/mt8173/platform.mk
View file

@ -71,5 +71,3 @@ $(eval $(call add_define,MTK_SIP_SET_AUTHORIZED_SECURE_REG_ENABLE))
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
MULTI_CONSOLE_API := 1

2
plat/mediatek/mt8183/platform.mk
View file

@ -81,8 +81,6 @@ PROGRAMMABLE_RESET_ADDRESS := 1
COLD_BOOT_SINGLE_CPU := 1
MULTI_CONSOLE_API := 1
MACH_MT8183 := 1
$(eval $(call add_define,MACH_MT8183))

1
plat/qemu/qemu_sbsa/platform.mk
View file

@ -7,7 +7,6 @@
PLAT_QEMU_PATH := plat/qemu/qemu_sbsa
PLAT_QEMU_COMMON_PATH := plat/qemu/common
MULTI_CONSOLE_API := 1
CRASH_REPORTING := 1
# Disable the PSCI platform compatibility layer

2
plat/qti/sc7180/platform.mk
View file

@ -32,8 +32,6 @@ PROGRAMMABLE_RESET_ADDRESS := 1
RESET_TO_BL31 := 0
MULTI_CONSOLE_API := 1
QTI_SDI_BUILD := 0
$(eval $(call assert_boolean,QTI_SDI_BUILD))
$(eval $(call add_define,QTI_SDI_BUILD))

2
plat/qti/sc7280/platform.mk
View file

@ -35,8 +35,6 @@ PROGRAMMABLE_RESET_ADDRESS := 1
RESET_TO_BL31 := 0
MULTI_CONSOLE_API := 1
QTI_SDI_BUILD := 0
$(eval $(call assert_boolean,QTI_SDI_BUILD))
$(eval $(call add_define,QTI_SDI_BUILD))

1
plat/renesas/common/common.mk
View file

@ -12,7 +12,6 @@ RESET_TO_BL31 := 1
GENERATE_COT := 1
RESET_TO_BL2 := 1
ENABLE_SVE_FOR_NS := 0
MULTI_CONSOLE_API := 1
CRASH_REPORTING := 1
HANDLE_EA_EL3_FIRST_NS := 1

1
plat/rockchip/px30/platform.mk
View file

@ -64,7 +64,6 @@ BL31_SOURCES += ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c
endif
ENABLE_PLAT_COMPAT := 0
MULTI_CONSOLE_API := 1
include lib/libfdt/libfdt.mk

2
plat/rockchip/rk3288/platform.mk
View file

@ -56,8 +56,6 @@ BL32_SOURCES += ${RK_GIC_SOURCES} \
${RK_PLAT_SOC}/drivers/secure/secure.c \
${RK_PLAT_SOC}/drivers/soc/soc.c \
MULTI_CONSOLE_API := 1
include lib/coreboot/coreboot.mk
include lib/libfdt/libfdt.mk