We're a bit inconsistent about which tool we use to preprocess source
files; in some places we use `$(CC) -E` whilst in others we use `cpp`.
This change forces all invocations of the C preprocessor to use the
first scheme, which ensures that the preprocessor behaves the same way
as the C compiler used when compiling C source files.
Change-Id: Iede2f25ff86ea8b43d7a523e32648058d5023832
Signed-off-by: Chris Kay <chris.kay@arm.com>
The `rzg_layout_create` and `rcar_layout_create` tools have a rule to
build object files from C files, but it depends on object files in the
parent directory when it should depend on object files in the current
directory. Consequently, the rule is not triggering and the implicit C
compilation rule is executed instead. This rule works, so I have
replaced the broken rule with exactly the same command as what the
implicit rule is executing and fixed the dependency.
Change-Id: Ib8d640361adff8c4d660738dda230e5536bec629
Signed-off-by: Chris Kay <chris.kay@arm.com>
* changes:
feat(stm32mp2): put back core 1 in wfi after debugger's halt
feat(stm32mp2): add plat_my_core_pos
fix(stm32mp2): correct early/crash console init
Add support for FFA_CONSOLE_LOG in EL3 SPMC,
Disallow forwarding FFA_CONSOLE_LOG across worlds.
Add support for FFA_CONSOLE_LOG in FFA_FEATURES.
Input parameters:
w0/x0 - FFA_CONSOLE_LOG_32/64
w1/x1 - Character count
w2/x2-w7/x7 - 24 or 48 characters depending upon whether a SMC32 or
SMC64 FID was used.
Output parameters in case of success:
w0/x0 - FFA_SUCCESS
Output parameters in case of error:
w0/x0 - FFA_ERROR
w2/x2 - NOT_SUPPORTED: ABI is not implemented
INVALID_PARAMETERS: Parameters are incorrectly encoded
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I004c043729e77d1b9aa396c42d25c73d9268169a
Coverity Scan reminded that we need to take care of MPIDR properly.
We need to make sure that we get MPIDR values from QEMU.
No MPIDR == panic() in case which should not happen.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Idb5fe7d958f0bcecd3d66a643743f478538f4a8b
The core 1 is put in wfi for pen holding. If a debugger halts the
core, it causes the core to exit from wfi.
Let the core to jump back in wfi when the debugger resumes the
core's execution.
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Change-Id: I9b5607b05cdcde905dc4047af8d6f1292d53d701
This function is required, at least for bakery locks.
Change-Id: I28906c50e0a0ebff5d387a424247513ec1a599fc
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The former code, using x2 register, was removing the LPEN bit from UART
config register. So the UART clock is stopped as soon as the CA35 is in
CSleep. It was then displaying crap in Linux console.
The ands check instruction is replaced with a clearer tst instruction
directly with the bit to be tested.
Change-Id: I8a2b3ab195981dee2962e0c2f5d501d5933c17f4
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Calculate the free space as the range between the
limit and the end of the memory region *_REGION_END.
Change-Id: I9cacadea2543c9f5ddaebca82344a83678cd7d55
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
The FF-A specification has made it such that SPs
may optionally specify their load address in the manifest.
This info was being retrieved to generate some information
for the SPMC manifest. However, it is not a mandatory utility.
This change relaxes the case in which the SP manifest doesn't
have a load address.
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ic4c1b1ec6666522900c113903be45ba0eb5d0bf6
QEMU provides us with minimal information about hardware platform using
minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even
a firmware DeviceTree.
Change-Id: I7b6cc5f53a4f78a9ed69bc7fc2fa1a69ea65428d
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
We want to remove use of DeviceTree from EDK2. So we move
functions to TF-A:
- counting cpu cores
- checking NUMA node id
- checking MPIDR
And then it gets passed to EDK2 via SMC calls.
Change-Id: I1c7fc234ba90ba32433b6e4aa2cf127f26da00fd
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
EL2 registers are 8 byte wide and are allocated continuous memory.
After moving MPAM_EL2 registers out of the EL2 struct, the section
of memory, assigned to MPAM registers in EL2 registers structure has
to be removed.
Henceforth, this patch addresses this issue and cleans up the unsued memory.
Change-Id: I3425b43add0755ff1f5cb803cd5fa667082e7814
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* changes:
fix(rotpk): move rotpk definitions out of arm_def.h
feat(cpu): add support for Poseidon V CPU
fix(cpu): correct variant name for default Poseidon CPU
fix(rmmd): avoid TRP when external RMM is defined
The TF-A does have a official PRELOADED_BL33_BASE define which is used
to tell the TF-A where to jump and that no bl33 loading is requied. Use
this to make the platform specific PLAT_NS_IMAGE_OFFSET configurable.
This becomes necessary if one would like to place the bl33 code to other
places.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I9d462c0e9df8e6d2ad78ee770bfa59e680739a51
* changes:
feat(qemu): support TRP for RME
feat(qemu): load and run RMM image
feat(qemu): setup Granule Protection Table
feat(qemu): setup memory map for RME
feat(qemu): update mapping types for RME
feat(qemu): use mock attestation functions for RME
fix(qemu): increase max FIP size
When an external RMM is not provided during make invocation, include the
Test Realm Payload (TRP) to the FIP.
Change-Id: I15d396cf268a08d79da63075aadb4172238eb225
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
When RME is enabled, jump to the RMM image before BL33. When using
semihosting rather than FIP, the image called "rmm.bin" is loaded from
the runtime directory.
Change-Id: I15863410b1e505aa502276b339b22a2ddcb0b745
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
When RME is enabled, call the GPT library to setup the granule
protection tables and partition the physical address space.
Change-Id: Ib466c4579ff55fcff9307550e6d26d432674779a
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reserve some space in DRAM for RMM, and some space in SRAM for the GPT
tables. Create the page table mappings.
Change-Id: I3822e7e505e86eb0fa15b1b5b6298e4122b17181
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
With RME, mappings for EL3 use MT_ROOT rather than MT_SECURE. Update the
mapping types to select the right memory type: EL3_PAS is MT_ROOT when
RME is enabled, MT_SECURE otherwise.
Change-Id: I93e287009515b64e833a6f69545766be4c87e473
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Since QEMU doesn't yet emulate hardware attestation, provide hardcoded
key and token to demonstrate attestation for RME. They are copied from
the mock values for the FVP platform.
Change-Id: I9ce686955345854e9409af5c3aad2a648adea226
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
The max FIP size for the QEMU virt platform is currently 4MB, which
isn't enough when including a RMM in the FIP. Since the secure flash
size is actually 64MB, we can significantly increase the max FIP size.
Change-Id: Id2b5df355f8d4c90a41fec66f180e46eb7bab9f8
Fixes: a886bbeceb ("qemu: Update flash address map to keep FIP in secure FLASH0")
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
The file arm_def.h currently contains common definitions used by ARM
platforms. However, some platforms may have their own definitions,
allowing them to avoid a direct dependency on arm_def.h. For a clean
platform port of arm_def.h, none of the source files should directly
include arm_def.h; instead, they should include the platform header
which would indirectly include the required definitions.
Presently, the rotpk module has a source file that directly includes
arm_def.h. This could lead to compilation issues if the platform
incorporating the rotpk module has a separate implementation of some or
all of the definitions in arm_def.h file. To address this, move the
relevant definitions out of arm_def.h and into rotpk_def.h.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I9e8b0d319391f9a167af5c69a7b2d42ac488e7b4
Enable support for Poseidon V CPUs. Poseidon V CPUs are distinguished by
a 3MB L2 cache, differing from Poseidon VN(AE) CPUs with a 2MB L2 cache.
This enhancement ensures compatibility with RD-Fremont and similar
platforms utilizing Poseidon V CPUs.
CC: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Icdcc5f57c62855b2ec54c58a401d3bf09f292189
Update the Poseidon CPU variant name to "POSEIDON VNAE" in alignment
with the MIDR 0x410FD830. This adjustment reflects the accurate
designation for the default Poseidon CPU and allows for seamless support
of other variants in the future.
CC: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I48183290ffc2889d6ae000d3aa423c0ee5e4d211
The Test Realm Package (TRP) is a small payload that runs at R-EL2 if an
external RMM image path is not provided. Currently, the TRP makefile is
included if RME is enabled, regardless of whether an external RMM
image path is defined or not. This fix ensures that TRP is included
only when an external RMM path is not defined.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I3cc3d2a636e65071e45c5c82cc125290887ffc09
The code in the AMD-Xilinx platform for Versal and Versal NET is being
refactored to move the plat_get_syscnt_freq2() function to a common
file. This common function is utilized for obtaining the CPU clock
frequency from the platform.
Change-Id: I7a4c3fa43a2941d51cacd259c57b24e545aea848
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Refactor, the macro named VERSAL_NET_IOU_SCNTRS is being renamed to a more
generic macro name, which will be used in common code to enable reuse
across various platforms.
Change-Id: I548437e0fe2d73b196468bc92029f8099ea1f8d1
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Refactor the system counter configuration into the
syscnt_freq_config_setup() function as it involves timestamp and
system counter configuration, which requires early configuration for
clock setup and read the value of the IOU_SCNTRS_BASE_FREQ register
using mmio_read_32() to determine the counter frequency.
If the counter frequency is zero, the system will set the default CPU
clocks constants in TF-A and displays message. However, if the counter
frequency is non-zero, the program will return the value stored in the
IOU_SCNTRS_BASE_FREQ register.
The issue lies in dcc_status_timeout(),function verifying timeout
status, particularly within timeout_cnt_us2cnt(), converting
microseconds to counter ticks using read_cntfrq_el0(), which returns
zero. timeout_elapsed() then checks if the current counter from
read_cntpct_el0() exceeds the expiration count, reached to timeout.
After the function set_cnt_freq() writes into the counter frequency
register, the function timeout_cnt_us2cnt() is used to obtain the
appropriate counter ticks. Subsequently, the function timeout_elapsed()
checks whether the current counter value read_cntpct_el0() has
exceeded the specified expiration count. If it has, this indicates
that the timeout has lapsed.
Change-Id: Ib9ed3493d22f23c832f8bb7d11c4f727fe1ebe3c
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
The set_cnt_freq() function is introduced to configure the counter
frequency register.If the counter frequency register is zero, it writes
the output of plat_get_syscnt_freq2() the cpu_clocks to the counter
frequency register.
According to the design specifications provided for Versal, the
lpd_data.cdo file contains a mask_write operation for register
0xFF140020 (base_frequency_ID_register) to set it to 0x5f5e100,
configuring it for a 100MHz clock frequency.
Reading the value of the IOU_SCNTRS_BASE_FREQ register using
mmio_read_32() to determine the counter frequency. If the counter
frequency is zero, the system will set the default CPU clocks constants
in TF-A and displays message. However, if the counter frequency is
non-zero, the program will return the value stored in the
IOU_SCNTRS_BASE_FREQ register.
The issue lies in dcc_status_timeout(),function verifying timeout
status, particularly within timeout_cnt_us2cnt(), converting
microseconds to counter ticks using read_cntfrq_el0(), which returns
zero. timeout_elapsed() then checks if the current counter from
read_cntpct_el0()exceeds the expiration count, denoting timeout.
After the function set_cnt_freq() writes into the counter frequency
register, the function timeout_cnt_us2cnt() is used to obtain the
appropriate counter ticks. Subsequently, the function timeout_elapsed()
checks whether the current counter value read_cntpct_el0() has
exceeded the specified expiration count. If it has, this indicates
that the timeout has lapsed.
Change-Id: I8f2f4d804b5aefa6f92083d831a5ebfade384294
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Use unsigned long values for __aarch64__ version of SZ_* macros.
This allows using masks with ~SZ_* without losing the 32 upper bits.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ie485fad65088df17e6c489ebb3159220d6add647
This patch provides a reporting functionality to display the memory
consumed by the context in each security state and for each exception
level. Flag PLATFORM_REPORT_CTX_MEM_USE enables or disables this
feature.
Change-Id: I1515366bf87561dcedf2b3206be167804df681d4
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
New build option CTX_INCLUDE_MPAM_REGS is added to select
if the firmware needs to save the MPAM EL2 registers during world
switches. This option is currently disabled as MPAM is only
enabled for NS world.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie2e5e184cdb65f7e1a98d8fe81590253fd859679
* changes:
feat(intel): support QSPI ECC Linux for Agilex
feat(intel): support QSPI ECC Linux for N5X
feat(intel): support QSPI ECC Linux for Stratix10
feat(intel): add in QSPI ECC for Linux
