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feat(cpu): add support for Poseidon V CPU

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Enable support for Poseidon V CPUs. Poseidon V CPUs are distinguished by
a 3MB L2 cache, differing from Poseidon VN(AE) CPUs with a 2MB L2 cache.
This enhancement ensures compatibility with RD-Fremont and similar
platforms utilizing Poseidon V CPUs.

CC: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Icdcc5f57c62855b2ec54c58a401d3bf09f292189
This commit is contained in:
Rohit Mathew 2023-12-15 12:50:58 +00:00
parent 61a29682c6
commit b77f55d6c7
2 changed files with 5 additions and 0 deletions
include/lib/cpus/aarch64
neoverse_poseidon.h
lib/cpus/aarch64
neoverse_poseidon.S

1
include/lib/cpus/aarch64/neoverse_poseidon.h
View file

@ -9,6 +9,7 @@
#define NEOVERSE_POSEIDON_VNAE_MIDR U(0x410FD830)
#define NEOVERSE_POSEIDON_V_MIDR U(0x410FD840)
/* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */
#define NEOVERSE_POSEIDON_BHB_LOOP_COUNT U(132)

4
lib/cpus/aarch64/neoverse_poseidon.S
View file

@ -84,3 +84,7 @@ endfunc neoverse_poseidon_cpu_reg_dump
declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_VNAE_MIDR, \
neoverse_poseidon_reset_func, \
neoverse_poseidon_core_pwr_dwn
declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_V_MIDR, \
neoverse_poseidon_reset_func, \
neoverse_poseidon_core_pwr_dwn