fix(cpu): correct variant name for default Poseidon CPU

Update the Poseidon CPU variant name to "POSEIDON VNAE" in alignment
with the MIDR 0x410FD830. This adjustment reflects the accurate
designation for the default Poseidon CPU and allows for seamless support
of other variants in the future.

CC: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I48183290ffc2889d6ae000d3aa423c0ee5e4d211
This commit is contained in:
Rohit Mathew 2023-12-15 12:40:41 +00:00
parent 57bc3c4056
commit 61a29682c6
2 changed files with 4 additions and 4 deletions

View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, Arm Limited. All rights reserved.
* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -8,7 +8,7 @@
#define NEOVERSE_POSEIDON_H
#define NEOVERSE_POSEIDON_MIDR U(0x410FD830)
#define NEOVERSE_POSEIDON_VNAE_MIDR U(0x410FD830)
/* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */
#define NEOVERSE_POSEIDON_BHB_LOOP_COUNT U(132)

View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, Arm Limited. All rights reserved.
* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -81,6 +81,6 @@ func neoverse_poseidon_cpu_reg_dump
ret
endfunc neoverse_poseidon_cpu_reg_dump
declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_MIDR, \
declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_VNAE_MIDR, \
neoverse_poseidon_reset_func, \
neoverse_poseidon_core_pwr_dwn