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fix(stm32mp2): correct early/crash console init

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The former code, using x2 register, was removing the LPEN bit from UART
config register. So the UART clock is stopped as soon as the CA35 is in
CSleep. It was then displaying crap in Linux console.
The ands check instruction is replaced with a clearer tst instruction
directly with the bit to be tested.

Change-Id: I8a2b3ab195981dee2962e0c2f5d501d5933c17f4
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier 2024-01-10 16:28:20 +01:00 • committed by Yann Gautier
parent e12b765e28
commit 4da462dcdc
1 changed files with 5 additions and 5 deletions
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10
plat/st/stm32mp2/aarch64/stm32mp2_helper.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
* Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -65,13 +65,13 @@ func plat_crash_console_init
str x0, [x1]
1:
ldr x0, [x1]
ands x2, x0, x2
tst x0, #DEBUG_UART_RST_BIT
beq 1b
bic x2, x2, #DEBUG_UART_RST_BIT
str x2, [x1]
bic x0, x0, #DEBUG_UART_RST_BIT
str x0, [x1]
2:
ldr x0, [x1]
ands x2, x0, x2
tst x0, #DEBUG_UART_RST_BIT
bne 2b
/* Enable GPIOs for UART TX */
mov_imm x1, (RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)