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15228 commits

Author SHA1 Message Date
Chris Kay
73f7b7ddbe fix(cot-dt2c): fix various breakages
This change fixes several breakages that were introduced in some build
configurations by the introduction of the cot-dt2c tool.

Some Python environments cannot be managed directly via `pip`, and
invocations of `make`, including `make distclean`, would cause errors
along the lines of:

    error: externally-managed-environment

    × This environment is externally managed
    ╰─> To install Python packages system-wide, try apt install
        python3-xyz, where xyz is the package you are trying to
        install.

This change has been resolved by ensuring that calls to the cot-dt2c
tool from the build system happen exclusively through Poetry, which
automatically sets up a virtual environment that *can* be modified.

Some environments saw the following error when building platforms where
the cot-dt2c tool was used:

    make: *** No rule to make target '<..>/debug/bl2_cot.c', needed
    by '<..>/debug/bl2/bl2_cot.o'.  Stop.

Additionally, environments with a more recent version of Python saw the
following error:

      File "<...>/lib/python3.12/site-packages/cot_dt2c/cot_parser.py",
      line 637, in img_to_c
        if ifdef:
           ^^^^^
    NameError: name 'ifdef' is not defined

Both of these errors have now been resolved by modifications to the
build system and the cot-dt2c tool to enable preprocessing of the device
tree source file before it is processed by the tool.

As a consequence of this change, the `pydevicetree` library is no longer
vendored into the repository tree, and we instead pull it in via a
dependency in Poetry.

This change also resolves several MyPy warnings and errors related to
missing type hints.

Change-Id: I72b2d01caca3fcb789d3fe2549f318a9c92d77d1
Signed-off-by: Chris Kay <chris.kay@arm.com>
2024-08-28 09:56:59 +00:00
Manish V Badarkhe
e19977d664 fix(cot-dt2c): use processed Device Tree source file as input
Update the test files to eliminate the use of preprocessor macros,
as the tool now requires processed output. The documentation has
also been revised accordingly.

Additionally, remove the Device Tree Source test files that were
added to test the #ifdef conditions.

Change-Id: I13a682db20e5e44170fc25a2e2dbedd45b9c7321
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2024-08-27 12:50:20 +01:00
Yann Gautier
8fb91783ff Merge "fix(intel): add in missing ECC register" into integration 2024-08-23 14:45:12 +02:00
Jit Loon Lim
4683946015 fix(intel): add in missing ECC register
This patch is to add in missing ECC register (INITSTAT)

Change-Id: Iecf03dc9597ec2884901c132fb9cef7e90ab06a0
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
2024-08-23 13:41:25 +02:00
Mark Dykes
44418fce30 Merge changes from topics "rockchip", "rockchip-rk3588" into integration
* changes:
  feat(rk3588): support SCMI for clock/reset domain
  feat(rk3588): support rk3588
2024-08-22 21:53:05 +02:00
Madhukar Pappireddy
d76d27e978 Merge changes from topic "stm32mp2_bl2_updates" into integration
* changes:
  feat(stm32mp2): load fw-config file
  feat(stm32mp2): add fw-config compilation
  feat(stm32mp2-fdts): add fw-config files for STM32MP257F-EV1
  feat(stm32mp2-fdts): add fw-config file
  feat(stm32mp2-fdts): add clock tree for STM32MP257F-EV1
  feat(stm32mp2): enable DDR sub-system clock
  feat(stm32mp2): add fixed regulators support
  feat(stm32mp2): print board info
  feat(stm32mp2): display CPU info
  feat(stm32mp2): get chip ID
  feat(stm32mp2): add BL2 boot first steps
  feat(stm32mp2): add defines for the PWR peripheral
  feat(stm32mp2-fdts): add SD-card and eMMC support on STM32MP257F-EV1
  feat(stm32mp2-fdts): add sdmmc pins definition
  feat(stm32mp2-fdts): add sdmmc nodes in SoC DT file
  feat(stm32mp2-fdts): add io_policies
  feat(stm32mp2-fdts): remove pins-are-numbered
2024-08-22 18:38:03 +02:00
Mark Dykes
44c5f8e582 Merge changes I23bdbbe1,Ic22ab741 into integration
* changes:
  feat(intel): enable VAB support for Intel products
  feat(intel): add in SHA384 authentication
2024-08-22 17:15:53 +02:00
Madhukar Pappireddy
5eac9fea5e Merge changes from topic "nxp-drivers/add-linflex-clk" into integration
* changes:
  feat(nxp-clk): enable UART clock
  feat(nxp-clk): add PERIPH PLL enablement
2024-08-22 15:09:16 +02:00
Joanna Farley
0c499d354f Merge "fix(xilinx): fix OVERRUN coverity violation" into integration 2024-08-22 08:55:02 +02:00
Madhukar Pappireddy
021cdbfbd4 Merge changes from topic "jc/refact_el1_ctx" into integration
* changes:
  feat(cm): enhance the cpu_context memory report
  refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1
2024-08-21 21:55:56 +02:00
Mark Dykes
f538a096ca Merge "fix(intel): update sip smc config addr for agilex5" into integration 2024-08-21 18:03:19 +02:00
Jayanth Dodderi Chidanand
781e1a44e0 feat(cm): enhance the cpu_context memory report
Currently, as part of the context_memory report, we explicitly
list the EL3, EL1 and EL2 registers and memory usage per CPU
for each world. The remaining bits in the cpu_context_t structure
are grouped and listed as other section.

This patch enhances this part, by individually listing all the
remaining bits (GPREGS, PAUTH_REGS) separately providing
a much detailed overview of the context memory consumption
amongst the registers.

The patch has been tested on the CI with the following patch
and the results are summarised precisely.
[https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/28849]

Change-Id: I16f210b605ddd7900600519520accf1ccd057bc7
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
2024-08-21 16:43:16 +01:00
Jayanth Dodderi Chidanand
a0674ab081 refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1
* Currently, EL1 context is included in cpu_context_t by default
  for all the build configurations.
  As part of the cpu context structure, we hold a copy of EL1, EL2
  system registers, per world per PE. This context structure is
  enormous and will continue to grow bigger with the addition of
  new features incorporating  new registers.

* Ideally, EL3 should save and restore the system registers at its next
  lower exception level, which is EL2 in majority of the configurations.

* This patch aims at optimising the memory allocation in cases, when
  the members from the context structure are unused. So el1 system
  register context must be omitted when lower EL is always x-EL2.

* "CTX_INCLUDE_EL2_REGS" is the internal build flag which gets set,
  when SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1.
  It indicates, the system registers at EL2 are context switched for
  the respective build configuration. Here, there is no need  to save
  and restore EL1 system registers, while x-EL2 is enabled.

Henceforth, this patch addresses this issue, by taking out the EL1
context at all possible places, while EL2 (CTX_INCLUDE_EL2_REGS) is
enabled, there by saving memory.

Change-Id: Ifddc497d3c810e22a15b1c227a731bcc133c2f4a
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
2024-08-21 16:35:27 +01:00
Mark Dykes
31826ba221 Merge "fix(cpus): workaround for Cortex-A720 erratum 2792132" into integration 2024-08-21 16:41:19 +02:00
Manish V Badarkhe
5fba09ccb0 Merge "chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code" into integration 2024-08-21 16:36:30 +02:00
Jayanth Dodderi Chidanand
a0d9a973a4 chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code
SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to write and read into these context entries, looks
repetitive and is invoked at most places.
This section is refactored to bring them under a static procedure,
keeping the code neat and easier to maintain.

Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
2024-08-21 08:45:25 +01:00
Manish V Badarkhe
4b6e4e618e Merge changes from topic "mp/simd_ctxt_mgmt" into integration
* changes:
  feat(fvp): allow SIMD context to be put in TZC DRAM
  docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
  feat(fvp): add Cactus partition manifest for EL3 SPMC
  chore(simd): remove unused macros and utilities for FP
  feat(el3-spmc): support simd context management upon world switch
  feat(trusty): switch to simd_ctx_save/restore apis
  feat(pncd): switch to simd_ctx_save/restore apis
  feat(spm-mm): switch to simd_ctx_save/restore APIs
  feat(simd): add rules to rationalize simd ctxt mgmt
  feat(simd): introduce simd context helper APIs
  feat(simd): add routines to save, restore sve state
  feat(simd): add sve state to simd ctxt struct
  feat(simd): add data struct for simd ctxt management
2024-08-20 22:30:06 +02:00
Madhukar Pappireddy
bd3944366a Merge "feat(nxp-drivers): add Linflex flush callback" into integration 2024-08-20 16:55:32 +02:00
Ghennadi Procopciuc
e4462dae81 feat(nxp-clk): enable UART clock
Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.

Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
2024-08-20 16:28:56 +03:00
Ghennadi Procopciuc
8653352ad7 feat(nxp-clk): add PERIPH PLL enablement
Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or FXOSC oscillators. It has eight outputs (PHIs) and
their frequencies can be controlled programmatically using output
dividers. An additional output clocks the PERIPH DFS using the VCO
frequency of the PERIPH PLL.

Change-Id: I637294b2da94f35e95dc1750dad36c129a276bb9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
2024-08-20 16:28:56 +03:00
Jay Buddhabhatti
e27b9491f3 fix(xilinx): fix OVERRUN coverity violation
This change fixes below MISRA violation:
CID 441243:  Memory - corruptions  (OVERRUN)
Overrunning callee's array of size 7 by passing argument "7UL" in call to
"pm_ipi_send_sync".

Change-Id: Ie7fd9ccad058e97eb4b36c4f0e77be8bfb3e6006
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
2024-08-20 04:57:13 -07:00
Ghennadi Procopciuc
95ac568b61 feat(nxp-drivers): add Linflex flush callback
Implement a flush callback for the Linflex UART driver to avoid cases
where the BL31 stage reinitializes the console while there is ongoing TX
initiated by the BL2.

Change-Id: Ic49852f809198362de1f993474c7c45f1439dc98
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
2024-08-20 07:57:47 +03:00
Arvind Ram Prakash
b1bde25ed9 fix(cpus): workaround for Cortex-A720 erratum 2792132
Cortex-A720 erratum 2792132 is a Cat B erratum that is present
in revision r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[26] of the CPUACTLR2_EL1 to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8d11fe65a2ab5f79244cc3395d0645f77256304c
2024-08-19 15:19:08 -05:00
Madhukar Pappireddy
b4c23adf58 feat(fvp): allow SIMD context to be put in TZC DRAM
This patch demonstrates the capability of SEPARATE_SIMD_SECTION build
flag through which the memory intensive SIMD context data structures
are allocated in a separate section withtin the TZC DRAM space.

Change-Id: Idf3f232a7960a8f84f279d496c76953a6dad2009
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-08-19 11:12:20 -05:00
Madhukar Pappireddy
50fba2db86 docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
This patch documents the support for the newly introduced
CTX_INCLUDE_SVE_REGS build flag. Since this build flag is influenced
by other build flags, the relevant sections have been updated with
proper guidance.

This patch also documents the SEPARATE_SIMD_SECTION build flag.

Change-Id: I07852c4a65239c6a9c6de18a95c61aac429bec1c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-08-19 11:12:06 -05:00
Madhukar Pappireddy
51346236c3 feat(fvp): add Cactus partition manifest for EL3 SPMC
This patch adds the SP partition manifest to boot Cactus SP on
EL3 SPMC to be used with FVP platform.

Change-Id: I88b36f6ac21ebba7fa93aef75dad74bb9ee5c944
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-08-19 11:11:43 -05:00
Madhukar Pappireddy
3e840ec874 chore(simd): remove unused macros and utilities for FP
Now that we have switched to simd context save/restore apis
which uses simd_context_t data structures, we can safely remove
any macros, helpers and utilities used in the old way of
FPU context management.

Change-Id: I27a636dd07bf5c4cb99fd25b9a204d55b525b677
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-08-19 11:11:38 -05:00
Madhukar Pappireddy
59bdcc58c3 feat(el3-spmc): support simd context management upon world switch
This patch performs necessary simd context management operations for
context switch from NWd to SWD and vice versa.

Change-Id: Ife01fffc4e2a7f3deb9b6273424161c225fdbbfb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-08-19 11:11:14 -05:00
Madhukar Pappireddy
7461025985 feat(trusty): switch to simd_ctx_save/restore apis
Change-Id: Ifa72334c4793965c23a20d31ff6dff258f72ddcb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-08-19 11:11:14 -05:00
Madhukar Pappireddy
a9b64ed969 feat(pncd): switch to simd_ctx_save/restore apis
Change-Id: I662c0b35e938f8b2013ec60f863de55445f559da
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-08-19 11:11:14 -05:00
Madhukar Pappireddy
e6e348689a feat(spm-mm): switch to simd_ctx_save/restore APIs
This patch demonstrates the trivial changes to transparently switch
the fpregs_context_* helpers to simd_ctx_* helpers.

Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I14bda6bd0ead1f34a570b59be8dec3ac40891c20
2024-08-19 11:11:14 -05:00
Madhukar Pappireddy
3524d0742e feat(simd): add rules to rationalize simd ctxt mgmt
Illegal combinations of build flags associated with SIMD context
management are flagged by the build system.

Change-Id: I3192af3889e1e864c7875778616e167ba6894195
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-08-19 11:11:06 -05:00
Madhukar Pappireddy
308ebfa188 feat(simd): introduce simd context helper APIs
This patch adds the common API to save and restore FP and SVE. When SVE
is enabled we save and restore SVE which automatically covers FP. If FP
is enabled while SVE is not, then we save and restore FP only.

The patch uses simd_ctx_t to save and restore both FP and SVE which
means developers need not use fp or sve routines directly. Once all the
calls to fpregs_context_* are replaced with simd_ctx_*, we can remove
fp_regs_t data structure and macros (taken care in a following patch).

simd_ctx_t is currently allocated in section of its own. This will go
into  BSS section by default but platform will have option of relocating
it to a different section by overriding in plat.ld.S.

Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I090f8b8fa3862e527b6c40385249adc69256bf24
2024-08-19 11:10:10 -05:00
Madhukar Pappireddy
6d5319afec feat(simd): add routines to save, restore sve state
This adds assembly routines to save and restore SVE registers. In order
to share between FPU and SVE the code to save and restore FPCR and
FPSR, the patch converts code for those registers into macro.
Since we will be using simd_ctx_t to save and restore FPU also, we use
offsets in simd_ctx_t for FPSR and FPCR. Since simd_ctx_t has the same
structure at the beginning as fp_regs_t, those offsets should be the
same as CTX_FP_* offsets, when SVE is not enabled. Note that the code
also saves and restores FPEXC32 reg along with FPSR and FPCR.

Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I120c02359794aa6bb6376a464a9afe98bd84ae60
2024-08-19 11:10:10 -05:00
Madhukar Pappireddy
42422622f9 feat(simd): add sve state to simd ctxt struct
This patch extends the simd data structure to hold the SVE state. A new
build flag CTX_INCLUDE_SVE_REGS is introduced in this patch to enable
SVE context management.

Necessary precautions are taken such as ensuring the field offsets are
not changed and necessary padding is added for alignment reasons.

Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I54f5222c7d8c68638105003f68caa511d347cd60
2024-08-19 11:10:10 -05:00
Madhukar Pappireddy
841533dd53 feat(simd): add data struct for simd ctxt management
From a context management perspective, we refer to SVE and FP state
as SIMD. SVE can be considered as a superset of FP/NEON functionality
and there is a architectural dependency between the two due to the fact
that FP registers occupy the bottom 128 bits of SVE Z vector registers.

This patch introduces a new data structure to hold the FP state of a CPU
as needed for context management operations during world switch events.
It will evolve in next patches to capture the SVE state as well.

Having this unified data structure is necessary for us to implement
SIMD context management while catering to various build configurations.

Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: If2a9a7526883780df49bbd3dade2f09f7c3d95ae
2024-08-19 11:10:10 -05:00
Manish V Badarkhe
553b70c3ef Merge changes from topic "ar/asymmetricSupport" into integration
* changes:
  feat(tc): enable trbe errata flags for Cortex-A520 and X4
  feat(cm): asymmetric feature support for trbe
  refactor(errata-abi): move EXTRACT_PARTNUM to arch.h
  feat(cpus): workaround for Cortex-A520(2938996) and Cortex-X4(2726228)
  feat(tc): make SPE feature asymmetric
  feat(cm): handle asymmetry for SPE feature
  feat(cm): support for asymmetric feature among cores
  feat(cpufeat): add new feature state for asymmetric features
2024-08-19 11:56:49 +02:00
Manish Pandey
74dc801d4b feat(tc): enable trbe errata flags for Cortex-A520 and X4
Enable following erratas as per the TARGET_PLATFORM of TC
 - ERRATA_A520_2938996
 - ERRATA_X4_2726228

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ia552473740c34867dd9fd619faf378adcb784821
2024-08-17 09:38:55 +01:00
Arvind Ram Prakash
721249b0c0 feat(cm): asymmetric feature support for trbe
This patch checks if the Errata 2938996(Cortex-A520) , 2726228(Cortex-X4)
applies to cores and if affected applies the errata workaround which
disables TRBE.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I53b037839820c8b3a869f393588302a365d5b97c
2024-08-17 09:38:44 +01:00
Arvind Ram Prakash
1073bf3d8c refactor(errata-abi): move EXTRACT_PARTNUM to arch.h
This patch moves EXTRACT_PARTNUM from errata abi includes
to arch.h which is part of common includes

Change-Id: Id8bbaf21566f3145a75cfa0dafec6823ed2df3a9
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
2024-08-17 09:38:31 +01:00
Arvind Ram Prakash
4a97ff5111 feat(cpus): workaround for Cortex-A520(2938996) and Cortex-X4(2726228)
This patch implements errata functions for two errata, both of them
disable TRBE as a workaround. This patch doesn't have functions
that disable TRBE but only implemented helper functions that are
used to detect cores affected by Errata 2938996(Cortex-A520) & 2726228(Cortex-X4)

Cortex-X4 SDEN documentation:
    https://developer.arm.com/documentation/SDEN2432808/latest

Cortex-A520 SDEN Documentation:
    https://developer.arm.com/documentation/SDEN-2444153/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8f886a1c21698f546a0996c719cc27dc0a23633a
2024-08-17 09:37:55 +01:00
Manish Pandey
7754b770cf feat(tc): make SPE feature asymmetric
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf0fecb2a97cb0f3508e01e0907e61e3c437ac00
2024-08-17 09:36:23 +01:00
Manish Pandey
188f8c4b60 feat(cm): handle asymmetry for SPE feature
With introduction of FEAT_STATE_CHECK_ASYMMETRIC, the asymmetry of cores
can be handled. SPE is one of the features which can be asymmetric
across cores.

Add a function to handle this asymmetry by re-visting the feature
presence on running core.
There are two possible cases:
 - If the primary has the feature and secondary does not have it then,
   the feature needs to be disabled.
 - If the primary does not have the feature and secondary has it then,
   the feature need to be enabled

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibb2b88b5ef63b3efcb80801898ae8d8967e5c271
2024-08-17 09:36:10 +01:00
Manish Pandey
2f41c9a7be feat(cm): support for asymmetric feature among cores
TF-A assumes that all the cores in a platform has architecture feature
parity, this is evident by the fact that primary sets up the
Non-secure context of secondary cores.

With changing landscape of platforms (e.g. big/little/mid cores), we are
seeing more and more platforms which has feature asymmetry among cores.
There is also a scenario where certain CPU erratum only applies to one
type of cores and requires a feature to be disabled even it supports
the feature.

To handle these scenarios, introduce a hook in warmboot path which would
be called on the running CPU to override any feature disparity in the
NS context stashed up by primary. Note that, re-checking of feature for
Secure/Realm context is not required as the context is created on
running core itself.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I5a01dbda528fa8481a00fdd098b58a7463ed0e22
2024-08-17 09:35:53 +01:00
Manish Pandey
43d1d951dd feat(cpufeat): add new feature state for asymmetric features
Introduce a new feature state CHECK_ASYMMETRIC to cater for the features
which are asymmetric across cores. This state is useful for platforms
which has architectural asymmetric cores (A feature is only present in
one type of core e.g. big).
This state is similar to FEAT_STATE_CHECK (dynamic detection) except
that feature state is also checked on each core during warmboot path and
override the context (just for asymmetric features) which was setup by
core executing CPU_ON call.

Only Non-secure context will be re-checked as secure and realm context
is created on same core.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ic78a0b6ca996e0d7881c43da1a6a0c422f528ef3
2024-08-17 09:35:13 +01:00
Manish V Badarkhe
2d4f264ba5 Merge changes from topic "romlib-fixes" into integration
* changes:
  fix(romlib): wrap indirectly included functions
  fix(arm): remove duplicate jumptable entry
2024-08-17 10:09:06 +02:00
Mark Dykes
abeb8ad6c1 Merge "fix(cpus): workaround for Cortex-A720 erratum 2844092" into integration 2024-08-17 00:18:54 +02:00
Mark Dykes
28e4ec1b39 Merge "fix(cpus): workaround for Cortex-X4 erratum 2816013" into integration 2024-08-17 00:18:02 +02:00
Manish Pandey
a0c7bee6e6 Merge "docs(maintainers): update Corstone-1000 maintainers" into integration 2024-08-16 18:01:58 +02:00
Manish Pandey
9b1f2c7957 Merge "fix(rdv3): remove NEED_* from RD-V3 makefile" into integration 2024-08-16 18:00:12 +02:00